CN116364678B - Heat dissipation structure and device compatible with embedded micro-channel by liquid through silicon vias and manufacturing method thereof - Google Patents

Abstract

The invention relates to the field of heat dissipation. The invention provides a heat dissipation structure and a device compatible with a liquid through silicon via and an embedded micro-channel and a manufacturing method thereof, wherein the heat dissipation structure comprises: the substrate comprises a first outer bottom plate and a first inner bottom plate, and a first turbulent flow column array is etched in the substrate; the heat sink comprises a second outer bottom plate and a second inner bottom plate, and a second turbulent flow column array is etched in the heat sink; and the multilayer integrated circuit chip is vertically stacked and arranged between the substrate and the heat sink, the multilayer integrated circuit chip is etched with a signal through silicon via array and a liquid through silicon via array, the signal through silicon via array is connected with the substrate through the convex points, and the liquid through silicon via array is respectively connected with the heat sink and the substrate through the liquid micro convex points. The heat radiation structure of the invention is composed of the liquid silicon through hole, the micro-channel heat sink embedded with the turbulent flow column and the base plate, thereby improving the heat radiation performance and the system reliability of the integrated circuit.

Description

Liquid through-silicon via compatible heat dissipation structure and device of embedded micro-channel and its manufacturing method

technical field

The present invention relates to the field of heat dissipation, and more specifically refers to a heat dissipation structure compatible with embedded micro-channels through liquid silicon vias, a motherboard including the same, a liquid-cooled motherboard, a liquid-cooled server, and a method for making the same.

Background technique

In order to further improve integration and reduce power consumption, 3D integration based on TSV (Through Si Via) has attracted extensive attention. In the limited chip area, 3D integration increases the integration density, and the vertical interconnection of through-silicon vias reduces the interconnection length, but at the same time, 3D stacking leads to higher thermal density, which poses challenges to the heat dissipation performance of the chip.

At present, the conventional way is to add a heat sink and a heat sink on the top of the 3D IC (Integrated Circuit, integrated circuit) chip, or add a TTSV (Thermal Through Si Via, thermal conduction silicon via) inside the 3D IC chip, or add a heat sink on the chip substrate A microchannel with a width of 100 microns is etched on the top, and a cooling liquid is introduced. As the cooling liquid circulates inside the microchannel, the heat of the chip is taken away, thereby achieving cooling. However, the heat dissipation efficiency of the microchannel depends on its size. , the larger the size and the higher the height, the better the heat dissipation performance, but at the same time increasing the thickness of the chip will intensify the heat accumulation. At the same time, there is space competition in the mixed layout of the microchannel and the through-silicon via array, which requires precise chip layout and planning. A very high process is required to prevent the crossing of microchannels and TSVs. In addition, TSVs transmit electrical signals in the vertical direction, and the electrothermal coupling effect between TSV arrays is significant, so heat is distributed along the vertical direction. However, microchannels are only etched in the substrate to conduct heat transfer to the same layer of chips, and there is an insulating layer between chips of different layers, which will lead to uneven heat distribution in the vertical direction, and may even cause hot spots, which will affect the heat dissipation of the chip. affect stability.

Contents of the invention

In view of this, the purpose of the embodiment of the present invention is to propose a liquid through-silicon via compatible embedded micro-channel heat dissipation structure, a motherboard including it, a liquid-cooled motherboard, a liquid-cooled server, and a method for making the same. Through-holes, microfluidic heat sinks embedded with spoilers, and substrates together constitute a heat dissipation structure, and at the same time provide a three-dimensional active heat dissipation structure and its manufacturing process based on this heat dissipation method, through multi-dimensional, multi-scale balanced active heat dissipation To improve the heat dissipation efficiency of 3D integrated circuit chips, it can improve the heat dissipation performance and system reliability of 3D integrated circuit chips, and because the heat sink and substrate are both silicon, the internal microchannel structure remains consistent, thereby reducing the overall process of the structure. Complexity can improve chip yield.

Based on the above purpose, an aspect of the embodiments of the present invention provides a liquid through silicon via compatible embedded micro-channel heat dissipation structure, including the following components: a base, the base includes a first outer bottom plate and a first inner bottom plate, the A first spoiler column array is etched in the substrate; a heat sink includes a second outer bottom plate and a second inner bottom plate, and a second spoiler column array is etched in the heat sink; and a multilayer integrated circuit chip, the multi-layer integrated circuit chip is vertically stacked and arranged between the base and the heat sink, the multi-layer integrated circuit chip is etched with a signal through-silicon via array and a liquid through-silicon via array, the signal The TSV array is connected to the base through bumps, and the liquid TSV array is respectively connected to the heat sink and the base through liquid micro bumps.

In some implementations, the second array of spoiler posts is etched on the second inner bottom plate, the second array of spoiler posts includes first spoiler posts and second spoiler posts, the second The spoiler post is higher than the first spoiler post.

In some embodiments, the shape of the first spoiler post is the same as that of the second spoiler post.

In some embodiments, the shape of the first spoiler column is a cylinder or a regular hexagonal column.

In some embodiments, the heat sink is configured to hold a cooling liquid, which is a liquid with high thermal conductivity.

In some embodiments, the heat sink is connected to the multilayer integrated circuit chip through solder joints.

In some embodiments, the second outer bottom plate and the second inner bottom plate are made of the same material, and the second outer bottom plate is made of silicon, diamond, thermally conductive ceramics or organic resin.

In some embodiments, the materials of the second outer bottom plate and the second inner bottom plate are different.

In some embodiments, the material of the second outer bottom plate is glass.

In some embodiments, the layout of the first array of spoiler posts is the same as that of the second array of spoiler posts.

In some embodiments, the layout of the second spoiler column array is the same as that of the signal TSV array and the liquid TSV array.

In some embodiments, an insulating layer is filled on the outer surfaces of the signal TSV array and the liquid TSV array.

In some embodiments, a liquid inlet is arranged at one end of the diagonal line of the second outer bottom plate, and a liquid outlet is arranged at one end of the diagonal line of the first outer bottom plate.

Another aspect of the embodiments of the present invention provides a motherboard, including the liquid through-silicon via compatible embedded micro-channel heat dissipation structure described in any one of the above.

Another aspect of the embodiments of the present invention provides a liquid-cooled motherboard, including the liquid through-silicon via-compatible embedded micro-channel heat dissipation structure described in any one of the above items.

Still another aspect of the embodiments of the present invention provides a liquid-cooled server, including the heat dissipation structure of the liquid through-silicon vias compatible with embedded micro-channels described in any one of the above.

In yet another aspect of the embodiments of the present invention, a method for manufacturing a liquid through-silicon via compatible embedded micro-channel heat dissipation structure is provided, including the following steps: etching a second spoiler column on the surface of the second inner bottom plate of the heat sink The array constitutes a micro-channel, and the liquid through-silicon hole array interface is etched on the second outer bottom plate of the heat sink to seal the micro-channel, and a liquid inlet is set on the heat sink; the multi-layer integrated chips are vertically stacked, and the The multi-layer integrated chip etches the signal TSV array and the liquid TSV array; etches the first spoiler column array on the lower surface of the first outer bottom plate of the substrate to form a second micro-channel, and the second micro-channel sealing, and setting a liquid outlet on the substrate; and interconnecting the signal TSV array with the substrate, and interconnecting the liquid TSV array with the substrate and the heat sink respectively.

In some embodiments, the sealing the micro-channel includes: bonding the second outer bottom plate to the micro-channel structure through a wafer-level bonding process.

In some embodiments, the etching the signal TSV array and the liquid TSV array on the multi-layer integrated chip includes: nesting and distributing the signal TSV array and the liquid TSV array.

In some embodiments, the etching the signal TSV array and the liquid TSV array on the multilayer integrated chip includes: using the TSV deep process to etch the signal TSV array and the liquid silicon via array inside the multilayer integrated chip. via array.

In some embodiments, the interconnecting the liquid TSV arrays with the substrate and the heat sink respectively includes: respectively interconnecting the liquid TSV arrays with the heat sink through a liquid micro-bump process. interconnected with the substrate.

In some embodiments, the manufacturing method further includes: connecting the heat sink and the multilayer integrated chip by soldering.

The present invention has the following beneficial technical effects: the heat dissipation structure is composed of the liquid through-silicon hole, the micro-channel heat sink embedded with the spoiler column, and the substrate, and a three-dimensional active heat dissipation structure based on the heat dissipation method and its manufacturing process are provided at the same time. Improving the heat dissipation efficiency of 3D integrated circuit chips through multi-dimensional and multi-scale balanced active heat dissipation can improve the heat dissipation performance and system reliability of 3D integrated circuit chips. The structure remains consistent, thereby reducing the overall process complexity of the structure and improving the chip yield.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and those skilled in the art can obtain other embodiments according to these drawings without any creative effort.

FIG. 1 is a schematic diagram of an embodiment of a liquid through-silicon via compatible embedded micro-channel heat dissipation structure provided by the present invention;

Fig. 2 is a schematic diagram of the top heat sink and the bumps below it provided by the embodiment of the present invention;

3 is a schematic diagram of a spoiler column array in a top heat sink provided by an embodiment of the present invention;

4 is a schematic diagram of a bump array under the top heat sink provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of an embodiment of a manufacturing method of a liquid through silicon via compatible embedded microfluidic channel heat dissipation structure provided by the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are to distinguish two entities with the same name but different parameters or parameters that are not the same, see "first" and "second" It is only for the convenience of expression, and should not be construed as a limitation on the embodiments of the present invention, which will not be described one by one in the subsequent embodiments.

According to the first aspect of the embodiments of the present invention, an embodiment of a liquid through-silicon via compatible embedded micro-channel heat dissipation structure is proposed. FIG. 1 is a schematic diagram of an embodiment of a liquid through-silicon via compatible embedded micro-channel heat dissipation structure provided by the present invention. As shown in Figure 1, the embodiment of the present invention includes the following components:

A base 1, the base 1 includes a first outer bottom plate 11 and a first inner bottom plate 12, and a first spoiler column array (including 13 and 14) is etched in the base 1;

A heat sink 2, the heat sink 2 includes a second outer bottom plate 21 and a second inner bottom plate 22, and a second spoiler column array (including 23 and 24) is etched in the heat sink 2; and

A multi-layer integrated circuit chip 3, the multi-layer integrated circuit chip 3 is vertically stacked and arranged between the substrate 1 and the heat sink 2, and a signal through-silicon via array 31 is etched in the multi-layer integrated circuit chip 3 and a liquid TSV array 32, the signal TSV array 31 is connected to the substrate 1 through bumps 4, and the liquid TSV array 32 is respectively connected to the heat sink 2 and the heat sink 2 through liquid micro bumps 5. The substrate 1 is connected.

That is to say, in the embodiment of the present invention, a heat sink 2 that can accommodate a cooling liquid is provided on the top layer of the liquid through-silicon via compatible embedded micro-channel heat sink, and the second spoiler is etched in the heat sink 2 of the embodiment of the present invention. Column array (composed of 23 and 24); under the heat sink 2 of the embodiment of the present invention is a vertically stacked multilayer integrated circuit chip 3; a signal through-silicon via array 31 and liquid are etched in the stacked multilayer integrated circuit chip 3 Through-silicon via array 32; in the embodiment of the present invention, the signal through-silicon via array 31 is connected to the substrate 1 through the metal bump 4; in the embodiment of the present invention, the liquid through-silicon via array 32 is connected to the top heat sink 2 and the top heat sink through the liquid micro-bump 5 The bottom base 1 is connected to communicate with the cooling liquid channel; in the embodiment of the present invention, the bottom base 1 is embedded with a first spoiler column array (composed of 13 and 14 ) corresponding to the top heat sink 2 .

A first filling layer is made between the multilayer integrated circuit chip 3 and the substrate 1 , and a second filling layer is made between the multilayer integrated circuit chip 3 and the heat sink 2 .

In some embodiments, the second spoiler post array is etched on the second inner bottom plate 22, the second spoiler post array includes a first spoiler post 23 and a second spoiler post 24, so The second spoiler post 24 is higher than the first spoiler post 23 .

In some embodiments, the first spoiler column array is etched on the first inner bottom plate 12, the second spoiler column array includes a third spoiler column 13 and a fourth spoiler column 14, so The fourth spoiler post 14 is higher than the third spoiler post 13 .

In some embodiments, a liquid inlet is provided at one diagonal end of the second outer bottom plate 21 , and a liquid outlet is arranged at one diagonal end of the first outer bottom plate 11 . The liquid inlet and liquid outlet in the embodiment of the present invention are only exemplary. In other embodiments, the positions of the liquid inlet and the liquid outlet can be changed, and it is only necessary to meet the requirement that the liquid flows from the top heat sink 2 and then from the bottom substrate 1 Just flow out.

In some implementations, the heat sink 2 is connected to the multilayer integrated circuit chip 3 through solder joints 6 .

FIG. 2 is a schematic diagram of the top heat sink and the bumps below it provided by the embodiment of the present invention. As shown in Figure 2, the first spoiler column (not shown in the figure) and the second spoiler column 24 are alternately arranged to form the second spoiler column array in the heat sink 2, and the liquid micro-bump 5 on the top is used to connect the liquid TSV array 32 and the top heat sink 2 , and the solder joints 6 are used to connect the multilayer integrated circuit chip 3 and the top heat sink 2 .

FIG. 3 is a schematic diagram of a spoiler array in a top heat sink provided by an embodiment of the present invention, and FIG. 4 is a schematic diagram of a bump array under a top heat sink provided by an embodiment of the present invention. The dotted lines in FIG. 3 and FIG. 4 are auxiliary dotted lines, which are only used to see the arrangement of the second spoiler array more intuitively, and have no other meanings. Fig. 3 is a vertical view from the top of the heat sink 2. As shown in Fig. 3, the dots with crossed solid lines in the circle represent the second spoiler columns 24, which are evenly arranged on the heat sink 2 for Supporting the space between the second outer bottom plate 21 and the second inner bottom plate 22 in the heat sink 2 , the hollow dots indicate the first spoiler columns 23 , which are evenly arranged on the heat sink 2 . Fig. 4 is a vertical view from the bottom of the heat sink 2 upwards. As shown in Fig. 4, the liquid micro-bumps 5 used to connect the liquid TSV array 32 and the top heat sink 2 are evenly arranged on the bottom of the heat sink 2, The solder joints 6 connecting the multilayer integrated circuit chip 3 and the top heat sink 2 are evenly arranged around the liquid micro bumps 5 .

In some embodiments, the first spoiler column 23 and the second spoiler column 24 have the same shape. In some embodiments, the shape of the first spoiler column 23 is a cylinder or a regular hexagon.

In some embodiments, the shape of the first spoiler column 23 is different from that of the second spoiler column 24 . For example, the shape of the first spoiler post 23 is cylindrical, and the shape of the second spoiler post 24 is a regular hexagonal post; or, the shape of the first spoiler post 23 is a regular hexagonal post, The shape of the second spoiler column 24 is cylindrical. The shapes of the first spoiler post 23 and the second spoiler post 24 in the embodiment of the present invention are only exemplary. In other embodiments, the first spoiler post 23 and the second spoiler post 24 can be set as other shapes.

In some embodiments, the heat sink 2 is configured to accommodate a cooling liquid, which is a liquid with high thermal conductivity. The high thermal conductivity in the embodiment of the present invention is a general understanding in the art, and liquids with high thermal conductivity are water, EGW (ethylene glycol and aqueous solution), PGW (propylene glycol and aqueous solution) and the like.

In some embodiments, the second outer bottom plate 21 and the second inner bottom plate 22 are made of the same material, and the second outer bottom plate 21 is made of silicon, diamond, thermally conductive ceramics or organic resin.

In some embodiments, the materials of the second outer bottom plate 21 and the second inner bottom plate 22 are different. In some embodiments, the material of the second outer bottom plate 21 is glass. The materials of the second outer bottom plate 21 and the second inner bottom plate 22 in the embodiment of the present invention are only exemplary. In other embodiments, the second outer bottom plate 21 and the second inner bottom plate 22 can be made of other materials.

In some embodiments, the layout of the first array of spoiler posts is the same as that of the second array of spoiler posts. That is to say, in the embodiment of the present invention, the in-plane distribution of the first spoiler array embedded in the bottom substrate 1 and the second spoiler array of the top heat sink 2 are consistent.

In some embodiments, the layout of the second spoiler column array is the same as that of the signal TSV array and the liquid TSV array. That is to say, in the embodiment of the present invention, the in-plane distribution of the second spoiler column array is consistent with the signal TSV array 31 and the liquid TSV array 32 inside the multilayer integrated circuit chip 3 .

In some embodiments, an insulating layer is filled on the outer surfaces of the signal TSV array and the liquid TSV array. The signal TSV array 31 and the liquid TSV array 32 in the embodiment of the present invention are all filled with an insulating layer, such as silicon dioxide, after etching.

The cooling liquid enters the heat sink 2 through the entrance of the second outer bottom plate 21 of the heat sink 2, enters the substrate 1 embedded with micro-channels through the channel of the liquid TSV array 32, and finally flows out from the outlet of the substrate 1 to take away the chip heat , the exit is not marked in the drawings.

The embodiment of the present invention consists of a liquid through-silicon via, a micro-channel heat sink embedded with a spoiler column, and a substrate to form a heat dissipation structure. At the same time, a three-dimensional active heat dissipation structure and its manufacturing process based on the heat dissipation method are provided. Through multi-dimensional, Multi-scale balanced active heat dissipation to improve the heat dissipation efficiency of 3D integrated circuit chips can improve the heat dissipation performance and system reliability of 3D integrated circuit chips, and because the heat sink and substrate are both silicon, the internal microfluidic structure remains consistent, Therefore, the process complexity of the overall structure is reduced, and the chip yield rate can be improved.

Based on the above purpose, the second aspect of the embodiments of the present invention proposes a motherboard, including the heat dissipation structure of liquid through silicon vias compatible with embedded micro-channels as described in any one of the above items.

The heat dissipation structure of liquid through-silicon vias compatible with embedded micro-channels includes the following components:

A base 1, the base 1 includes a first outer bottom plate 11 and a first inner bottom plate 12, and a first spoiler column array (including 13 and 14) is etched in the base 1;

A heat sink 2, the heat sink 2 includes a second outer bottom plate 21 and a second inner bottom plate 22, and a second spoiler column array (including 23 and 24) is etched in the heat sink 2; and

A multi-layer integrated circuit chip 3, the multi-layer integrated circuit chip 3 is vertically stacked and arranged between the substrate 1 and the heat sink 2, and a signal through-silicon via array 31 is etched in the multi-layer integrated circuit chip 3 and a liquid TSV array 32, the signal TSV array 31 is connected to the substrate 1 through bumps 4, and the liquid TSV array 32 is respectively connected to the heat sink 2 and the heat sink 2 through liquid micro bumps 5. The substrate 1 is connected.

That is to say, in the embodiment of the present invention, a heat sink 2 that can accommodate a cooling liquid is provided on the top layer of the liquid through-silicon via compatible embedded micro-channel heat sink, and the second spoiler is etched in the heat sink 2 of the embodiment of the present invention. Column array (composed of 23 and 24); under the heat sink 2 of the embodiment of the present invention is a vertically stacked multilayer integrated circuit chip 3; a signal through-silicon via array 31 and liquid are etched in the stacked multilayer integrated circuit chip 3 Through-silicon via array 32; in the embodiment of the present invention, the signal through-silicon via array 31 is connected to the substrate 1 through the metal bump 4; in the embodiment of the present invention, the liquid through-silicon via array 32 is connected to the top heat sink 2 and the top heat sink through the liquid micro-bump 5 The bottom base 1 is connected to communicate with the cooling liquid channel; in the embodiment of the present invention, the bottom base 1 is embedded with a first spoiler column array (composed of 13 and 14 ) corresponding to the top heat sink 2 .

In some embodiments, the second spoiler post array is etched on the second inner bottom plate 22, the second spoiler post array includes a first spoiler post 23 and a second spoiler post 24, so The second spoiler post 24 is higher than the first spoiler post 23 .

In some embodiments, the first spoiler column array is etched on the first inner bottom plate 12, the second spoiler column array includes a third spoiler column 13 and a fourth spoiler column 14, so The fourth spoiler post 14 is higher than the third spoiler post 13 .

In some embodiments, a liquid inlet is provided at one diagonal end of the second outer bottom plate 21 , and a liquid outlet is arranged at one diagonal end of the first outer bottom plate 11 . The liquid inlet and liquid outlet in the embodiment of the present invention are only exemplary. In other embodiments, the positions of the liquid inlet and the liquid outlet can be changed, and it is only necessary to meet the requirement that the liquid flows from the top heat sink 2 and then from the bottom substrate 1 Just flow out.

In some implementations, the heat sink 2 is connected to the multilayer integrated circuit chip 3 through solder joints 6 .

FIG. 2 is a schematic diagram of the top heat sink and the bumps below it provided by the embodiment of the present invention. As shown in Figure 2, the first spoiler column (not shown in the figure) and the second spoiler column 24 are alternately arranged to form the second spoiler column array in the heat sink 2, and the liquid micro-bump 5 on the top is used to connect the liquid TSV array 32 and the top heat sink 2 , and the solder joints 6 are used to connect the multilayer integrated circuit chip 3 and the top heat sink 2 .

FIG. 3 is a schematic diagram of a spoiler array in a top heat sink provided by an embodiment of the present invention, and FIG. 4 is a schematic diagram of a bump array under a top heat sink provided by an embodiment of the present invention. The dotted lines in FIG. 3 and FIG. 4 are auxiliary dotted lines, which are only used to see the arrangement of the second spoiler array more intuitively, and have no other meanings. Fig. 3 is a vertical view from the top of the heat sink 2. As shown in Fig. 3, the dots with crossed solid lines in the circle represent the second spoiler columns 24, which are evenly arranged on the heat sink 2 for Supporting the space between the second outer bottom plate 21 and the second inner bottom plate 22 in the heat sink 2 , the hollow dots indicate the first spoiler columns 23 , which are evenly arranged on the heat sink 2 . Fig. 4 is a vertical view from the bottom of the heat sink 2 upwards. As shown in Fig. 4, the liquid micro-bumps 5 used to connect the liquid TSV array 32 and the top heat sink 2 are evenly arranged on the bottom of the heat sink 2, The solder joints 6 connecting the multilayer integrated circuit chip 3 and the top heat sink 2 are evenly arranged around the liquid micro bumps 5 .

In some embodiments, the first spoiler column 23 and the second spoiler column 24 have the same shape. In some embodiments, the shape of the first spoiler column 23 is a cylinder or a regular hexagon.

In some embodiments, the shape of the first spoiler column 23 is different from that of the second spoiler column 24 . For example, the shape of the first spoiler post 23 is cylindrical, and the shape of the second spoiler post 24 is a regular hexagonal post; or, the shape of the first spoiler post 23 is a regular hexagonal post, The shape of the second spoiler column 24 is cylindrical. The shapes of the first spoiler post 23 and the second spoiler post 24 in the embodiment of the present invention are only exemplary. In other embodiments, the first spoiler post 23 and the second spoiler post 24 can be set as other shapes.

In some embodiments, the heat sink 2 is configured to accommodate a cooling liquid, which is a liquid with high thermal conductivity. The high thermal conductivity in the embodiment of the present invention is a general understanding in the art, and liquids with high thermal conductivity are water, EGW (ethylene glycol and aqueous solution), PGW (propylene glycol and aqueous solution) and the like.

In some embodiments, the second outer bottom plate 21 and the second inner bottom plate 22 are made of the same material, and the second outer bottom plate 21 is made of silicon, diamond, thermally conductive ceramics or organic resin.

In some embodiments, the materials of the second outer bottom plate 21 and the second inner bottom plate 22 are different. In some embodiments, the material of the second outer bottom plate 21 is glass. The materials of the second outer bottom plate 21 and the second inner bottom plate 22 in the embodiment of the present invention are only exemplary. In other embodiments, the second outer bottom plate 21 and the second inner bottom plate 22 can be made of other materials.

In some embodiments, the layout of the first array of spoiler posts is the same as that of the second array of spoiler posts. That is to say, in the embodiment of the present invention, the in-plane distribution of the first spoiler array embedded in the bottom substrate 1 and the second spoiler array of the top heat sink 2 are consistent.

In some embodiments, the layout of the second spoiler column array is the same as that of the signal TSV array and the liquid TSV array. That is to say, in the embodiment of the present invention, the in-plane distribution of the second spoiler column array is consistent with the signal TSV array 31 and the liquid TSV array 32 inside the multilayer integrated circuit chip 3 .

In some embodiments, an insulating layer is filled on the outer surfaces of the signal TSV array and the liquid TSV array. The signal TSV array 31 and the liquid TSV array 32 in the embodiment of the present invention are all filled with an insulating layer, such as SiO2 (silicon dioxide), after etching.

The cooling liquid enters the heat sink 2 through the entrance of the second outer bottom plate 21 of the heat sink 2, enters the substrate 1 embedded with micro-channels through the channel of the liquid TSV array 32, and finally flows out from the outlet of the substrate 1 to take away the chip heat , the exit is not marked in the drawings.

The embodiment of the present invention consists of a liquid through-silicon via, a micro-channel heat sink embedded with a spoiler column, and a substrate to form a heat dissipation structure. At the same time, a three-dimensional active heat dissipation structure and its manufacturing process based on the heat dissipation method are provided. Through multi-dimensional, Multi-scale balanced active heat dissipation to improve the heat dissipation efficiency of 3D integrated circuit chips can improve the heat dissipation performance and system reliability of 3D integrated circuit chips, and because the heat sink and substrate are both silicon, the internal microfluidic structure remains consistent, Therefore, the process complexity of the overall structure is reduced, and the chip yield rate can be improved.

The embodiments of the present invention can be used for heat dissipation of laser chips, internal circuits of automobiles, liquid cooling of servers, and the like.

Based on the above purpose, the third aspect of the embodiments of the present invention proposes a liquid-cooled motherboard, including the heat dissipation structure of the liquid through-silicon vias compatible with embedded micro-channels as described in any one of the above items. Those skilled in the art know that the liquid-cooled server includes all the technical features and technical effects described above for the heat dissipation structure of liquid through-silicon vias compatible with embedded micro-channels. For the sake of brevity, details are not repeated here.

Based on the above purpose, the fourth aspect of the embodiments of the present invention provides a liquid-cooled server, including the liquid through-silicon via compatible embedded micro-channel heat dissipation structure described in any one of the above items. Those skilled in the art know that the liquid-cooled server includes all the technical features and technical effects described above for the heat dissipation structure of liquid through-silicon vias compatible with embedded micro-channels. For the sake of brevity, details are not repeated here.

Based on the above purpose, the fifth aspect of the embodiments of the present invention proposes a method for manufacturing a liquid through silicon via compatible embedded micro-channel heat dissipation structure. Fig. 5 is a schematic diagram of an embodiment of a manufacturing method of a liquid through-silicon via compatible embedded micro-channel heat dissipation structure provided by the present invention. As shown in Fig. 5, the manufacturing method in the embodiment of the present invention includes the following steps: S1. The surface of the second inner bottom plate of the sink is etched with a second spoiler column array to form a micro flow channel, and the liquid through-silicon hole array interface is etched on the second outer bottom plate of the heat sink to seal the micro flow channel, and the micro flow channel is sealed in the heat sink A liquid inlet is provided on the top; S2, vertically stack the multilayer integrated chips, and etch the signal through-silicon via array and the liquid through-silicon via array on the multi-layer integrated chip; S3, etch the first The spoiler column array constitutes a second micro-channel, sealing the second micro-channel, and setting a liquid outlet on the substrate; and S4, interconnecting the signal TSV array with the substrate, and The liquid TSV arrays are respectively interconnected with the substrate and the heat sink.

In some embodiments, the sealing the micro-channel includes: bonding the second outer bottom plate to the micro-channel structure through a wafer-level bonding process.

In some embodiments, the etching the signal TSV array and the liquid TSV array on the multi-layer integrated chip includes: nesting and distributing the signal TSV array and the liquid TSV array.

In some embodiments, the etching the signal TSV array and the liquid TSV array on the multilayer integrated chip includes: using the TSV deep process to etch the signal TSV array and the liquid silicon via array inside the multilayer integrated chip. via array.

In some embodiments, the interconnecting the liquid TSV arrays with the substrate and the heat sink respectively includes: respectively interconnecting the liquid TSV arrays with the heat sink through a liquid micro-bump process. interconnected with the substrate.

In some embodiments, the manufacturing method further includes: connecting the heat sink and the multilayer integrated chip by soldering.

In the embodiment of the present invention, the production method can be as follows:

Secondary deep reactive ion etching technology is used to etch the second spoiler column array on the upper surface of the second inner bottom plate 22 of the heat sink 2 to form an internal micro flow channel; the second inner bottom plate 22 is etched with a liquid through-silicon hole array Interface; make a metal welding layer at the position where the second inner bottom plate and the second outer bottom plate are in contact with each other, and use a thermocompression bonding process to bond the second outer bottom plate 21 of the heat sink 2 to the micro-channel structure to seal the micro-channel ; A liquid inlet is left at one end of the diagonal line of the second outer bottom plate 21 to obtain a microchannel heat sink containing a second spoiler array.

The heat sink 2 and the multi-layer integrated circuit chip 3 are connected through solder joints 6 , and the interface of the liquid through-silicon via array 32 is communicated by the liquid micro-bump 5 . Multi-layer integrated circuit chips 3 are vertically stacked to form 3D integration.

The signal TSV array 31 and the liquid TSV array 32 are etched inside the multi-layer chip by using a conventional TSV deep process. The signal TSV array 31 is etched on the multilayer integrated circuit chip 3 to realize signal interconnection and cooling channel interconnection; the center of the signal TSV array 31 is a liquid TSV array 32, and the in-plane distribution presents signal TSVs The feature of the nested distribution of the array 31 and the liquid TSV array 32 .

Using secondary deep reactive ion etching technology, etch the first spoiler column array on the lower surface of the first outer bottom plate 11 of the substrate 1 to form an internal micro flow channel; etch the interface of the liquid through-silicon hole 32 on the first outer bottom plate 11; A liquid outlet is left at the other end of the diagonal line of the first outer bottom plate 11; a metal welding layer is made at the position where the first outer bottom plate and the first inner bottom plate are in contact with each other, and the first inner bottom plate 12 is bonded to the second inner bottom plate by using a thermocompression bonding process. An outer bottom plate 11 is bonded to seal the micro-channel.

The liquid through-silicon via array 32 is interconnected with the heat sink 2 through a liquid micro-bump process, and a second filling layer is made between the multilayer integrated circuit chip 3 and the heat sink 2; the signal through-silicon via of the above-mentioned 3D integrated circuit chip The array 31 is interconnected with the substrate 1 through metal bumps 4; the liquid through-silicon via array 32 is interconnected with the substrate 1 and the heat sink 2 respectively through the liquid micro-bump process, and is fabricated between the multilayer integrated circuit chip 3 and the substrate 1 The first filling layer is used to prepare the heat dissipation structure of the liquid through-silicon via compatible with the embedded micro-channel substrate. The bump interconnection process includes thermocompression welding, reflow soldering and other processes.

The cooling liquid enters the heat sink 2 through the entrance of the second outer bottom plate 21 of the heat sink 2, enters the substrate 1 embedded with micro-channels through the channel of the liquid TSV array 32, and finally flows out from the outlet of the substrate 1 to take away the chip heat , the exit is not marked in the drawings.

The embodiment of the present invention consists of liquid through-silicon vias, a microchannel heat sink embedded with spoiler columns, and a substrate to form a heat dissipation structure, and at the same time provides a three-dimensional active heat dissipation structure based on the heat dissipation method and its manufacturing process. On the basis of sinking, micro-channels are built to form a liquid-cooled heat dissipation circulation path, and the heat dissipation efficiency is improved through active heat dissipation. Compatible with liquid TSV arrays, it can balance heat distribution in the vertical direction and reduce heat concentration caused by signal electrothermal coupling. Both the signal TSV array and the liquid TSV array are distributed vertically, so there is no difficulty in in-plane crossover design. And because the heat sink and the substrate are both silicon, the internal micro-channel structure remains consistent, thereby reducing the overall process complexity of the structure and improving the chip yield.

It should be pointed out that the various steps in the various embodiments of the above-mentioned method for manufacturing the heat dissipation structure of liquid through silicon vias compatible with embedded microchannels can be mutually intersected, replaced, added, and deleted. Therefore, these reasonable permutations and combinations of transformations The manufacturing method of the liquid TSV-compatible heat dissipation structure with embedded micro-channels should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.

Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be realized through computer programs to instruct relevant hardware to complete, and the liquid through-silicon vias are compatible with the fabrication of embedded micro-channel heat dissipation structures The program of the method can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM). The foregoing computer program embodiments can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

The above are the exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosed embodiments of the present invention defined in the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in an individual form, they may also be understood as a plurality unless explicitly limited to a singular number.

It should be understood that as used herein, the singular form "a" and "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The serial numbers of the embodiments disclosed in the above-mentioned embodiments of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above-mentioned embodiments can be completed by hardware, or can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. The above-mentioned The storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like.

Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is exemplary only, and is not intended to imply that the disclosed scope (including claims) of the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention , the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in details for the sake of brevity. Therefore, within the spirit and principle of the embodiments of the present invention, any omissions, modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the embodiments of the present invention.

Claims (22)

1. The heat dissipation structure compatible with the embedded micro-channel by the liquid through silicon vias is characterized by comprising the following components:

the substrate comprises a first outer bottom plate and a first inner bottom plate, and a first turbulent flow column array is etched in the substrate;

the heat sink comprises a second outer bottom plate and a second inner bottom plate, and a second turbulent flow column array is etched in the heat sink; and

the multi-layer integrated circuit chip is vertically stacked and arranged between the substrate and the heat sink, a signal through silicon hole array and a liquid through silicon hole array are etched in the multi-layer integrated circuit chip, the signal through silicon hole array is connected with the substrate through bumps, and the liquid through silicon hole array is respectively connected with the heat sink and the substrate through liquid micro bumps.

2. The heat dissipation structure of the embedded micro-fluidic channel compatible with the through-silicon-via of claim 1, wherein the second turbulence post array is etched on the second inner bottom plate, the second turbulence post array comprises a first turbulence post and a second turbulence post, and the second turbulence post is higher than the first turbulence post.

3. The heat dissipation structure of the embedded micro flow channel compatible with the through silicon via of claim 2, wherein the first turbulence column and the second turbulence column have the same shape.

4. The heat dissipation structure of the embedded micro flow channel compatible with the through silicon via of claim 3, wherein the shape of the first turbulence column is a cylindrical column or a regular hexagonal column.

5. The thermal dissipation structure of a liquid through silicon via compatible embedded micro-fluidic channel of claim 1, wherein the heat sink is configured to hold a cooling liquid, the cooling liquid being a liquid having a high thermal conductivity.

6. The thermal dissipation structure of a liquid through silicon via compatible embedded micro-fluidic channel of claim 1, wherein the heat sink is connected to the multi-layer integrated circuit die by solder joints.

7. The heat dissipation structure of the embedded micro-fluidic channel compatible with the liquid through silicon vias according to claim 1, wherein the second outer bottom plate and the second inner bottom plate are made of the same material, and the second outer bottom plate is made of silicon, diamond, heat-conducting ceramic or organic resin.

8. The heat dissipation structure of a liquid through silicon via compatible embedded micro-fluidic channel of claim 1, wherein the second outer bottom plate and the second inner bottom plate are different in material.

9. The heat dissipation structure of a liquid through silicon via compatible embedded micro-fluidic channel of claim 8, wherein the second outer bottom plate is glass.

10. The heat dissipation structure of a liquid through silicon via compatible embedded micro flow channel according to claim 1, wherein a layout mode of the first turbulence column array is the same as a layout mode of the second turbulence column array.

11. The heat dissipation structure of a liquid through silicon via compatible embedded micro flow channel according to claim 1, wherein a layout manner of the second turbulence column array is the same as a layout manner of the signal through silicon via array and the liquid through silicon via array.

12. The heat dissipation structure of a liquid through silicon via compatible embedded micro flow channel of claim 1, wherein an insulating layer is filled on the outer surfaces of the signal through silicon via array and the liquid through silicon via array.

13. The heat dissipation structure of a liquid through silicon via compatible embedded micro flow channel according to claim 1, wherein a liquid inlet is provided at one end of a diagonal of the second outer bottom plate, and a liquid outlet is provided at one end of a diagonal of the first outer bottom plate.

14. A motherboard comprising a heat dissipation structure of any one of claims 1-13, wherein the liquid through silicon vias are compatible with embedded micro-fluidic channels.

15. A liquid-cooled motherboard comprising the heat dissipation structure of any one of claims 1-13, wherein the liquid through silicon vias are compatible with embedded micro-fluidic channels.

16. A liquid cooling server comprising the heat dissipation structure of any one of claims 1-13, wherein the liquid through silicon vias are compatible with embedded micro-fluidic channels.

17. The manufacturing method of the heat dissipation structure compatible with the embedded micro-channel by the liquid through silicon vias is characterized by comprising the following steps of:

etching a second turbulent column array on the upper surface of a second inner bottom plate of the heat sink to form a micro-channel, etching a liquid silicon through hole array interface on a second outer bottom plate of the heat sink, sealing the micro-channel, and arranging a liquid inlet on the heat sink;

vertically stacking the multi-layer integrated chips, and etching the signal through silicon via array and the liquid through silicon via array on the multi-layer integrated chips;

etching a first turbulent flow column array on the lower surface of a first outer bottom plate of a substrate to form a second micro-channel, sealing the second micro-channel, and arranging a liquid outlet on the substrate; and

interconnecting the array of signal through-silicon vias with the substrate and interconnecting the array of liquid through-silicon vias with the substrate and the heat sink, respectively.

18. The method for manufacturing the heat dissipation structure of the embedded micro-fluidic channel compatible with the through-silicon-via of claim 17, wherein the sealing the micro-fluidic channel comprises:

and bonding the second outer bottom plate with the micro-channel structure through a wafer-level bonding process.

19. The method for manufacturing the heat dissipation structure of the embedded micro-fluidic channel compatible with the liquid through silicon vias according to claim 17, wherein the etching the signal through silicon via array and the liquid through silicon via array on the multilayer integrated chip comprises:

and embedding and distributing the signal through silicon via array and the liquid through silicon via array.

20. The method for manufacturing the heat dissipation structure of the embedded micro-fluidic channel compatible with the liquid through silicon vias according to claim 17, wherein the etching the signal through silicon via array and the liquid through silicon via array on the multilayer integrated chip comprises:

and etching the signal through-silicon via array and the liquid through-silicon via array inside the multilayer integrated chip by adopting a through-silicon via deep process.

21. The method of fabricating a thermal dissipation structure for a liquid through silicon via compatible embedded micro-fluidic channel of claim 17, wherein interconnecting the liquid through silicon via array with the substrate and the heat sink, respectively, comprises:

and interconnecting the liquid through silicon via array with the heat sink and the substrate respectively through a liquid micro bump process.

22. The method for manufacturing the heat dissipation structure of the embedded micro-fluidic channel compatible with the through-silicon-via of claim 17, further comprising:

and connecting the heat sink and the multilayer integrated chip through welding.