CN116364150B - Memory self-adaptive write auxiliary circuit control method and device and memory - Google Patents
Memory self-adaptive write auxiliary circuit control method and device and memory Download PDFInfo
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- CN116364150B CN116364150B CN202310393205.XA CN202310393205A CN116364150B CN 116364150 B CN116364150 B CN 116364150B CN 202310393205 A CN202310393205 A CN 202310393205A CN 116364150 B CN116364150 B CN 116364150B
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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Abstract
The invention relates to the technical field of memories, and provides a method and a device for controlling a self-adaptive write auxiliary circuit of a memory and the memory, wherein the method comprises the following steps: when the power-on stage of the memory is completed, after the memory is started, before normal operation, acquiring the power supply voltage of the memory; judging the voltage state of the memory according to the power supply voltage of the memory; and controlling the corresponding functional state of the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to perform writing operation normally and lock the functional state of the writing auxiliary circuit. According to the invention, when the power-on stage is completed, after the memory is started and before normal operation, the corresponding functional state of the writing auxiliary circuit is controlled according to the power supply voltage, so that the memory can normally perform writing operation, and the defect of writing failure of the memory caused by low power supply voltage is overcome.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a method and an apparatus for controlling a self-adaptive write auxiliary circuit of a memory, and a memory.
Background
SRAM (Static Random-Access Memory) is a volatile Random Access Memory that stores data through a Memory array and writes external data to the Memory array through a write circuit. In order to reduce power consumption, current memory chips generally operate at a lower power supply voltage, and when the power supply voltage drops, bit cells (memory cells) of the SRAM may fail to be written due to insufficient write margin.
Disclosure of Invention
The invention mainly aims to provide a method and a device for controlling a self-adaptive write auxiliary circuit of a memory and the memory, and aims to overcome the defect of write failure of the memory caused by low power supply voltage.
In order to achieve the above object, the present invention provides a method for controlling a self-adaptive write assist circuit of a memory, which is applied to a volatile random access memory, and includes the following steps:
when the power-on stage of the memory is completed, after the memory is started, before normal operation, acquiring the power supply voltage of the memory;
judging the voltage state of the memory according to the power supply voltage of the memory;
and controlling the corresponding functional state of the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to perform writing operation normally and lock the functional state of the writing auxiliary circuit.
Further, the step of determining the voltage state of the memory according to the power supply voltage of the memory includes:
comparing the power supply voltage with a first voltage threshold and a second voltage threshold; wherein the first voltage threshold is greater than the second voltage threshold;
if the power supply voltage is not lower than the first voltage threshold, judging that the memory is in a normal working voltage state;
if the power supply voltage is lower than the first voltage threshold and not lower than the second voltage threshold, determining that the memory is in a first abnormal voltage state;
and if the power supply voltage is lower than the second voltage threshold, judging that the memory is in a second abnormal voltage state.
Further, the step of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory includes:
and if the memory is in a normal working voltage state, controlling the function corresponding to the writing auxiliary circuit to be closed.
Further, the step of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory includes:
if the memory is in the first abnormal working voltage state, the write-in auxiliary circuit is controlled to start the function of reducing the bit line voltage.
Further, the step of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory includes:
if the memory is in the second abnormal working voltage state, the write auxiliary circuit is controlled to simultaneously start the function of reducing the bit line voltage and the function of increasing the word line voltage.
Further, according to the voltage state of the memory, controlling the functional state corresponding to the write auxiliary circuit, so that the memory performs the write operation normally, the method includes:
acquiring test data and generating a data identifier;
acquiring the data length of the test data, adding a data head into the test data, and adding the data length and a data identifier into the data head;
writing test data with an added data header into a memory;
acquiring a data head of target data written into a memory, and detecting whether the data identification exists in the data head;
if so, acquiring the data length recorded in the data header and acquiring the data length of the target data;
judging whether the data length recorded in the data header is consistent with the data length of the target data; and if the data are consistent, judging that the writing data of the memory are normal.
Further, the step of adding the data length and the data identifier in the data header includes:
dividing the data head into two partitions which are connected in sequence, wherein the two partitions are connected by adopting a preset separator;
respectively generating corresponding identifiers for the data identifier and the data length, and respectively generating a data identifier and a length identifier;
adding the data identifier at the head of the former partition and the length identifier at the head of the latter partition;
adding the data length after a length identifier of the data header; the data identification is added after the data identifier of the data header.
The invention also provides a memory self-adaptive write auxiliary circuit control device, which is applied to the volatile random access memory and comprises:
the acquisition unit is used for acquiring the power supply voltage of the memory after the memory is started and before normal operation when the power-on stage of the memory is completed;
a judging unit, configured to judge a voltage state of the memory according to a power supply voltage of the memory;
and the control unit is used for controlling the functional state corresponding to the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to normally perform writing operation and lock the functional state of the writing auxiliary circuit.
Further, the judging unit is specifically configured to:
comparing the power supply voltage with a first voltage threshold and a second voltage threshold; wherein the first voltage threshold is greater than the second voltage threshold;
if the power supply voltage is not lower than the first voltage threshold, judging that the memory is in a normal working voltage state;
if the power supply voltage is lower than the first voltage threshold and not lower than the second voltage threshold, determining that the memory is in a first abnormal voltage state;
and if the power supply voltage is lower than the second voltage threshold, judging that the memory is in a second abnormal voltage state.
The invention also provides a memory on which the adaptive write assist circuit control circuit implements the steps of the method of any of the above.
The invention provides a method and a device for controlling a self-adaptive write auxiliary circuit of a memory, and the memory, comprising the following steps: when the power-on stage of the memory is completed, after the memory is started, before normal operation, acquiring the power supply voltage of the memory; judging the voltage state of the memory according to the power supply voltage of the memory; and controlling the corresponding functional state of the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to perform writing operation normally and lock the functional state of the writing auxiliary circuit. According to the invention, when the power-on stage is completed, after the memory is started and before normal operation, the corresponding functional state of the writing auxiliary circuit is controlled according to the power supply voltage, so that the memory can normally perform writing operation, and the defect of writing failure of the memory caused by low power supply voltage is overcome.
Drawings
FIG. 1 is a schematic diagram showing steps of a control method of a memory adaptive write assist circuit according to an embodiment of the invention;
FIG. 2 is a block diagram of a control device for a memory adaptive write assist circuit according to an embodiment of the invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, in one embodiment of the present invention, a method for controlling a memory adaptive write assist circuit is provided, which is applied to a volatile random access memory, and includes the following steps:
step S1, when the power-on stage of the memory is completed, after the memory is started, before normal operation, acquiring the power supply voltage of the memory;
step S2, judging the voltage state of the memory according to the power supply voltage of the memory;
and step S3, controlling the corresponding functional state of a Write auxiliary circuit (Write auxiliary) according to the voltage state of the memory so that the memory can normally perform Write operation, and locking the functional state of the Write auxiliary circuit.
In this embodiment, the memory is a volatile random access memory, which is usually operated at a low power supply voltage in order to reduce power consumption, but when the power supply voltage is too low, it is easy to cause failure in writing data. Therefore, as described in step S1 above, when the power-up phase of the memory is completed, after the memory is started, before normal operation, the power supply voltage of the memory needs to be obtained, that is, the power supply voltage of the memory during operation, if the power supply voltage is too low, the corresponding processing should be performed subsequently, so as to avoid failure of the storage and writing operation; as described in the above step S2, the voltage state of the memory is determined according to the power supply voltage of the memory; that is, it is determined whether the current power supply voltage is stored in a state where the voltage is too low. As described in step S3, the functional state corresponding to the write assist circuit is controlled according to the voltage state of the memory, so that the memory performs the write operation normally. The write assist circuit has the functions of lowering the bit line voltage (BL) and raising the word line voltage (WL), and when the write data fails due to the excessively low power supply voltage of the memory, the functions of lowering the bit line voltage and raising the word line voltage can enhance the write capability of the memory, thereby improving the write success rate of the memory. Therefore, when the power supply voltage of the memory is in different voltage states, the write auxiliary circuit can be controlled to start corresponding functions.
It can be understood that, after the corresponding functional state of the write assist circuit is controlled, in order to enable the memory to perform persistent normal write operation, the functional state of the write assist circuit may be locked, so that the memory may still perform normal write operation after the power-up is completed to perform the working state.
In one embodiment, a plurality of voltage thresholds may be set for respectively determining the current voltage state of the power supply voltage of the memory; it will be appreciated that when the power supply voltage of the memory is only slightly lower, only one of the functions of the write assist circuit that enhances the memory writing capability, i.e., the function of lowering the bit line voltage, or the function of raising the word line voltage, may be turned on. When the power supply voltage is too low, the function of lowering the bit line voltage and the function of raising the word line voltage are required to be simultaneously started to enhance the writing capability of the memory. In this embodiment, by setting the first voltage threshold and the second voltage threshold, the current voltage state of the power supply voltage of the memory is determined, that is, whether the voltage is too low is qualitatively determined. Wherein the first voltage threshold is greater than the second voltage threshold.
Specifically, in this embodiment, the step S2 of determining the voltage state of the memory according to the power supply voltage of the memory includes:
step S21, comparing the power supply voltage with a first voltage threshold and a second voltage threshold; wherein the first voltage threshold is greater than the second voltage threshold;
step S22a, if the power supply voltage is not lower than the first voltage threshold, judging that the memory is in a normal working voltage state;
step S22b, if the power supply voltage is lower than the first voltage threshold and not lower than the second voltage threshold, determining that the memory is in a first abnormal voltage state;
step S22c, if the power supply voltage is lower than the second voltage threshold, determining that the memory is in a second abnormal voltage state.
In this embodiment, the step S3 of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory includes:
and if the memory is in a normal working voltage state, controlling the function corresponding to the writing auxiliary circuit to be closed. When the power supply voltage of the memory is in a normal working voltage state, the memory can normally perform writing operation at the moment, and the corresponding function of the writing auxiliary circuit is controlled to be closed; after the power-on is completed, the memory can perform normal write operation without starting the corresponding function of the write auxiliary circuit.
In another embodiment, the step S3 of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory includes:
if the memory is in the first abnormal working voltage state, the write-in auxiliary circuit is controlled to start the function of reducing the bit line voltage. When the power supply voltage of the memory is in a first abnormal working voltage state, the voltage is low, and the memory cannot normally perform writing operation at the moment, the writing auxiliary circuit is controlled to start a function of reducing the voltage of the bit line; after power up is completed, the memory may perform a write operation normally.
In yet another embodiment, the step S3 of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory includes:
if the memory is in the second abnormal working voltage state, the write auxiliary circuit is controlled to simultaneously start the function of reducing the bit line voltage and the function of increasing the word line voltage.
When the power supply voltage of the memory is in the second abnormal working voltage state, the voltage is very low, and the memory cannot normally perform writing operation at the moment, and if only one function of the writing auxiliary circuit for enhancing the writing capability of the memory is adopted, the condition of reading errors still exists; therefore, the write auxiliary circuit is controlled to simultaneously start the function of reducing the bit line voltage and the function of increasing the word line voltage, and two ways of enhancing the writing capability of the memory are adopted; so that after the power-up of the memory is completed, the memory can normally perform the write operation.
In an embodiment, after step S3 of controlling the functional state corresponding to the write assist circuit according to the voltage state of the memory, so that the memory performs the write operation normally, the method includes:
s4, acquiring test data and generating a data identifier;
step S5, obtaining the data length of the test data, adding a data head in the test data, and adding the data length and a data identifier in the data head;
step S6, writing the test data added with the data header into a memory;
step S7, acquiring a data header of target data written into a memory, and detecting whether the data identifier exists in the data header;
step S8, if the target data exists, acquiring the data length recorded in the data header and acquiring the data length of the target data;
step S9, judging whether the data length recorded in the data head is consistent with the data length of the target data; and if the data are consistent, judging that the writing data of the memory are normal.
In this embodiment, after the write assist circuit turns on the corresponding enhancement function, in order to test whether the write operation of the memory is normal, test data may be used for testing, where the test data may be one or more; the acquired test data are all required to be identified, so that corresponding data identification is required to be generated aiming at the test data; then, acquiring the data length of the test data, adding a data head into the test data, and adding the data length and a data identifier into the data head; test data with the data header added is written into the memory. It will be appreciated that if the memory write operation is normal, then test data may be written normally, and the data it writes should be entirely valid. Thus, a data header of target data written in a memory can be acquired, and whether the data identifier exists in the data header is detected; if so, acquiring the data length recorded in the data header and acquiring the data length of the target data; judging whether the data length recorded in the data header is consistent with the data length of the target data; and if the data are consistent, judging that the writing data of the memory are normal.
In this embodiment, a specific scheme of adding a data length and a data identifier to a data header is also proposed. Specifically, the step S5 of adding the data length and the data identifier in the data header includes:
dividing the data head into two partitions which are connected in sequence, wherein the two partitions are connected by adopting a preset separator; the predetermined separator includes a specific symbol: any one or a combination of a plurality of%, #, & gt, & lt/EN & gt and numbers.
Respectively generating corresponding identifiers for the data identifier and the data length, and respectively generating a data identifier and a length identifier; in order to distinguish the data identifier and the data length in the data header, the corresponding identifiers need to be generated to identify respectively, and then only the identifiers are needed to pass through, so that whether the corresponding data is the data identifier or the data length can be identified.
Adding the data identifier at the head of the former partition and the length identifier at the head of the latter partition;
adding the data length after a length identifier of the data header; the data identification is added after the data identifier of the data header.
Referring to fig. 2, in an embodiment of the present invention, there is further provided a memory adaptive write assist circuit control apparatus applied to a volatile random access memory, including:
the acquisition unit is used for acquiring the power supply voltage of the memory after the memory is started and before normal operation when the power-on stage of the memory is completed;
a judging unit, configured to judge a voltage state of the memory according to a power supply voltage of the memory;
and the control unit is used for controlling the functional state corresponding to the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to normally perform writing operation and lock the functional state of the writing auxiliary circuit.
In an embodiment, the determining unit is specifically configured to:
comparing the power supply voltage with a first voltage threshold and a second voltage threshold; wherein the first voltage threshold is greater than the second voltage threshold;
if the power supply voltage is not lower than the first voltage threshold, judging that the memory is in a normal working voltage state;
if the power supply voltage is lower than the first voltage threshold and not lower than the second voltage threshold, determining that the memory is in a first abnormal voltage state;
and if the power supply voltage is lower than the second voltage threshold, judging that the memory is in a second abnormal voltage state.
In this embodiment, for specific implementation of each unit in the above embodiment of the apparatus, please refer to the description in the above embodiment of the method, and no further description is given here.
The embodiment of the invention also provides a memory, which is provided with the self-adaptive writing auxiliary circuit control circuit, and the self-adaptive writing auxiliary circuit control method of the memory is realized when the memory is started.
In summary, the method, the device and the memory for controlling the adaptive write assist circuit of the memory provided in the embodiments of the present invention include: when the power-on stage of the memory is completed, after the memory is started, before normal operation, acquiring the power supply voltage of the memory; judging the voltage state of the memory according to the power supply voltage of the memory; and controlling the corresponding functional state of the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to perform writing operation normally and lock the functional state of the writing auxiliary circuit. According to the invention, when the power-on stage is completed, after the memory is started and before normal operation, the corresponding functional state of the writing auxiliary circuit is controlled according to the power supply voltage, so that the memory can normally perform writing operation, and the defect of writing failure of the memory caused by low power supply voltage is overcome.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by an internal memory-related control circuit that is capable of executing, at the time of memory start-up, the processes of embodiments including the methods described above. Any reference to memory, storage, database, or other medium provided by the present invention and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus, article or method that comprises the element.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (8)
1. The self-adaptive write auxiliary circuit control method for the memory is characterized by being applied to a volatile random access memory and comprising the following steps of:
when the power-on stage of the memory is completed, after the memory is started, before normal operation, acquiring the power supply voltage of the memory;
judging the voltage state of the memory according to the power supply voltage of the memory;
controlling the corresponding functional state of the writing auxiliary circuit according to the voltage state of the memory, so that the memory normally performs writing operation and locks the functional state of the writing auxiliary circuit;
according to the voltage state of the memory, controlling the corresponding functional state of the write auxiliary circuit to enable the memory to normally perform the write operation, the method comprises the following steps:
acquiring test data and generating a data identifier;
acquiring the data length of the test data, adding a data head into the test data, and adding the data length and a data identifier into the data head;
writing test data with an added data header into a memory;
acquiring a data head of target data written into a memory, and detecting whether the data identification exists in the data head;
if so, acquiring the data length recorded in the data header and acquiring the data length of the target data;
judging whether the data length recorded in the data header is consistent with the data length of the target data; if the data written into the memory is consistent, judging that the data written into the memory is normal;
the step of adding the data length and the data identifier in the data header includes:
dividing the data head into two partitions which are connected in sequence, wherein the two partitions are connected by adopting a preset separator;
respectively generating corresponding identifiers for the data identifier and the data length, and respectively generating a data identifier and a length identifier;
adding the data identifier at the head of the former partition and the length identifier at the head of the latter partition;
adding the data length after a length identifier of the data header; the data identification is added after the data identifier of the data header.
2. The method of claim 1, wherein the step of determining the voltage state of the memory based on the power supply voltage of the memory comprises:
comparing the power supply voltage with a first voltage threshold and a second voltage threshold; wherein the first voltage threshold is greater than the second voltage threshold;
if the power supply voltage is not lower than the first voltage threshold, judging that the memory is in a normal working voltage state;
if the power supply voltage is lower than the first voltage threshold and not lower than the second voltage threshold, determining that the memory is in a first abnormal voltage state;
and if the power supply voltage is lower than the second voltage threshold, judging that the memory is in a second abnormal voltage state.
3. The method for controlling a memory adaptive write assist circuit according to claim 2, wherein the step of controlling a functional state corresponding to a write assist circuit according to a voltage state of the memory comprises:
and if the memory is in a normal working voltage state, controlling the function corresponding to the writing auxiliary circuit to be closed.
4. The method for controlling a memory adaptive write assist circuit according to claim 2, wherein the step of controlling a functional state corresponding to a write assist circuit according to a voltage state of the memory comprises:
if the memory is in the first abnormal working voltage state, the write-in auxiliary circuit is controlled to start the function of reducing the bit line voltage.
5. The method for controlling a memory adaptive write assist circuit according to claim 2, wherein the step of controlling a functional state corresponding to a write assist circuit according to a voltage state of the memory comprises:
if the memory is in the second abnormal working voltage state, the write auxiliary circuit is controlled to simultaneously start the function of reducing the bit line voltage and the function of increasing the word line voltage.
6. A memory adaptive write assist circuit control apparatus, for use with a volatile random access memory, comprising:
the acquisition unit is used for acquiring the power supply voltage of the memory after the memory is started and before normal operation when the power-on stage of the memory is completed;
a judging unit, configured to judge a voltage state of the memory according to a power supply voltage of the memory;
the control unit is used for controlling the functional state corresponding to the writing auxiliary circuit according to the voltage state of the memory so as to enable the memory to normally perform writing operation and lock the functional state of the writing auxiliary circuit;
according to the voltage state of the memory, controlling the corresponding functional state of the write auxiliary circuit to enable the memory to perform write operation normally, the method comprises the following steps:
acquiring test data and generating a data identifier;
acquiring the data length of the test data, adding a data head into the test data, and adding the data length and a data identifier into the data head;
writing test data with an added data header into a memory;
acquiring a data head of target data written into a memory, and detecting whether the data identification exists in the data head;
if so, acquiring the data length recorded in the data header and acquiring the data length of the target data;
judging whether the data length recorded in the data header is consistent with the data length of the target data; if the data written into the memory is consistent, judging that the data written into the memory is normal;
the step of adding the data length and the data identifier in the data header includes:
dividing the data head into two partitions which are connected in sequence, wherein the two partitions are connected by adopting a preset separator;
respectively generating corresponding identifiers for the data identifier and the data length, and respectively generating a data identifier and a length identifier;
adding the data identifier at the head of the former partition and the length identifier at the head of the latter partition;
adding the data length after a length identifier of the data header; the data identification is added after the data identifier of the data header.
7. The memory adaptive write assist circuit control apparatus as set forth in claim 6, wherein said judgment unit is specifically configured to:
comparing the power supply voltage with a first voltage threshold and a second voltage threshold; wherein the first voltage threshold is greater than the second voltage threshold;
if the power supply voltage is not lower than the first voltage threshold, judging that the memory is in a normal working voltage state;
if the power supply voltage is lower than the first voltage threshold and not lower than the second voltage threshold, determining that the memory is in a first abnormal voltage state;
and if the power supply voltage is lower than the second voltage threshold, judging that the memory is in a second abnormal voltage state.
8. A memory having thereon adaptive write assist circuitry control circuitry to implement the steps of the method of any of claims 1 to 5.
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| CN107408409A (en) * | 2015-06-05 | 2017-11-28 | 思科技术公司 | Low-power, towards capable memory write auxiliary circuit |
| CN109801656A (en) * | 2018-12-29 | 2019-05-24 | 成都海光集成电路设计有限公司 | A kind of memory circuit, adaptive negative voltage write auxiliary control method and chip |
| CN113314175A (en) * | 2021-05-25 | 2021-08-27 | 海光信息技术股份有限公司 | Write-assist device, working method thereof and memory |
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| CN116364150A (en) | 2023-06-30 |
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