CN116360858B - Data processing method, graphics processor, electronic device and storage medium - Google Patents

Abstract

The present disclosure relates to the technical field of information processing, and in particular to a data processing method, a graphics processor, an electronic device, and a storage medium. The processing method includes: receiving an instruction to be operated; The interactive address corresponding to the operation data, and based on the interactive address, obtains the data to be operated stored in the register group; wherein, the interactive address includes: storage area row address alignment offset, storage area intermediate address; the storage area The area row address alignment offset is used to indicate the address offset of the data to be operated in the storage area in the preset data processing mode; the intermediate address of the storage area is used to indicate that the data to be operated is in the corresponding An intermediate address in the storage area; an operation result is generated according to the data to be operated and the operation method. The data processing method provided by the embodiment of the present disclosure is beneficial to improving the access flexibility of the register set.

Description

Data processing method, graphics processor, electronic device and storage medium

technical field

The present disclosure relates to the technical field of information processing, and in particular, to a data processing method, a graphics processor, an electronic device, and a storage medium.

Background technique

In related technologies, there is frequent data interaction between the graphics processor and the host, and the host sends the data to be calculated to the graphics processor, and the graphics processor saves the data to the memory and performs parallel operations on it according to the operator of the data to be calculated. In order to realize the high-speed processing of the data to be calculated. However, with the different application scenarios of the program, the graphics processor can no longer process the data to be calculated in different data processing modes at the same time, and the calculation limitation is too large. Therefore, how to better process the data is an urgent need for developers to solve technical problem.

Contents of the invention

The present disclosure proposes a data processing technical solution.

According to an aspect of the present disclosure, a data processing method is provided, which is applied to a graphics processor, and the graphics processor includes a computing core and a register set; the processing method includes: receiving an instruction to be operated; Instructions, determine the operation mode and the interaction address corresponding to the data to be operated, and obtain the data to be operated stored in the register group based on the interaction address; wherein, the interaction address includes: storage area row address alignment offset, storage The middle address of the area; the row address alignment offset of the storage area is used to represent the address offset of the data to be operated in the storage area in the preset data processing mode; the middle address of the storage area is used to represent the The intermediate address of the data to be operated in the corresponding storage area; according to the data to be operated and the operation method, an operation result is generated.

In a possible implementation manner, the register set includes at least one storage area, and the processing method further includes: receiving a plurality of data to be operated; according to a data processing mode corresponding to the plurality of data to be operated, converting the The plurality of data to be operated is divided into a plurality of data groups to be operated; wherein, the amount of data to be operated in the data groups to be operated corresponding to different data processing modes is different; the plurality of data groups to be operated is allocated to the at least one In the storage area, the interactive address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated is obtained; wherein, each data group to be operated in the plurality of data groups to be operated is allocated to at least one storage area.

In a possible implementation manner, the obtaining the interaction address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated includes: according to the address corresponding to each data to be operated The address bits from the lowest preset number of bits in the base address of the logical address are used as the storage area row address alignment offset in the interactive address corresponding to each data to be operated, and the remaining address bits are shifted to the left by the preset bits After counting, the sum value obtained by adding the logical offset address is used as the intermediate address of the storage area in the interactive address corresponding to each data to be operated; wherein, the logical offset address is the logical address corresponding to each data to be operated address offset.

In a possible implementation manner, the dividing the plurality of data to be operated into a plurality of data groups to be operated according to the data processing mode corresponding to the plurality of data to be operated includes: according to the plurality of data to be operated The data processing mode corresponding to the operation data divides the plurality of data to be operated into a plurality of data groups to be operated corresponding to task identifiers; wherein, the task identifier is used to map each of the plurality of data groups to be operated The array to be operated is allocated to the base address position in the at least one storage area.

In a possible implementation manner, the interaction address includes: storage area row address alignment offset, storage area intermediate address, and hash value, and each data to be operated in the plurality of data groups to be operated is obtained The interaction address corresponding to each data to be calculated in the group includes: generating a hash value corresponding to each data group to be calculated according to the task identifier corresponding to each data group to be calculated in the plurality of data groups to be calculated; Wherein, the task identifiers have different hash values between adjacent data groups to be operated; according to the hash value corresponding to each data group to be operated, generate the corresponding The interactive address; where, the data to be calculated in the data group to be calculated corresponding to different hash values are stored in different physical storage areas.

In a possible implementation manner, the interaction address includes: storage area row address alignment offset, storage area intermediate address, and hash value, and each data to be operated in the plurality of data groups to be operated is obtained The interaction address corresponding to each data to be calculated in the group includes: generating the each A hash value corresponding to each data group to be operated; wherein, the sampling identifier is used to represent a different sampling point for processing of each data group to be operated in the plurality of data groups to be operated; according to each data group to be operated The hash value corresponding to the group generates the interactive address corresponding to each data to be calculated in each data group to be calculated; wherein, the data to be calculated in the data group to be calculated corresponding to different hash values are stored in different physical storage area.

In a possible implementation manner, the register group includes a storage area, and the obtaining the data to be operated in the register group based on the interaction address includes: according to the interaction address corresponding to each data to be operated, Determine the row address and column address of each data to be operated in its corresponding storage area; wherein, the row address and column address are used to indicate the position of the register in the storage area; according to each data to be operated The row address and column address of the data in its corresponding storage area are accessed to its corresponding register to obtain each of the data to be operated.

In a possible implementation manner, the register set includes a plurality of storage areas, and the obtaining the data to be operated in the register set based on the interaction address includes: For each data to be operated, according to the plurality of data to be operated, an interactive address and a storage area identifier corresponding to each data to be operated are determined; wherein, the storage area identification is used to store the plurality of data to be operated When a group is allocated to multiple storage areas, determine the storage area corresponding to each data group to be calculated among the multiple data groups to be calculated; determine each data to be calculated according to the storage area identifier corresponding to each data to be calculated Corresponding storage area; according to the interactive address corresponding to each data to be operated, determine the row address and column address of each data to be operated in its corresponding storage area; wherein, the row address and column address are used To indicate the position of the register in the storage area; according to the row address and column address of each data to be operated in its corresponding storage area, access the register in its corresponding storage area to obtain the data.

In a possible implementation manner, the obtaining the interaction address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated includes: generating an address in the plurality of data groups to be operated The interactive address corresponding to each data to be calculated in each data group to be calculated; generate the number of segments corresponding to each data to be calculated according to the thread number corresponding to the data to be calculated and the total number of threads corresponding to the preset data processing mode ; Wherein, the number of segments represents the segment offset generated by storing each of the data to be operated in the preset data processing mode; according to the interactive address corresponding to each of the data to be operated, determine the The row address and column address of each data to be operated in its corresponding storage area, including: generating the data to be operated in its corresponding storage area according to the interactive address and the number of segments corresponding to each data to be operated The row address in; according to the interaction address, segment number, and hash value corresponding to each data to be operated, generate the column address of each data to be operated in its corresponding storage area, or according to each data to be operated The interactive address and segment number corresponding to the data are calculated, and the column address of each data to be calculated in its corresponding storage area is generated.

In a possible implementation manner, the allocating the plurality of data groups to be operated into the at least one storage area includes: for each data group to be operated in the plurality of data groups to be operated, Each of the data groups to be operated is equally distributed to each storage area.

In a possible implementation manner, the acquiring the data to be operated stored in the register set based on the interaction address includes: acquiring the register based on the interaction address through multiple pipelines of the graphics processor The data to be calculated stored in the group; said generating a calculation result according to the data to be calculated and the calculation method includes: passing through multiple pipelines of the graphics processor, according to the data to be calculated and the calculation method , to generate the operation result corresponding to each data to be operated.

In a possible implementation manner, generating an operation result corresponding to each data to be operated according to the data to be operated and the operation mode through multiple pipelines of the graphics processor includes: In the case that there are different pipelines in the multiple pipelines of the graphics processor accessing the target port of the register group at the same time, arbitration is performed according to the priorities of the different pipelines and/or the priority of the read and write operations to determine the target port The corresponding target pipeline: through the target pipeline and other pipelines in the different pipelines in sequence, according to the data to be calculated and the calculation method, an operation result corresponding to each data to be calculated is generated.

According to an aspect of the present disclosure, a graphics processor is provided, the graphics processor includes: a computing core, a register group connected to the computing core; the computing core is used to receive instructions to be calculated; according to the The instruction to be operated determines the operation mode and the interactive address corresponding to the data to be operated, and obtains the data to be operated stored in the register set based on the interactive address; wherein the interactive address includes: storage area row address alignment offset . The middle address of the storage area; the row address alignment offset of the storage area is used to represent the address offset of the data to be calculated in the storage area in the preset data processing mode; the middle address of the storage area is used to Indicates the intermediate address of the data to be operated in the corresponding storage area; generates an operation result according to the data to be operated and the operation mode.

According to an aspect of the present disclosure, an electronic device is provided, including: a host, and the above-mentioned graphics processor.

According to one aspect of the present disclosure, a computer-readable and writable data storage medium is provided, on which computer program instructions and data to be calculated are stored, and when the computer program instructions are executed by a processor, the above data processing method is implemented.

In the embodiment of the present disclosure, the instruction to be operated can be received, and then according to the instruction to be operated, the operation mode and the interaction address corresponding to the data to be operated can be determined, and the data to be operated stored in the register group can be obtained based on the interaction address , and finally generate a calculation result according to the data to be calculated and the calculation method. The embodiment of the present disclosure can perform process interaction through the interaction address recorded with the alignment offset of the row address of the storage area, and convert the logical address of the data to be operated in the register set in different data processing modes to the interaction in the preset data processing mode The way of the address makes the register group compatible with saving the data to be calculated in different data processing modes, and also compatible with the operation and processing of the data to be calculated in different data processing modes, which is beneficial to improve the access flexibility of the register group.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings here are incorporated into the description and constitute a part of the present description. These drawings show embodiments consistent with the present disclosure, and are used together with the description to explain the technical solution of the present disclosure.

Fig. 1 shows a flowchart of a data processing method provided according to an embodiment of the present disclosure.

Fig. 2 shows a flowchart of a data processing method provided according to an embodiment of the present disclosure.

Fig. 3 shows a reference schematic diagram of a data processing method provided according to an embodiment of the present disclosure.

FIG. 4 shows a reference schematic diagram of a data processing method provided according to an embodiment of the present disclosure.

Fig. 5 shows a block diagram of a graphics processor provided according to an embodiment of the present disclosure.

Fig. 6 shows a block diagram of an electronic device provided according to an embodiment of the present disclosure.

Detailed ways

Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements. While various aspects of the embodiments are shown in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations. In addition, the term "at least one" herein means any one of a variety or any combination of at least two of the more, for example, including at least one of A, B, and C, which may mean including from A, Any one or more elements selected from the set formed by B and C.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present disclosure may be practiced without some of the specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art have not been described in detail so as to obscure the gist of the present disclosure.

In the related art, the register bank can usually only process the data to be operated in the same data processing mode. In the related art, WAVE32 (data processing is completed by 32 threads in a data processing flow, where WAVE is also called a thread warp, example Specifically, WAVE is a thread warp under the SIMT (Single Instruction Multiple Threads) programming model, WAVE32, WAVE64, and WAVE128 are 32, 64, and 128 threads (and data) that jointly execute the same instruction sequence), WAVE64 (a data processing Data processing is completed by 64 threads in the process), WAVE128 (data processing is completed by 128 threads in a data processing process) are not compatible, here we take the incompatible scheme of WAVE32 and WAVE128 as an example, if the register set has several rows and several columns register matrix, the number of columns of the register set is 32, then the data to be calculated stored in the WAVE32 data processing mode is a whole line, and the data to be calculated stored in the WAVE128 data processing mode is 4 whole lines. When the repeat (or weighing operation) or burst (or jump) needs to be added and accumulated on the basis of the address of the register group, the WAVE128 data processing mode logically adds 1 and the WAVE32 data processing mode Logically adding 1 is not equivalent. If the two are forced to be processed together, an address access error will occur. In other words, the register set in the related art cannot be compatible with the data processing modes of WAVE32 and WAVE128 at the same time. In other words, there is no data processing mode in the related art, only a fixed data processing mode.

In view of this, the embodiment of the present disclosure provides a data processing method, which can receive the instruction to be operated, and then determine the operation method and the interaction address corresponding to the data to be operated according to the instruction to be operated, and obtain the data based on the interaction address. The data to be operated stored in the register group finally generates an operation result according to the data to be operated and the operation mode. The embodiment of the present disclosure can perform process interaction through the interaction address recorded with the alignment offset of the row address of the storage area, and convert the logical address of the data to be operated in the register set in different data processing modes to the interaction in the preset data processing mode The way of the address makes the register group compatible with saving the data to be calculated in different data processing modes, and also compatible with the operation and processing of the data to be calculated in different data processing modes, which is beneficial to improve the access flexibility of the register group.

Referring to FIG. 1, FIG. 1 shows a flow chart of a data processing method according to an embodiment of the present disclosure. With reference to FIG. 1, the processing method is applied to a graphics processor. In one example, the graphics The processor is heterogeneously connected to the host, and the graphics processor includes a computing core and a register set. The processing method includes: step S100, receiving an instruction to be calculated. Exemplarily, the above instruction to be operated may be expressed as an operator, such as addition, multiplication, etc., and the operators of multiple data to be operated may be the same. In one example, if the graphics processor is connected to the host, the instruction to be executed can be sent by the host.

Step S200, according to the instruction to be operated, determine the operation mode and the interaction address corresponding to the data to be operated, and obtain the data to be operated stored in the register group based on the interaction address. Wherein, the interactive address includes: a row address alignment offset of the storage area, and an intermediate address of the storage area. The row address alignment offset of the storage area is used to represent the address offset of the data to be operated in the storage area in a preset data processing mode. The intermediate address of the storage area is used to represent the intermediate address of the data to be calculated in the corresponding storage area. The composition of the interactive address will be described in detail later. The above-mentioned intermediate address may be between the conversion process of the physical address and the logical address to realize the conversion between different addresses, as long as there is a corresponding relationship between the intermediate address and the physical address and the logical address. In an example, the instruction to be operated may include an operation code and an operation field, wherein the operation code is used to represent the above-mentioned operation mode, and the operation field is used to be parsed to obtain the above-mentioned interaction address, and the specific conversion relationship may depend on the actual situation.

Step S300, generating a calculation result according to the data to be calculated and the calculation method. In one example, the above calculation results can be stored in the storage medium of the graphics processor. If the graphics processor is connected to the host, the host can access the storage medium after receiving the calculation completion signal from the graphics processor to obtain the above calculation. result. In another example, the above calculation result can be converted into a display signal of a display screen connected to a graphics processor only by data processing in the related art, so as to realize the display of the picture.

In a possible implementation manner, in step S200, obtaining the data to be calculated stored in the register set based on the interaction address in step S200 may include: obtaining the data to be calculated based on the interaction address through multiple pipelines of the graphics processor. The data to be operated stored in the above register group. Step S300 may include: generating an operation result corresponding to each data to be operated according to the data to be operated and the operation mode through multiple pipelines of the graphics processor. Exemplarily, the graphics processor can access the above-mentioned interactive address through at least one pipeline to obtain the data to be operated, and perform operations on it based on the instruction to be operated. The embodiment is not limited here, and the developer can set it according to the actual situation. Exemplarily, the calculation related to the address can be calculated at the instruction parsing address unit in the computing core, or placed in the register bank for calculation, which is not limited in this embodiment of the present disclosure. Exemplarily, here, a single thread instance handles data processing of an addition operation as an example, thread index_n processes A array element A[index_n] + B array element B[index_n], and array A[5] ={1, 3, 5, 7, 9} is added to the array B[5]={2, 4, 6, 8, 10} for example, to get 3 (1+2), 7 (3+4), 11 (5+6), 15 (7+8), 19 (9+10) are the results of the above operators, and the array C[5]={3, 7, 11, 15, 19} is the result of the above operations.

In a possible implementation manner, generating an operation result corresponding to each data to be operated according to the data to be operated and the operation mode through multiple pipelines of the graphics processor includes: In the case that there are different pipelines in the multiple pipelines of the graphics processor accessing the target port of the register group at the same time, arbitration is performed according to the priorities of the different pipelines and/or the priority of the read and write operations to determine the target port Corresponding target pipeline. Exemplarily, the above-mentioned priority of the pipeline and the priority of the read and write operations are not limited in this embodiment of the present disclosure, and developers can set them according to actual requirements. For example, the priority of the above-mentioned pipelines may be related to the timing and numbering sequence corresponding to the pipelines. Then, through the target pipeline and other pipelines in the different pipelines in sequence, according to the data to be calculated and the calculation method, a calculation result corresponding to each data to be calculated is generated. Referring to FIG. 2, FIG. 2 shows a flowchart of a data processing method according to an embodiment of the present disclosure. In a possible implementation, the register set includes at least one storage area, for example , the above-mentioned register group can be represented as a general-purpose data register group, each storage area of which includes several registers. The processing method further includes: Step S10, receiving a plurality of data to be calculated. In an example, the plurality of data to be operated corresponds to an operation sequence. Exemplarily, the above-mentioned multiple data to be operated can be expressed as vectors, arrays, matrices, etc., and the elements in them can have the attribute of operation sequence, which can be used to divide the data to be operated and store each element The sequence is determined, etc. Taking an array as an example here, the above-mentioned instruction to be operated can be expressed as an addition between arrays, and multiple data to be operated can include: array A[5] = {1, 3, 5, 7, 9} and array B[5] ={2, 4, 6, 8, 10}, then A[0]+B[0], A[1]+B[1], A[2]+B[2], A[3] ]+B[3], A[4]+B[4] to get a new array C[5]={3, 7, 11, 15, 19}. In one example, if the graphics processor is connected to the host, multiple pieces of data to be calculated may be sent by the host, and the specific data content may depend on the upper-layer tasks running on the host.

Step S20, dividing the plurality of data to be operated into a plurality of data groups to be operated according to the data processing modes corresponding to the plurality of data to be operated on. Wherein, different data processing modes correspond to different amounts of data to be operated in the data group to be operated. Exemplarily, the above-mentioned data processing mode may include WAVE32, WAVE64, WAVE128, etc. in the related art. Here, WAVE32 is used as an example. If there are 64 data to be calculated, the multiple data to be calculated may correspond to 2 segments of WAVE32. processing, each WAVE32 includes 32 threads (threads 0 to 31), and the threads with corresponding numbers can be assigned according to the operation order of the plurality of data to be operated (in other examples, it can also be assigned by other rules, this disclosure Examples are not limited here). Continuing with the example of array A[5] = {1, 3, 5, 7, 9}, thread 0 corresponds to number 1, thread 1 corresponds to number 3, until the elements in array A are allocated by WAVE32. If the array A has less than 32 elements during the allocation process, a WAVE32 can still be allocated to it, and some threads in the WAVE32 can be idle. For example, the array A has 50 elements, and after allocating a WAVE32 there are 18 elements left (in this example, one thread corresponds to one element), then another WAVE32 is allocated, and 14 threads in this WAVE32 are idle. Here, taking the data processing modes of WAVE32 and WAVE128 as examples, different data processing modes correspond to different amounts of data to be calculated in the data group to be calculated, which can be expressed as follows: there are 32 threads in WAVE32, corresponding to 32 data to be calculated, There are 128 threads in WAVE128, that is, there are 128 data to be calculated.

In a possible implementation manner, step S20 may include: dividing the plurality of data to be operated into a plurality of data groups to be operated corresponding to task identifiers according to a data processing mode corresponding to the plurality of data to be operated. Wherein, the task identifier is used to map each of the plurality of data groups to be operated to a base address position allocated in the at least one storage area. For example: if the array A has 100 elements, and the corresponding data processing mode is WAVE32, then WAVE32 tasks with task identifiers 0, 1, 2, and 3 can be allocated.

Continue to refer to FIG. 2, step S30, assign the plurality of data groups to be operated to the at least one storage area, and obtain the corresponding interaction address. Wherein, each data group to be operated among the plurality of data groups to be operated is allocated to at least one storage area. The interactive address includes: the row address alignment offset of the storage area, and the middle address of the storage area. The row address alignment offset of the storage area is used to represent the address offset of the plurality of data to be operated in the storage area in a preset data processing mode. The intermediate address of the storage area is used to represent the intermediate address of each data to be calculated in the corresponding storage area. Exemplarily, the row address alignment offset of the storage area in the above-mentioned interaction address may be at a high position, and the middle address of the storage area may be at a low position. In one example, the above-mentioned preset data processing mode can be a data processing mode with a small number of threads. For example, if the developer wants to make the register set compatible with WAVE32, WAVE64, and WAVE128, since WAVE64 can be split into two WAVE32, WAVE128 It can be divided into four WAVE32, and WAVE32 can be used as the above-mentioned preset data processing mode, so that the data processing mode with a larger thread warp can be aligned with the data processing mode with a smaller number of threads. If the total number of bits of the middle address corresponding to WAVE32 is 10 bits, the total number of bits of the middle address corresponding to WAVE128 is 10 bits, and the preset number of bits corresponding to WAVE128 (will be described in detail later) is 2, then the middle address of WAVE128 can be selected The last two bits of the address are used as the row address alignment offset of the above storage area. Of course, the above storage area row address alignment offset may also establish a mapping relationship with the above last two digits, which is not limited in this embodiment of the present disclosure.

In a possible implementation manner, obtaining the interaction address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated in step S30 may include: The address bits from the lowest preset number of bits in the base address of the corresponding logical address are used as the storage area row address alignment offset in the interactive address corresponding to each data to be operated, and the remaining address bits are shifted left by the preset After the number of bits is set, the sum obtained by adding the logical offset address is used as the intermediate address of the storage area in the interactive address corresponding to each data to be operated. Wherein, the logical offset address is an address offset of a logical address corresponding to each data to be operated. Exemplarily, the logical offset address is used to represent the logical offset corresponding to different data to be operated, for example: the logical offset between the 9th data to be operated and the 0th data to be operated is 9. In an example, the above logical address and logical offset address may be obtained by a compiler in a graphics processor, and in an example, the instruction to be operated may include: an operation type and a logical address. In another example, a logical address may include a base address, a logical offset. In one example, different data processing modes correspond to different preset bits. For example, if WAVE32 is used as the default data processing mode, the preset number of digits for WAVE32 can be 0, the preset number of digits for WAVE64 can be 1, and the preset number of digits for WAVE128 can be 2. Referring to FIG. 3, FIG. 3 shows a reference schematic diagram of a data processing method provided according to an embodiment of the present disclosure. In combination with FIG. R_4n to R_4n+3, R0 to R4, where R is Register, shorthand for register) as an example, the data array D[5] to be processed by the first thread instance is {11, 13, 15, 17, 19}, Then 19 is the 4th data to be calculated, and 11 is the 0th data to be calculated (refer to DW0=11 in the first data processing mode in the figure, where DW is the abbreviation of Double-Word, translated It is a double word. In the embodiment of the present disclosure, each register Bank can store 8 double words (refer to DW0 to DW7 in the figure) as an example. Exemplarily, each double word can correspond to a thread for access), In the Wave32 data processing mode (refer to the first data processing mode in the figure), the row address alignment offset of the storage area is 1 row. If the hash bit processing is not considered, the data to be operated 11 is stored in the current task start row In the middle R0 position, the data to be calculated 19 (refer to DW0=19 in the first data processing mode in the figure) is stored in the R4 position of the next row. In the Wave128 data processing mode (refer to the second data processing mode in the figure), the corresponding logical offset is 4 lines (refer to segment 0 to segment 3 in the figure), if the hash bit processing is not considered, the data to be operated 11 is stored in the R0 position in the start line of the current task (refer to DW0=11 in the second data processing mode in the figure), and the data to be calculated 19 is stored in the R4 position of the current task start line with a logical offset of 4 lines (can be Refer to DW0=19 in the second data processing mode in the figure).

Exemplarily, the embodiment of the present disclosure provides a method for generating the alignment offset of the row address of the storage area for reference. Here, the preset data processing mode is WAVE32, and the data processing mode corresponding to multiple data to be operated is For WAVE128 and WAVE32, the total number of bits of the intermediate address is 10 bits, and the total number of bits of the intermediate address corresponding to WAVE128 is 10 bits (the high bits may be filled with 0). For example, the pseudo code is as follows: storage area row address alignment offset base_align_mod4 = (wave_mode == wave32) ? 0 : (base & 0x3), where base is the starting base row address of the current task corresponding to the data to be calculated in the data processing mode, which can be generated by an address generation module. It only needs that the address configuration module can generate the base, which is not limited in this embodiment of the present disclosure. Following the above example, base & 0x3 can get the two lower bits that are not aligned in WAVE128 compared to WAVE32 as the alignment offset of the storage area row address. The specific value can be combined with the actual situation of the developer and then the storage area row address alignment offset Move to the high bit of the interaction address, that is, base_align_mod4<<= const_addr_bit, where const_addr_bit is the total number of bits of the intermediate address of WAVE32, which is 10 in this example, that is, the row address alignment offset of the storage area is used as the 11th bit of the interaction address, The 12th bit, in other words, in this example, the value of const_addr_bit is equal to the total number of bits of the intermediate address in the preset data processing mode. Then, the sum of the value corresponding to other address bits (in this example, the 2nd to 9th bits of WAVE128) and the logical offset address is used as the intermediate address of the storage area in the interactive address corresponding to each address to be calculated. In another example, the interactive address may further include a hash bit (details will be described later), and the value of const_addr_bit is equal to the total number of bits of the intermediate address in the preset data processing mode plus the number of hash bits. Exemplarily, if the data processing mode corresponding to the data to be operated is the same as the preset data processing mode, the storage area row address alignment offset is 0. Exemplarily, the pseudocode for generating the intermediate address ac_addr1 of the storage area is as follows: ac_addr1 = ((base >> base_shift_bit) << 2) + reg_off, wherein, reg_off is the logical offset address after the logical address conversion of the instruction, and base_shift_bit is the address alignment shift deviation. Exemplarily, here is a two-digit difference between the middle address of WAVE32 and the middle address of WAVE128 (filling to the high bit to align the two middle addresses), the default data format is WAVE32, and it is intended to achieve compatibility between WAVE32 and WAVE128 For example, the pseudo code for generating the address alignment shift deviation base_shift_bit is: base_shift_bit = (wave_mode == wave32) ? 0 : 2. Exemplarily, the pseudo code for generating the interaction address ac_addr2 is as follows: ac_addr2 = base_align_mod4 | ac_addr1.

In a possible implementation manner, the interaction address includes: storage area row address alignment offset, storage area intermediate address, and hash value. In step S30, each to-be-operated data group in the plurality of to-be-operated data groups is obtained The interaction address corresponding to each data group to be operated in the data group may include: generating a hash corresponding to each data group to be operated according to the task identifier corresponding to each data group to be operated in the plurality of data groups to be operated value. Wherein, the hash values between adjacent data groups to be operated by the task identifier are different. Exemplarily, the above hash value can be simply divided into parity identifiers, which can be represented by 1 bit (0 indicates even or 1 indicates odd), and the task identifier can be obtained by taking the remainder of 2 to know the parity of the task identifier. or 1 as the above hash. In an example, the lowest bit of the task identifier may also be directly used as the above hash value. The method of generating the above-mentioned task identifier will not be described in detail here in the embodiment of the present disclosure. It can be generated when multiple data to be calculated are divided into different data groups to be calculated, and can represent the calculation sequence of the multiple data groups to be calculated. Of course, in an example, the hash value can also take the remainder of any value of the task identifier, and the number of digits of the hash value will also change accordingly. Just change the value of const_addr_bit above adaptively, and the embodiment of the present disclosure does not limit it here , which can be set by the developer according to the actual situation. Among them, taskid is the task ID. Then, according to the hash value corresponding to each data group to be operated, an interaction address corresponding to each data to be operated in each data group to be operated is generated. Wherein, the data to be calculated in the data group to be calculated corresponding to different hash values are stored in different physical storage areas. Exemplarily, the pseudo-code for generating the hash value is as follows: taskid_hash = (taskid & 0x1) << (const_addr_bit - 1), where the const_addr_bit is 1 bit more than that without the hash bit due to the addition of the hash bit. According to this, the interactive address that can be obtained is: high-order storage area row address alignment offset, hash value, and low-order storage area middle address. Exemplarily, in the case that the interaction address ac_addr2 is generated by a hash value, the pseudo code for generating it may be as follows: ac_addr2 = base_align_mod4 | taskid_hash | ac_addr1.

Referring to FIG. 4, FIG. 4 shows a reference schematic diagram of a data processing method provided according to an embodiment of the present disclosure. With reference to FIG. 4, in an embodiment of the present disclosure, the data processing modes under different hash values The storage methods are different. Here, the preset data processing mode is the second data processing mode, and the register group is the general data register group as an example. The first data processing mode occupies four rows of the general data register group (refer to section 0 to section 3 in the figure ), R0 to R_2N-1 in the figure (where R is the abbreviation of Register, or register) are 2N registers, and only one storage area is shown in the figure, it should be understood that the number of storage areas can be set arbitrarily, It is not limited in the figure. In the figure, the storage methods corresponding to even tasks and odd tasks (which can be represented by the hash value above) in the first data processing mode are interleaved, and the storage methods corresponding to even tasks and odd tasks in the second data processing mode are interleaved. The location of the storage bank is different, so in the reading stage, the parity task can also read information from multiple register columns (or multiple banks, the same bank shares the same communication channel) at the same time, which is conducive to improving the data processing speed. The specific interleaving manner is not limited in this embodiment of the present disclosure, as long as different hash values correspond to different storage sequences of the data to be calculated.

In a possible implementation manner, the interaction address includes: storage area row address alignment offset, storage area intermediate address, and hash value. In step S30, each to-be-operated data group in the plurality of to-be-operated data groups is obtained The interaction address corresponding to each data to be calculated in the data group may include: generating the corresponding address according to the task identification corresponding to each data group to be calculated in the plurality of data groups to be calculated and the sampling identification corresponding to the data group to be calculated. Describe the hash value corresponding to each data group to be operated. Wherein, the sampling identifier is used to indicate a different sampling point for processing of each data group to be operated in the plurality of data groups to be operated. An interaction address corresponding to each data to be operated in each data group to be operated is generated according to the hash value corresponding to each data group to be operated. Wherein, the data to be calculated in the data group to be calculated corresponding to different hash values are stored in different physical storage areas. Exemplarily, the pseudo code for generating the hash value is as follows: taskid_hash = ((taskid& 0x1) ^ (samplerid & 0x1) )<< (const_addr_bit - 1). Wherein, samplerid is the above-mentioned sampling identifier that can be generated by the computing core, and related technologies can be referred to, and the embodiments of the present disclosure will not repeat it here. The data processing method provided by the embodiments of the present disclosure not only takes into account the influence of different task identifiers on the storage Bank location, but also takes into account the influence of the sampling identifier on the storage Bank location, which is conducive to the realization of equalization when the subsequent pipeline accesses the computing data. Helps reduce access conflicts.

In a possible implementation manner, the register group includes a storage area, and the obtaining the data to be operated in the register group based on the interaction address includes: according to the interaction address corresponding to each data to be operated, Determine the row address and column address of each data to be operated in its corresponding storage area. Wherein, the row address and the column address are used to indicate the position of the register in the storage area. Then, according to the row address and the column address of each data to be operated in its corresponding storage area, the corresponding register is accessed to obtain each data to be operated. Exemplarily, in the case where the register group includes only one storage area, each interactive address corresponds to a unique row address and column address, and the corresponding register in the register group can be accessed directly through the row address and column address to obtain Data to be processed. Each interaction address only needs to correspond to a unique row address and column address, and the specific generation corresponding relationship can be determined according to actual needs.

In a possible implementation manner, the register set includes multiple storage areas. In an example, obtaining the data to be operated in the register group based on the interaction address in step S200 may include: for each data to be operated in the plurality of data to be operated, according to the plurality of data to be operated To calculate the data, determine the interaction address and storage area identifier corresponding to each data to be calculated. Wherein, the storage area identification is used to determine the storage area corresponding to each data group to be operated in the plurality of data groups to be operated when the plurality of data groups to be operated is allocated to the plurality of storage areas. Exemplarily, each of the above-mentioned plurality of data groups to be operated can be associated with a storage area identifier, and the specific distribution rules are not limited in this embodiment of the present disclosure, for example, the plurality of data groups to be operated can be Arbitrary, allocated according to the storage space weight of each storage area. In an example, the allocating the plurality of data groups to be operated into the at least one storage area may include: for each data group to be operated in the plurality of data groups to be operated, assigning the Each data group to be operated is equally distributed to each storage area. Here, taking the example of equal division, the processing format of the data to be calculated as WAVE32, and a total of 4 storage areas, the 32 threads in WAVE32 (each thread corresponds to storing a data to be calculated) can be divided into 4 parts, and each 8 Continuous threads are a small thread block and are equipped with a thread block number, that is, thread blocks corresponding to threads 0-7 are stored in storage area 0, threads 8-15 are stored in storage area 1, and threads 16-23 are stored in storage area 1. Threads are stored in storage area 2, and threads 24-31 are stored in storage area 3. Exemplarily, taking a total of four storage areas as an example, the storage areas are identified as the lower two bits of the thread block number to indicate that they are stored in corresponding storage areas. Then, according to the storage area identifier corresponding to each data to be operated, the storage area corresponding to each data to be operated is determined. Exemplarily, the above-mentioned storage area identifiers are in one-to-one correspondence with storage areas. Then, according to the interaction address corresponding to each data to be operated, the row address and the column address of each data to be operated in its corresponding storage area are determined. Wherein, the row address and the column address are used to indicate the position of the register in the storage area. Finally, according to the row address and the column address of each data to be operated in its corresponding storage area, the register in its corresponding storage area is accessed to obtain each data to be operated. Exemplarily, the above-mentioned row address and column address are respectively used to indicate the row number and the column number of the register to be accessed in the register set, so as to accurately access it.

In a possible implementation manner, obtaining the interaction address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated in step S30 may include: generating the plurality of data to be operated The interactive address corresponding to each data to be operated in each data group to be operated in the group. According to the thread number corresponding to the data to be operated and the total number of threads corresponding to the preset data processing mode, the number of segments corresponding to each data to be operated is generated. Wherein, the number of segments represents a segment offset generated when each data to be operated is stored in the preset data processing mode. Exemplarily, each data to be calculated may correspond to a thread. If the data processing mode corresponding to the data to be calculated is WAVE32, the thread number corresponding to the data to be calculated may be 0 to 31. If it is WAVE128, the corresponding thread number may be The number is 0 to 127. The total number of threads corresponding to the above preset data processing modes, if WAVE32 is taken as an example, the total number of threads is 32, and if WAVE128 is taken as an example, the total number of threads is 128. You can directly divide the thread number by the total number of threads in the above segment. For example, if the thread number is 30 and the total number of threads is 32, the corresponding segment number is 0 (30/32=0). For example, if the thread number is 66 (for example, the The data processing mode corresponding to the data to be calculated is WAVE128), and the total number of threads is 32, for example, the corresponding number of segments is 2 (66/32=2). As shown in Figure 4, the first data processing mode generates a segment offset when it is adapted to the preset data processing mode. Here, the first data processing mode is WAVE128, and the default data processing mode is WAVE32. , WAVE128 has a total of 128 threads, and WAVE32 has a total of 32 threads. Therefore, the data format of WAVE128 is processed in the data format of WAVE32, which is equivalent to a WAVE128 including four WAVE32 segments. If each row of registers can store a WAVE32 corresponding The data to be calculated requires a total of 4 lines (or 4 segments), and WAVE128 includes four segments of data to be calculated with the number of segments ranging from 0 to 3 (refer to segment 0 to segment 3 in the figure). The embodiment of the present disclosure handles this situation by setting the number of segments, so as to realize compatible processing of data to be operated in different data processing modes.

Exemplarily, the interaction address is processed first to obtain physical_addr1, the pseudocode is as follows: physical_addr1 = ac_addr2 + burst_offset, burst_offset is the accumulated value corresponding to the repeat instruction or the burst instruction in the related art. Exemplarily, the pipeline can obtain the above physical_addr1, and then process it to obtain the parameters needed to access the data to be operated. Exemplarily, the pseudocode is as follows: base_align_mod4 = (physical_addr1 >> const_addr_bit ) & 0x3, taskid_hash = ((physical_addr1 >> (const_addr_bit - 1)) & 0x1) << 1, segmentid_hash = (4 - segmentid), physical_addr2 = physical_addr1 & (0x1 << (const_addr_bit - 1)) - 0x1. Among them, segmentid is the number of segments, segment_num is the total number of segments in Wave, and the effect of segmentid_hash (or segment number hash) is similar to that of the hash value above, which can improve the balance of pipeline access, that is, it is beneficial to reduce access probability of conflict. In an example, the determining the row address and column address of each data to be operated in its corresponding storage area according to the interaction address corresponding to each data to be operated includes: The interactive address and segment number corresponding to the data are calculated, and the row address of each data to be calculated in its corresponding storage area is generated. Exemplarily, the pseudo code for generating the line address line_addr is as follows: line_addr = ((physical_addr2 >> 2) << base_shift_bit) + segmentid + base_align_mod4. Then, according to the interaction address, segment number, and hash value corresponding to each data to be operated, the column address of each data to be operated in its corresponding storage area is generated, or according to the address corresponding to each data to be operated By interacting with the address and the number of segments, the column address of each data to be operated in its corresponding storage area is generated. Exemplarily, the pseudo code for generating the column address bank_addr is as follows: bank_addr = (taskid_hash + segmentid_hash + (physical_addr2 & 0x3)) % bank_num. Wherein, bank_num is the total number of banks in a storage area. In one example, in order to better support the operation of the pipeline, the operation of reading the data to be calculated can be placed inside the pipeline. When the pipeline is ready to execute the instruction to be calculated, the data to be calculated can be read first, and then the calculation can be performed. The number of segments above can better indicate the access of the data processing mode whose thread number is higher than the preset data processing mode, so as to be compatible with reading data to be operated in different data processing modes. In another example, when different pipelines perform simultaneous read or write operations to the same register bank port, the arbitration decision can be made according to the priority of the pipeline itself. In one example, the read operation and the write operation Operations can also be arbitrated separately, and the above-mentioned priorities and specific arbitration content are not limited in this embodiment of the present disclosure, and developers can set them according to actual conditions. In the embodiment of the present disclosure, when the pipeline finally accesses the register group, the unaligned part can be removed based on physical_addr1, and then the storage area row address alignment offset, hash value, and storage area intermediate address can be separated respectively. The physical address physical_addr2 can be the middle address of the storage area. The middle address of the storage area is shifted to the right and then to the left to be aligned by the number of digits that need to be offset, and then the segment number, hash value, and alignment offset of the row address of the storage area are added to obtain the final access row address. The above-mentioned column address can be obtained by summing the hash value, the segment number hash, and the lower bits of the base_shift_bit number of physical_addr2, and taking the remainder according to the total number of segments. In the embodiments of the present disclosure, the data to be calculated and the instructions to be calculated on each pipeline can be dynamically and cyclically executed multiple times in the form of vector operations, and the resource utilization rate is higher. In terms of hardware implementation, each computing core can include WAVE scheduling and instruction scheduling execution units to achieve compatible management of different WAVEs. Scheduling can be performed according to the execution granularity and execution status of WAVEs, which can improve scheduling efficiency and improve Utilization of each pipeline.

In the data processing method provided by the embodiments of the present disclosure, each group of computing cores can be directly compatible with the WAVE32 data processing mode, and can also be compatible with the WAVE64 mode twice, and compatible with the WAVE128 mode four times. The graphics rendering pipeline in the graphics processor can use the WAVE32 mode to execute the producer-consumer model in related technologies, and it is also compatible with multiple modes of WAVE processing at the same time. According to specific application scenarios, WAVE can be dynamically configured and assembled for data processing. deal with.

It can be understood that the above-mentioned method embodiments mentioned in this disclosure can all be combined with each other to form a combined embodiment without violating the principle and logic. Due to space limitations, this disclosure will not repeat them. Those skilled in the art can understand that, in the above method in the specific implementation manner, the specific execution order of each step should be determined according to its function and possible internal logic.

In addition, this disclosure also provides electronic equipment, computer-readable and writable data storage media, and programs, all of which can be used to implement any data processing method provided by this disclosure, and refer to the corresponding technical solutions and descriptions in the method section. ,No longer.

Referring to FIG. 5, FIG. 5 shows a block diagram of a graphics processor provided according to an embodiment of the present disclosure. With reference to FIG. 5, the graphics processor 100 includes: a computing core 110, registers connected to the computing core Group 120. In one example, the graphics processor 100 may be connected to a host, and the computing core is used to receive instructions to be operated; determine the operation mode and the interactive address corresponding to the data to be operated according to the instructions to be operated, and based on the The interactive address obtains the data to be operated stored in the register group; wherein, the interactive address includes: storage area row address alignment offset, storage area intermediate address; the storage area row address alignment offset is used to represent the The address offset of the data to be calculated in the storage area in the preset data processing mode; the intermediate address of the storage area is used to indicate the intermediate address of the data to be calculated in the corresponding storage area; according to the data to be calculated Computing the data and the computing method to generate a computing result.

In a possible implementation manner, the register set includes at least one storage area, and the computing core is further configured to: receive a plurality of data to be operated; The plurality of data to be operated is divided into a plurality of data groups to be operated; wherein, the amount of data to be operated in the data groups to be operated corresponding to different data processing modes is different; the plurality of data groups to be operated is allocated to the at least In a storage area, an interactive address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated is obtained; wherein, each data group to be operated in the plurality of data groups to be operated are allocated in at least one storage area.

In a possible implementation manner, the obtaining the interaction address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated includes: according to the address corresponding to each data to be operated The address bits from the lowest preset number of bits in the base address of the logical address are used as the storage area row address alignment offset in the interactive address corresponding to each data to be operated, and the remaining address bits are shifted to the left by the preset bits After counting, the sum value obtained by adding the logical offset address is used as the intermediate address of the storage area in the interactive address corresponding to each data to be operated; wherein, the logical offset address is the logical address corresponding to each data to be operated address offset.

In a possible implementation manner, the dividing the plurality of data to be operated into a plurality of data groups to be operated according to the data processing mode corresponding to the plurality of data to be operated includes: according to the plurality of data to be operated The data processing mode corresponding to the operation data divides the plurality of data to be operated into a plurality of data groups to be operated corresponding to task identifiers; wherein, the task identifier is used to map each of the plurality of data groups to be operated The array to be operated is allocated to the base address position in the at least one storage area.

In a possible implementation manner, the interaction address includes: storage area row address alignment offset, storage area intermediate address, and hash value, and each data to be operated in the plurality of data groups to be operated is obtained The interaction address corresponding to each data to be calculated in the group includes: generating a hash value corresponding to each data group to be calculated according to the task identifier corresponding to each data group to be calculated in the plurality of data groups to be calculated; Wherein, the task identifiers have different hash values between adjacent data groups to be operated; according to the hash value corresponding to each data group to be operated, generate the corresponding The interactive address; where, the data to be calculated in the data group to be calculated corresponding to different hash values are stored in different physical storage areas.

In a possible implementation manner, the interaction address includes: storage area row address alignment offset, storage area intermediate address, and hash value, and each data to be operated in the plurality of data groups to be operated is obtained The interaction address corresponding to each data to be calculated in the group includes: generating the each A hash value corresponding to each data group to be operated; wherein, the sampling identifier is used to represent a different sampling point for processing of each data group to be operated in the plurality of data groups to be operated; according to each data group to be operated The hash value corresponding to the group generates the interactive address corresponding to each data to be calculated in each data group to be calculated; wherein, the data to be calculated in the data group to be calculated corresponding to different hash values are stored in different physical storage area.

In a possible implementation manner, the register group includes a storage area, and the obtaining the data to be operated in the register group based on the interaction address includes: according to the interaction address corresponding to each data to be operated, Determine the row address and column address of each data to be operated in its corresponding storage area; wherein, the row address and column address are used to indicate the position of the register in the storage area; according to each data to be operated The row address and column address of the data in its corresponding storage area are accessed to its corresponding register to obtain each of the data to be operated.

In a possible implementation manner, the register set includes a plurality of storage areas, and the obtaining the data to be operated in the register set based on the interaction address includes: For each data to be operated, according to the plurality of data to be operated, an interactive address and a storage area identifier corresponding to each data to be operated are determined; wherein, the storage area identification is used to store the plurality of data to be operated When a group is allocated to multiple storage areas, determine the storage area corresponding to each data group to be calculated among the multiple data groups to be calculated; determine each data to be calculated according to the storage area identifier corresponding to each data to be calculated Corresponding storage area; according to the interactive address corresponding to each data to be operated, determine the row address and column address of each data to be operated in its corresponding storage area; wherein, the row address and column address are used To indicate the position of the register in the storage area; according to the row address and column address of each data to be operated in its corresponding storage area, access the register in its corresponding storage area to obtain the data.

In a possible implementation manner, the obtaining the interaction address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated includes: generating an address in the plurality of data groups to be operated The interactive address corresponding to each data to be calculated in each data group to be calculated; generate each data to be calculated according to the thread number corresponding to the data to be calculated and the total number of threads in the segment corresponding to the preset data processing mode Corresponding segment number; wherein, the segment number represents the segment offset generated by storing each data to be operated in the preset data processing mode; according to the interactive address corresponding to each data to be operated, Determining the row address and column address of each data to be calculated in its corresponding storage area includes: generating the data to be calculated in its corresponding the row address in the storage area of each data to be operated; generate the column address of each data to be operated in its corresponding storage area according to the interactive address, the number of segments, and the hash value corresponding to each data to be operated; or according to the The interactive address and segment number corresponding to each data to be operated are used to generate the column address of each data to be operated in its corresponding storage area.

In a possible implementation manner, the allocating the plurality of data groups to be operated into the at least one storage area includes: for each data group to be operated in the plurality of data groups to be operated, Each of the data groups to be operated is equally distributed to each storage area.

In a possible implementation manner, the acquiring the data to be operated stored in the register set based on the interaction address includes: acquiring the register based on the interaction address through multiple pipelines of the graphics processor The data to be calculated stored in the group; said generating a calculation result according to the data to be calculated and the calculation method includes: passing through multiple pipelines of the graphics processor, according to the data to be calculated and the calculation method , to generate the operation result corresponding to each data to be operated.

In a possible implementation manner, generating an operation result corresponding to each data to be operated according to the data to be operated and the operation mode through multiple pipelines of the graphics processor includes: In the case that there are different pipelines in the multiple pipelines of the graphics processor accessing the target port of the register group at the same time, arbitration is performed according to the priorities of the different pipelines and/or the priority of the read and write operations to determine the target port The corresponding target pipeline: through the target pipeline and other pipelines in the different pipelines in sequence, according to the data to be calculated and the calculation method, an operation result corresponding to each data to be calculated is generated.

This method has a specific technical relationship with the internal structure of the computer system, and can solve the technical problems of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the processing speed of the hardware, etc.), so as to obtain a natural The technical effect of regular computer system internal performance improvements.

In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the method embodiments above, and its specific implementation can refer to the description of the method embodiments above. For brevity, here No longer.

Embodiments of the present disclosure also propose a computer-readable and writable data storage medium, on which computer program instructions and data to be processed are stored, and the above-mentioned method is implemented when the computer program instructions are executed by a processor. The computer readable and writable data storage medium may be a volatile or nonvolatile computer readable and writable data storage medium.

An embodiment of the present disclosure also proposes an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to invoke the instructions stored in the memory to execute the above method.

An embodiment of the present disclosure also provides a computer program product, including computer-readable codes, or a non-volatile computer-readable and writable data storage medium bearing computer-readable codes, when the computer-readable codes are stored in an electronic device When running in the processor of the electronic device, the processor in the electronic device executes the above method.

Electronic devices may be provided as terminal devices, servers, or other forms of devices.

Referring to FIG. 6 , FIG. 6 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or terminal device. Referring to FIG. 6 , electronic device 1900 includes processing component 1922 , which further includes one or more processors, and a memory resource represented by memory 1932 for storing instructions executable by processing component 1922 , such as application programs. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900 , a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input and output interface 1958 . The electronic device 1900 can operate based on the operating system stored in the memory 1932, such as the Microsoft server operating system (Windows Server ^TM ), the operating system based on the graphical user interface (Mac OS X ^TM ) introduced by Apple Inc., and the multi-user and multi-process computer operating system (Unix ^TM ), a free and open-source Unix-like operating system (Linux ^TM ), an open-source Unix-like operating system (FreeBSD ^TM ), or similar.

In an exemplary embodiment, there is also provided a non-volatile computer-readable and writable data storage medium, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above-mentioned method.

The present disclosure can be a system, method and/or computer program product. The computer program product may include a computer readable and writable data storage medium having computer readable program instructions thereon for causing a processor to implement various aspects of the present disclosure.

A computer readable and writable data storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable and writable data storage medium may be, for example (but not limited to), an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples (a non-exhaustive list) of computer readable and writable data storage media include: portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read-only Memories (EPROM or Flash), Static Random Access Memory (SRAM), Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disks (DVD), Memory Sticks, Floppy Disks, Mechanically encoded devices, e.g. Punch cards or raised-in-groove structures of instruction, and any suitable combination of the foregoing. As used herein, computer readable and writable data storage media are not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., pulses of light through fiber optic cables), Or an electrical signal transmitted over a wire.

The computer-readable program instructions described herein can be downloaded from a computer-readable and writable data storage medium to each computing/processing device, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. . The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for computer-readable and writable data stored in each computing/processing device in the storage medium.

Computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or Source or object code written in any combination, including object-oriented programming languages—such as Smalltalk, C++, etc., and conventional procedural programming languages—such as the “C” language or similar programming languages. Computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement. In cases involving a remote computer, the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as through the Internet using an Internet service provider). connect). In some embodiments, electronic circuits, such as programmable logic circuits, field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs), can be customized by utilizing state information of computer-readable program instructions, which can Various aspects of the present disclosure are implemented by executing computer readable program instructions.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It should be understood that each block of the flowcharts and/or block diagrams, and combinations of blocks in the flowcharts and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that when executed by the processor of the computer or other programmable data processing apparatus , producing an apparatus for realizing the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable and writable data storage medium, and these instructions make computers, programmable data processing devices and/or other devices work in a specific way, so that the computer-readable The medium then includes an article of manufacture including instructions for implementing various aspects of the functions/acts specified in one or more blocks in the flowcharts and/or block diagrams.

It is also possible to load computer-readable program instructions into a computer, other programmable data processing device, or other equipment, so that a series of operational steps are performed on the computer, other programmable data processing device, or other equipment to produce a computer-implemented process , so that instructions executed on computers, other programmable data processing devices, or other devices implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

The computer program product can be specifically realized by means of hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), etc. wait.

The above descriptions of the various embodiments tend to emphasize the differences between the various embodiments, the same or similar points can be referred to each other, and for the sake of brevity, details are not repeated herein.

Those skilled in the art can understand that in the above method of specific implementation, the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process. The specific execution order of each step should be based on its function and possible The inner logic is OK.

If the technical solution of this application involves personal information, the product applying the technical solution of this application has clearly notified the personal information processing rules and obtained the individual's independent consent before processing personal information. If the technical solution of this application involves sensitive personal information, the products applying the technical solution of this application have obtained individual consent before processing sensitive personal information, and at the same time meet the requirements of "express consent". For example, at a personal information collection device such as a camera, a clear and prominent sign is set up to inform that it has entered the scope of personal information collection, and personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed to agree to the collection of his personal information; or On the personal information processing device, when the personal information processing rules are informed with obvious signs/information, personal authorization is obtained through pop-up information or by asking individuals to upload their personal information; among them, the personal information processing rules may include Information such as the information processor, the purpose of personal information processing, the method of processing, and the type of personal information processed.

Having described various embodiments of the present disclosure above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims (14)

1. A data processing method, characterized in that it is applied to a graphics processor, and the graphics processor includes a computing core and a register group, and the computing core is used to store data to be calculated in different data processing modes in the registers The logical addresses in the group are converted into interactive addresses in a preset data processing mode; the processing method includes: Receive pending instructions; According to the instruction to be operated, determine the operation mode and the interaction address corresponding to the data to be operated, and obtain the data to be operated stored in the register group based on the interaction address; wherein, the interaction address includes: storage area row address alignment Offset, intermediate address of the storage area; the row address alignment offset of the storage area is used to represent the address offset of the data to be operated in the storage area in the preset data processing mode; the storage The middle address of the area is used to indicate the middle address of the data to be calculated in the corresponding storage area; generating a calculation result according to the data to be calculated and the calculation method; Wherein, the row address alignment offset of the storage area is the address bit from the lowest preset number of digits in the base address of the logical address corresponding to the data to be operated, and the middle address of the storage area is to shift the remaining address bits to the left A sum value obtained by adding a logical offset address to the preset number of bits, and the logical offset address is an address offset of the logical address corresponding to the data to be operated. 2. The processing method according to claim 1, wherein the register set comprises at least one storage area, and the processing method further comprises: Receive multiple data to be calculated; According to the data processing mode corresponding to the plurality of data to be operated, divide the plurality of data to be operated into a plurality of data groups to be operated; wherein, the amount of data to be operated in the data group to be operated corresponding to different data processing modes different; Allocating the plurality of data groups to be operated into the at least one storage area to obtain an interactive address corresponding to each data to be operated in each data group to be operated in the plurality of data groups to be operated; wherein, the Each data group to be operated among the plurality of data groups to be operated is allocated to at least one storage area. 3. The processing method according to claim 1, wherein, according to the data processing mode corresponding to the plurality of data to be operated, the plurality of data to be operated is divided into a plurality of data groups to be operated, including : According to the data processing mode corresponding to the plurality of data to be operated, divide the plurality of data to be operated into a plurality of data groups to be operated corresponding to task identifiers; wherein, the task identifier is used to map the plurality of data to be operated Each array to be operated in the operation data group is allocated to a base address position in the at least one storage area. 4. The processing method according to claim 3, wherein the interactive address comprises: storage area row address alignment offset, storage area intermediate address, hash value, and the obtaining of the plurality of data to be operated The interactive address corresponding to each data to be operated in each data group to be operated in the group, including: According to the task identification corresponding to each data group to be operated in the plurality of data groups to be operated, a hash value corresponding to each data group to be operated is generated; wherein, the task identification is between adjacent data groups to be operated different hash values; According to the hash value corresponding to each data group to be operated, an interaction address corresponding to each data group to be operated in each data group to be operated is generated; wherein, different hash values correspond to the data group to be operated Operational data is stored in different physical storage areas. 5. The processing method according to claim 3, wherein the interactive address comprises: storage area row address alignment offset, storage area intermediate address, hash value, and the obtaining of the plurality of data to be operated The interactive address corresponding to each data to be operated in each data group to be operated in the group, including: According to the task identification corresponding to each data group to be operated in the plurality of data groups to be operated, and the sampling identification corresponding to the data group to be operated, generate the hash value corresponding to each data group to be operated; wherein, the The sampling identifier is used to indicate a different sampling point for each data group to be processed in the plurality of data groups to be processed; According to the hash value corresponding to each data group to be operated, an interaction address corresponding to each data group to be operated in each data group to be operated is generated; wherein, different hash values correspond to the data group to be operated Operational data is stored in different physical storage areas. 6. The processing method according to claim 1, wherein the register set includes a storage area, and the acquisition of the data to be operated stored in the register set based on the interaction address comprises: According to the interactive address corresponding to each data to be operated, determine the row address and column address of each data to be operated in its corresponding storage area; wherein, the row address and column address are used to indicate the the location of the register; According to the row address and column address of each data to be operated in its corresponding storage area, access its corresponding register to obtain each data to be operated. 7. The processing method according to claim 1, wherein the register set includes a plurality of storage areas, and the acquisition of the data to be operated stored in the register set based on the interaction address comprises: For each data to be operated in the plurality of data to be operated, according to the plurality of data to be operated, determine an interaction address and a storage area identifier corresponding to each data to be operated; wherein, the storage area identification is used When allocating the plurality of data groups to be operated into a plurality of storage areas, determine the storage area corresponding to each data group to be operated in the plurality of data groups to be operated; Determine the storage area corresponding to each data to be calculated according to the storage area identifier corresponding to each data to be calculated; According to the interactive address corresponding to each data to be operated, determine the row address and column address of each data to be operated in its corresponding storage area; wherein, the row address and column address are used to represent the storage the location of the register in the region; According to the row address and column address of each data to be operated in its corresponding storage area, access the register in its corresponding storage area to obtain each data to be operated. 8. The processing method according to claim 2, wherein said obtaining the interactive address corresponding to each data to be operated in each data group to be operated in said plurality of data groups to be operated comprises: Generate an interaction address corresponding to each data to be operated in each data group to be operated among the plurality of data groups to be operated; According to the thread number corresponding to the data to be calculated and the total number of threads corresponding to the preset data processing mode, the number of segments corresponding to each data to be calculated is generated; wherein, the number of segments indicates that each data to be calculated is in the The segment offset generated by storage in the preset data processing mode; The determining the row address and column address of each data to be calculated in its corresponding storage area according to the interaction address corresponding to each data to be calculated includes: Generate a row address of each data to be calculated in its corresponding storage area according to the interactive address and segment number corresponding to each data to be calculated; According to the interaction address, segment number, and hash value corresponding to each data to be operated, generate the column address of each data to be operated in its corresponding storage area, or according to the interaction corresponding to each data to be operated The address and the number of segments generate the column address of each data to be operated in its corresponding storage area. 9. The processing method according to claim 2, wherein said distributing said plurality of data groups to be operated into said at least one storage area comprises: for said plurality of data groups to be operated For each data group to be operated, the data group to be operated is equally distributed to each storage area. 10. The processing method according to claim 1, wherein said obtaining the data to be calculated based on said interactive address and stored in said register bank comprises: passing through a plurality of pipelines of said graphics processor, based on said interactive address Obtain the data to be calculated stored in the register group through the interactive address; The generating an operation result according to the data to be operated and the operation method includes: Through the plurality of pipelines of the graphics processor, according to the data to be operated and the operation mode, an operation result corresponding to each data to be operated is generated. 11. The processing method according to claim 10, characterized in that, the plurality of pipelines of the graphics processor generates an operation corresponding to each data to be operated according to the data to be operated and the operation mode Results, including: In the case that there are different pipelines in the multiple pipelines of the graphics processor simultaneously accessing the target port of the register group, arbitration is performed according to the priorities of the different pipelines and/or the priorities of the read and write operations to determine the The target pipeline corresponding to the target port; Through the target pipeline and other pipelines in the different pipelines in sequence, according to the data to be calculated and the calculation method, a calculation result corresponding to each data to be calculated is generated. 12. A graphics processor, characterized in that the graphics processor comprises: a computing core, a register set connected to the computing core, and the computing core is used to transfer data to be calculated in different data processing modes in the The logical address in the register bank is converted into the interactive address in the preset data processing mode; The calculation core is also used to receive the instruction to be operated; according to the instruction to be operated, determine the operation mode and the interaction address corresponding to the data to be operated, and obtain the data to be operated stored in the register group based on the interaction address; Wherein, the interactive address includes: storage area row address alignment offset, storage area intermediate address; the storage area row address alignment offset is used to indicate that the data to be operated is in the preset data processing mode address offset in the storage area; the intermediate address of the storage area is used to represent the intermediate address of the data to be calculated in the corresponding storage area; according to the data to be calculated and the calculation method, an operation result is generated; Wherein, the row address alignment offset of the storage area is the address bit from the lowest preset number of digits in the base address of the logical address corresponding to the data to be operated, and the middle address of the storage area is to shift the remaining address bits to the left A sum value obtained by adding a logical offset address to the preset number of bits, and the logical offset address is an address offset of the logical address corresponding to the data to be operated. 13. An electronic device, comprising: a host, and the graphics processor according to claim 12. 14. A computer-readable and writable data storage medium, on which computer program instructions and data to be calculated are stored, characterized in that, when the computer program instructions are executed by a processor, the computer program instructions in any one of claims 1 to 11 are implemented. The data processing method described above.