CN116346126A - Novel all-digital delay phase-locked loop circuit - Google Patents
Novel all-digital delay phase-locked loop circuit Download PDFInfo
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- CN116346126A CN116346126A CN202310318865.1A CN202310318865A CN116346126A CN 116346126 A CN116346126 A CN 116346126A CN 202310318865 A CN202310318865 A CN 202310318865A CN 116346126 A CN116346126 A CN 116346126A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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Abstract
The application provides a novel all-digital delay phase-locked loop circuit, which comprises: a phase detector, a controller and a delay line. The phase discriminator is used for judging the phase difference between the reference clock signal and the delayed output clock signal and outputting a judging result signal to the controller; the controller is used for generating an adjustment control signal based on the judging result signal and outputting the adjustment control signal to the delay line; the delay line is used for receiving an input clock signal, generating a delayed output clock signal based on the adjustment control signal, and outputting the delayed output clock signal to the phase discriminator; the delay line comprises a plurality of different sub-delay circuits which are correspondingly started or closed based on the adjustment control signals so as to carry out delay adjustment on the input clock signals and generate delayed output clock signals. The circuit has the advantages of high locking speed, high locking precision, no harmonic locking and large adaptive clock frequency.
Description
Technical Field
The application relates to the technical field of Delay-locked loop (DLL) circuits, in particular to a novel all-digital Delay-locked loop circuit.
Background
With the rapid development of deep submicron CMOS semiconductor technology, more and more functional modules are integrated on the same chip, and a clock signal is required to synchronize the modules so that the system works correctly and orderly. Delay-locked loop (DLL) is widely used to solve the problems of clock skew and clock generation. The delay locked loop mainly comprises three major circuit modules, namely a Phase Comparator (PC), a variable delay line (Variable Delay Line, VDL) and a Control Block (Control Block), as shown in fig. 1. The working principle is that the output clock signal is delayed to align with the phase of the input reference clock, so that the purpose of eliminating clock deviation is achieved, namely, the length of a variable delay line is automatically adjusted through the self negative feedback closed loop working characteristic, the optimal delay line length is searched out, and the optimal delay line length is inserted between the input clock and the output clock, so that the input clock and the output clock are synchronized.
Depending on the implementation of the module circuits, the delay locked loop can be divided into three types, namely full analog, mixed signal and full digital. Among them, although the all-digital delay locked loop (All Digital Delay Locked Loop, ADDLL) has a shorter locking time and a stronger capability of resisting process, voltage and temperature variations than the other two delay locked loops, it still has drawbacks: the maximum delay time provided by the all-digital shift register delay phase-locked loop determines the locking frequency range and the lowest working frequency, the locking frequency range and the lowest working frequency can be widened by increasing the number of delay units in the numerical control delay line, but a register is correspondingly increased when one delay unit is added, and obviously, the occupied chip area is obviously increased; the delay phase-locked loop of the all-digital counter can solve the problem of the delay phase-locked loop of the all-digital shift register, but the locking time required by the delay phase-locked loop does not meet the requirements of a high-speed storage interface circuit and the like; the all-digital successive approximation register delay locked loop can solve the problems of the all-digital counter delay locked loop proposed above, but there may be problems of harmonic locking and/or deadlock, and locking times longer than theoretical.
Disclosure of Invention
In view of the foregoing, the present application provides a novel all-digital delay locked loop circuit, which aims to solve or partially solve the technical defects existing in the prior art. The novel all-digital delay phase-locked loop circuit has the advantages of higher locking speed, higher locking precision, no harmonic locking and capability of adapting to larger clock frequency.
Specifically, the application is realized by the following technical scheme:
the application provides a novel all-digital delay phase-locked loop circuit, the novel all-digital delay phase-locked loop circuit includes: a phase detector, a controller, and a delay line, wherein,
the phase discriminator is used for receiving the reference clock signal and the delayed output clock signal, judging the phase difference between the reference clock signal and the delayed output clock signal, generating a judging result signal and outputting the judging result signal to the controller;
the controller is used for generating an adjustment control signal based on the judging result signal and outputting the adjustment control signal to the delay line;
the delay line is configured to receive an input clock signal, where the input clock signal is the reference clock signal or a delayed output clock signal, generate a delayed output clock signal based on the adjustment control signal, and output the delayed output clock signal to the phase detector; the delay line comprises a plurality of sub-delay circuits with different delay effects, and the output clock signal after delay generated based on the adjustment control signal comprises a plurality of sub-delay circuits which are correspondingly started or closed based on the adjustment control signal to delay and adjust the input clock signal to generate the output clock signal after delay.
Preferably, the adjustment control signal is configured to control activation of one of the plurality of sub-delay circuits to perform delay adjustment on the input clock signal.
Preferably, a lookup table is preset in the controller, and the generating the adjustment control signal based on the determination result signal includes:
receiving a judgment result signal output by the phase discriminator;
determining an adjustment strategy based on the judgment result signal and the lookup table;
and generating an adjustment control signal based on the adjustment strategy.
Preferably, the lookup table is an amplitude information table, and the determining an adjustment policy based on the determination result signal and the lookup table includes:
according to the judging result signal, searching the amplitude to be adjusted in the amplitude information table;
selecting a sub-delay circuit to be started according to the amplitude to be regulated;
and determining an adjustment strategy based on the magnitude of the amplitude to be adjusted and the sub-delay circuit to be started.
Preferably, the delay line includes four sub-delay circuits of a first coarse delay circuit, a second coarse delay circuit, a first fine delay circuit, and a second fine delay circuit, respectively; the four sub-delay circuits are sequentially connected and the delay adjustment step sizes of the four sub-delay circuits are sequentially reduced, the delay adjustment step size of the first coarse adjustment delay circuit is largest, and the delay adjustment step size of the second fine adjustment delay circuit is smallest.
Preferably, an input clock signal is input from an input terminal of the first coarse tuning delay circuit, and a delayed output clock signal is output from an output terminal of the second fine tuning delay circuit.
Preferably, the first coarse tuning delay circuit comprises an LDU circuit, the LDU circuit comprises a plurality of first coarse tuning delay units, and each first coarse tuning delay unit comprises two serially connected not-gate circuits.
Preferably, the second coarse tuning delay circuit comprises a CCDU circuit including a controllable delay line circuit and an SR flip-flop coupled to the controllable delay line circuit.
Preferably, the first fine delay circuit includes a CDU circuit, and the CDU circuit includes a plurality of first fine delay units, each of which includes a delay element, an and gate, and a data selector, an output terminal of the delay element is connected to one input terminal of the and gate, and an output terminal of the and gate is connected to one input terminal of the data selector.
Preferably, the second fine delay circuit comprises an FDU circuit including a plurality of second fine delay units, each second fine delay unit including a plurality of nand gates connected in parallel.
According to the scheme, the beneficial effects of the application are as follows:
the delay line in the novel all-digital delay phase-locked loop circuit comprises a plurality of sub-delay circuits, and the delay effect of each sub-delay circuit is different, so that a plurality of different delay ranges from thick to thin can be realized; before delay adjustment is carried out on an input clock signal, a controller controls the starting and closing of a plurality of sub-delay circuits according to the phase difference between the input clock signal and an output clock signal judged by a phase discriminator, and the adjustment of the output clock signal can be realized with maximum efficiency; in addition, the circuit provided by the application does not need to divide the input clock signal by using a frequency divider, and the problem of harmonic locking caused by frequency division is avoided; in addition, the maximum delay of each sub-delay circuit can be programmed and adjusted according to different clock frequencies, and can adapt to a plurality of different clocks.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art delay locked loop circuit;
fig. 2 is a schematic structural diagram of a novel all-digital delay locked loop circuit according to an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram of an LDU circuit in the embodiment of FIG. 2;
FIG. 4 is a schematic diagram of a CCDU circuit in the embodiment of FIG. 2;
FIG. 5 is a schematic diagram of the structure of a CDU circuit in the embodiment of FIG. 2;
FIG. 6 is a schematic diagram of the construction of an FDU circuit in the embodiment of FIG. 2;
fig. 7 is a schematic diagram of a delay adjustment result provided in an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The figures are not necessarily to scale and in some instances, the proportions may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter or may be electrically connected or coupled to the latter via one or more intervening elements therebetween. Furthermore, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements may also be present.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could also be termed a second element, and, similarly, a second element could also be termed a first element, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
It will be further understood that the terms "comprises," "comprising," "includes," and "including" when used in this application specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. Unless defined otherwise, all terms including technical and scientific techniques used by embodiments of the invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs in view of the embodiments of the invention. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the embodiments and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention, and the invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention. It is also to be understood that in some cases, unless otherwise specified, features or elements described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment as would be apparent to one of ordinary skill in the relevant arts. Hereinafter, various embodiments of the present invention are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate an understanding of embodiments of the invention. Well-known technical details may be omitted so as not to obscure the features and aspects of the embodiments of the invention.
In the related art, a delay line is used for a delay locked Loop to replace a voltage-controlled oscillator in a Phase-locked Loop (PLL), so that stability is easier to achieve, and in particular, an all-digital delay locked Loop has unconditional stability. The all-digital delay phase-locked loop is evolved from a traditional analog delay phase-locked loop and can be divided into an all-digital shift register delay phase-locked loop, an all-digital counter delay phase-locked loop and an all-digital successive approximation register delay phase-locked loop. In order to solve the problem that the delay phase-locked loop of the all-digital shift register obviously increases the chip area when the locking frequency range is widened, the delay phase-locked loop of the all-digital counter is provided; in order to solve the problem that the delay phase-locked loop of the all-digital shift register and the delay phase-locked loop of the all-digital counter also need longer locking time, the delay phase-locked loop of the all-digital successive approximation register is provided, but an input clock can be used as a clock of the successive approximation register after frequency division, so that the problem of harmonic locking caused by frequency division is solved.
Therefore, the present application provides a novel all-digital delay phase-locked loop to solve or partially solve the technical defects existing in the prior art.
The novel all-digital delay phase-locked loop provided by the application is further described below with reference to the accompanying drawings and specific embodiments. Features of the embodiments described below may be combined with each other without conflict.
Fig. 2 is a schematic structural diagram of a novel all-digital delay locked loop circuit according to an exemplary embodiment of the present application. Referring to fig. 2, the novel all-digital delay locked loop circuit includes: phase Detector (Phase Detector), controller (Controller), and Delay Line (Delay Line), wherein,
the Phase Detector (Phase Detector) is configured to receive a reference clock signal and a delayed output clock signal, determine a Phase difference between the reference clock signal (ref_clk) and the output clock signal (out_clk), generate a determination result signal, and output the determination result signal to the controller;
the Controller (Controller) is used for generating an adjustment control signal based on the judging result signal and outputting the adjustment control signal to the delay line;
the Delay Line is configured to receive an input clock signal, where the input clock signal is the reference clock signal or a delayed output clock signal, generate a delayed output clock signal based on the adjustment control signal, and output the delayed output clock signal to the phase detector; the delay line comprises a plurality of sub-delay circuits with different delay effects, the output clock signal after delay generated based on the adjustment control signal comprises a plurality of sub-delay circuits which are correspondingly started or closed based on the adjustment control signal to delay the input clock signal to generate the output clock signal after delay
It should be noted that the novel ADDLL circuit shown in fig. 2 is a negative feedback control loop, and the working principle thereof may be as follows:
the phase discriminator compares the reference clock signal with the delayed output clock signal to obtain a phase difference between the reference clock signal and the delayed output clock signal, generates a judging result signal and outputs the judging result signal to the controller; after receiving the judging result signal, the controller generates an adjusting control signal for controlling the work of the delay line according to the judging result signal and outputs the adjusting control signal to the delay line; and after the delay line receives the adjustment control signal, a plurality of sub-delay circuits are correspondingly started or closed according to the adjustment control signal, and the started sub-delay circuits perform delay adjustment on an input clock signal input to the delay line according to the adjustment control signal and generate a delayed output clock signal.
The foregoing description of the working principle is only a delay adjustment process of the ADDLL circuit shown in fig. 2, and in a practical application process, the delay adjustment process of the circuit for the input clock signal is a dynamic process, which is continuously adjusted according to the phase difference between the output clock signal after delay received in real time and the reference clock signal input initially, until there is no phase difference therebetween or the phase difference is within a preset range, that is, the reference clock signal and the output clock signal after delay of the ADDLL circuit are synchronized (or aligned).
The input clock signal of the input delay line is a reference clock signal or a delayed output delay signal; when delay adjustment is performed for the first time, the input clock signal is the reference clock signal; after the delayed output clock signal is generated through the first delay adjustment, the delayed output clock signal is called a first output clock signal for convenience of distinction, the first output clock signal is input into a phase discriminator, and the phase discriminator judges the phase difference between the first output clock signal and a reference clock signal, generates a judging result signal and outputs the judging result signal to a controller; the controller determines whether delay adjustment is needed again according to the judging result signal, and if so, generates an adjustment control signal again and outputs the adjustment control signal to the delay line; the delay line further carries out delay adjustment on the first output clock signal with input delay according to the adjustment control signal to generate a second output clock signal; the second output clock signal is also input to the phase detector and compared with the reference clock signal to obtain a phase difference, and the controller determines whether delay adjustment is still required according to the phase difference.
It should be noted that, in this embodiment, the adjustment control signal is configured to control one of the plurality of sub-delay circuits to be started to perform delay adjustment on the input clock signal, that is, each time the delay line performs delay adjustment, only one of the plurality of sub-delay circuits is started to perform delay adjustment, and the other sub-delay circuits are turned off.
The delay line in the novel all-digital delay phase-locked loop circuit comprises a plurality of sub-delay circuits, and the delay effect of each sub-delay circuit is different, so that a plurality of different delay ranges from thick to thin can be realized; before delay adjustment is carried out on an input clock signal, a controller controls the starting and closing of a plurality of sub-delay circuits according to the phase difference between the input clock signal and an output clock signal judged by a phase discriminator, and the adjustment of the output clock signal can be realized with maximum efficiency; in addition, the circuit provided by the application does not need to divide the input clock signal by using a frequency divider, and the problem of harmonic locking caused by frequency division is avoided; in addition, the maximum delay of each sub-delay circuit can be programmed and adjusted according to different clock frequencies, and can adapt to a plurality of different clocks.
Furthermore, since the digital lookup table technology is simpler and easier to implement, in this embodiment, a lookup table is preset in the controller, and the lookup table is used for the controller to generate the adjustment control signal more quickly according to the determination result signal output by the phase detector. The process of generating the adjustment control signal based on the determination result signal may be as follows:
firstly, receiving a judging result signal output by the phase discriminator; determining an adjustment strategy based on the judgment result signal and the lookup table; and finally, generating an adjustment control signal based on the adjustment strategy.
Preferably, the look-up table is an amplitude information table, and determining the adjustment policy based on the determination result signal and the look-up table includes: according to the judging result signal, searching the amplitude to be adjusted in the amplitude information table; selecting a sub-delay circuit to be started according to the amplitude to be regulated; and determining an adjustment strategy based on the magnitude of the amplitude to be adjusted and the sub-delay circuit to be started.
A plurality of judging conditions or another lookup table can be preset in the controller, and the judging conditions or the another lookup table are used for the controller to determine the sub-delay circuit to be started according to the searched amplitude to be adjusted. For example, the judgment conditions may include: if the amplitude to be adjusted is larger than A, starting the A sub-delay circuit; if the amplitude to be adjusted is larger than B but not larger than A, starting a B sub-delay circuit; if the amplitude to be adjusted is larger than C but not larger than B, starting a C sub-delay circuit; if the amplitude to be adjusted is greater than D but not greater than C, the D sub-delay circuit is activated. The lookup table is similar to the above, and the corresponding sub-delay circuit to be started is found in the lookup table according to the amplitude to be adjusted.
In an actual application process, the delay line may include four sub-delay circuits respectively including a first coarse delay circuit, a second coarse delay circuit, a first fine delay circuit, and a second fine delay circuit; the four sub-delay circuits are sequentially connected and the delay adjustment step sizes of the four sub-delay circuits are sequentially reduced, the delay adjustment step size of the first coarse adjustment delay circuit is largest, and the delay adjustment step size of the second fine adjustment delay circuit is smallest.
In the above-mentioned delay line, the input clock signal is input from the input end of the first coarse tuning delay circuit, the delayed output clock signal is output from the output end of the second fine tuning delay circuit, that is, the clock signal is input from the sub-delay circuit with the largest delay adjustment step length and then output from the sub-delay circuit with the smallest delay adjustment step length, but only one of the four sub-delay circuits is started at a time, and the other is bypass. For example, if the magnitude of the required adjustment determined by the controller is larger, it is determined that the first coarse delay circuit is started, the other three sub-delay circuits are closed, when the first coarse delay circuit is adjusted, the phase detector again determines the phase difference between the delayed output clock signal generated by the first coarse delay circuit and the reference clock signal and outputs the result to the controller, the controller determines that the sub-delay circuit is required to be started, if the phase difference is still relatively larger but smaller than the adjustment step of the first coarse delay circuit, the second coarse delay circuit is opened, the first coarse delay circuit is closed, and the input clock signal directly bypass the first coarse delay circuit to the second coarse delay circuit for delay adjustment, i.e. the input clock signal received by the second coarse delay circuit is the output clock signal of the first coarse delay circuit, but the output clock signal of the first coarse delay circuit is identical to the input clock signal of the first coarse delay circuit.
In practical applications, the first coarse delay circuit may include an LDU circuit (Leakage Delay Unit), as shown in fig. 3, where the LDU circuit includes 32 first coarse delay units, and each first coarse delay unit includes two serially connected not-gate circuits.
When the delay line comprises the first coarse tuning delay circuit, the LDU circuit is started or closed according to the adjustment control signal output by the controller, if the adjustment control signal output by the controller comprises an array FAST with a value, the LDU circuit is started, and the corresponding number of the first coarse tuning delay units are started according to the value of the array FAST to delay and adjust an input clock signal to generate a delayed output clock signal, wherein the input clock signal can be a reference clock signal or an output clock signal delayed by the first coarse tuning delay circuit; the plurality of FAST groups are in one-to-one correspondence with the 32 first coarse tuning delay units, namely, each FAST value controls two NOT circuits, the delay of the two NOT circuits is the delay adjustment step length of one FAST value, and the first coarse tuning delay units only play a role in delay adjustment when the corresponding FAST value is 1.
In practice, the second coarse tuning delay circuit may include a CCDU circuit (Cycle Controlled Delay Unit) including a controllable delay line circuit and an SR flip-flop coupled to the controllable delay line circuit as shown in fig. 4.
When the delay line comprises the second coarse tuning delay circuit, the CCDU circuit is started or closed according to the adjustment control signal output by the controller, if the adjustment control signal output by the controller comprises count and the value of the count is 0, the first coarse tuning delay circuit of the input clock signal bypass is started, the controllable delay line circuit carries out delay adjustment on the input clock signal, and the delayed clock signal enters the SR trigger to generate a delayed output clock signal; i.e., the input clock signal enters the CCDU circuit via the first coarse delay circuit but the first coarse delay circuit is not enabled; the input clock signal may be a reference clock signal, an output clock signal delayed by the first coarse delay circuit, or an output clock signal delayed by the second coarse delay circuit; the value of the delay is also determined by the controller, i.e. the control signal of the adjustment of its output may control the CCDU to start and delay a specific value.
In the practical application process, the first fine delay circuit includes a CDU circuit (Coarse Delay Unit), as shown in fig. 5, where the CDU circuit includes a plurality of first fine delay units, each of the first fine delay units includes a delay element, an and gate, and a data selector, an output end of the delay element is connected to one input end of the and gate, and an output end of the and gate is connected to one input end of the data selector.
In the case that the delay line includes the first fine delay circuit, the CDU circuit is started or closed according to the adjustment control signal output by the controller, if the adjustment control signal output by the controller includes an array Coarse with a value, the CDU circuit is started, and a corresponding number of the first fine delay units are started according to the value of the array Coarse to delay and adjust the input clock signal and output the delayed output clock signal, wherein the input clock signal is output to the CDU circuit by the second Coarse delay circuit, and may be the reference clock signal, the output clock signal delayed by the first Coarse delay circuit, the output clock signal delayed by the second Coarse delay circuit, and the output clock signal delayed by the first fine delay circuit. As shown in FIG. 5, the CDU circuit further includes a data selector independent of the first fine delay cells, the data selector having a selection input with a value of Coarse [0 ]]The first fine delay unit is set near the second Coarse delay circuit, and the value input from one input end of AND gate in the first fine delay unit is Coarse 0]And the value input by the selection input end of the data selector is Coarse [1 ]]The method comprises the steps of carrying out a first treatment on the surface of the The value input from one input end of AND gate in the second fine delay unit connected with the first fine delay unit is Coarse 1]And the value input by the selection input end of the data selector is Coarse [2 ]]The method comprises the steps of carrying out a first treatment on the surface of the Input of the subsequent first fine delay unit and so on, one input of the AND gate in the last fine delay unit inputs a value of Coarse [2 ] n -2]And the value input by the selection input end of the data selector is Coarse [2 ] n -1]And the data input by the data input end corresponding to '1' is 0; the first fine delay unit will only perform the delay adjustment when the corresponding Coarse value is 1.
For example, the controller outputs an adjustment control signal including a value Coarse [2 ] n -1:0]The input clock signal directly passes through the first coarse delay circuit and the second coarse delay circuit, directly goes to the CDU circuit to carry out delay adjustment, and then is delayed by the second fine delay circuitThe delay circuit outputs the clock signal output by the CDU circuit to the phase discriminator as a delayed output clock signal, namely the input clock signal sequentially passes through: the first coarse tuning delay circuit-the second coarse tuning delay circuit-the CDU circuit-the second fine tuning delay circuit, but the two former coarse tuning delay circuits and the last second fine tuning delay circuit do not delay the clock signal; and as shown in FIG. 5, only Coarse [0 ]]And Coarse [1 ]]For 1, the CDU circuit enables the first fine delay unit and the second fine delay unit to delay and adjust the input clock signal, the input clock signal is delayed by the delay element 1 of the first fine delay unit and then is input into the AND gate 1, and then is output to the delay element 2 of the second fine delay unit by the AND gate 1, the delay element 2 further inputs the clock signal into the AND gate 2 of the second fine delay unit, because of Coarse [2 ]]～Coarse[2 n -2]The latter first fine delay unit is not enabled any more and gate 2 inputs the delayed clock signal from the "0" terminal of data selector 2, data selector 2 inputs the value according to the selection input terminal (i.e. Coarse 2]=0) outputs data input from the "0" terminal (i.e., delayed clock signal), and from the "1" terminal of the data selector 1, the data selector 1 outputs a value input from the selection input terminal (i.e., coarse [1 ]]=1) outputs the data input from the "1" terminal (i.e. delayed clock signal) and from the "1" terminal independently of the data selector other than any first fine delay unit, which data selector is based on the value input from the selection input terminal (i.e. Coarse [0 ]]=1) output data (i.e., delayed clock signal) input from the "1" terminal, i.e., delayed output delay signal generated for this adjustment process.
In the practical application process, the second Fine Delay circuit includes an FDU circuit (Fine Delay Unit), where the FDU circuit includes a plurality of second Fine Delay units, and each second Fine Delay Unit includes a plurality of parallel nand gates.
In the case where the delay line includes the second fine delay circuit described above, the FDU circuit is turned on or off based on the trim control signal output by the controller. If the adjustment control signal output by the controller includes an array Fine of values, the FDU circuit is started, and a corresponding number of second Fine delay units are started according to the values of the array Fine to delay the input clock signal and output a delayed output clock signal, where the input clock signal is output to the FDU circuit by the first Fine delay circuit, may be a reference clock signal, may be an output clock signal delayed by the first coarse delay circuit, may be an output clock signal delayed by the second coarse delay circuit, may be an output clock signal delayed by the first Fine delay circuit, and may be an output clock signal delayed by the second Fine delay circuit. As shown in fig. 6, the FDU circuit includes a plurality of buffers, a DCV cell is included between two adjacent buffers, each DCV cell includes a plurality of parallel nand gates, the array Fine corresponds to each nand gate one by one, and the number of 1 s in the array Fine determines how many nand gates will be used.
It should be noted that the delay units of all the sub-delay circuits can obtain different delay requirements by selecting different devices. For example, in one embodiment, the LDU circuit selects 20ps per cell (8 cells most/160ps most delay), the CCDU circuit selects 12ps per count,CDU ps per cell (8 cells most), and the FDU circuit selects 1ps per cell (8 cells most), and the simulation result shows that the required output clock signal can be obtained by the fastest 20 clock, i.e. 40ns, of the 500MHZ clock signal, and the experimental result is shown in fig. 7.
As can be seen from the above detailed description of the embodiments, the delay line in the novel all-digital delay locked loop circuit provided by the present application includes a plurality of sub-delay circuits, and the delay effect of each sub-delay circuit is different, so that a plurality of different delay ranges from coarse to fine can be realized; before delay adjustment is carried out on an input clock signal, a controller controls the starting and closing of a plurality of sub-delay circuits according to the phase difference between the input clock signal and an output clock signal judged by a phase discriminator, and the adjustment of the output clock signal can be realized with maximum efficiency; in addition, the circuit provided by the application does not need to divide the input clock signal by using a frequency divider, and the problem of harmonic locking caused by frequency division is avoided; in addition, the maximum delay of each sub-delay circuit can be programmed and adjusted according to different clock frequencies, and can adapt to a plurality of different clocks.
The foregoing description is only a preferred embodiment of the present application, and is not intended to limit the invention to the particular embodiment disclosed, but is not intended to limit the invention to the particular embodiment disclosed, as the equivalent of some alterations or modifications can be made without departing from the scope of the present application.
Claims (10)
1. A novel all-digital delay locked loop circuit, characterized in that the novel all-digital delay locked loop circuit comprises: a phase detector, a controller, and a delay line, wherein,
the phase discriminator is used for receiving the reference clock signal and the delayed output clock signal, judging the phase difference between the reference clock signal and the delayed output clock signal, generating a judging result signal and outputting the judging result signal to the controller;
the controller is used for generating an adjustment control signal based on the judging result signal and outputting the adjustment control signal to the delay line;
the delay line is configured to receive an input clock signal, where the input clock signal is the reference clock signal or a delayed output clock signal, generate a delayed output clock signal based on the adjustment control signal, and output the delayed output clock signal to the phase detector; the delay line comprises a plurality of sub-delay circuits with different delay effects, and the output clock signal after delay generated based on the adjustment control signal comprises a plurality of sub-delay circuits which are correspondingly started or closed based on the adjustment control signal to delay and adjust the input clock signal to generate the output clock signal after delay.
2. The novel all-digital delay locked loop circuit of claim 1, wherein the adjustment control signal is configured to control activation of one of the plurality of sub-delay circuits to delay adjustment of the input clock signal.
3. The novel all-digital delay locked loop circuit of claim 1, wherein a lookup table is preset in the controller, and wherein generating the adjustment control signal based on the determination result signal comprises:
receiving a judgment result signal output by the phase discriminator;
determining an adjustment strategy based on the judgment result signal and the lookup table;
and generating an adjustment control signal based on the adjustment strategy.
4. The novel all-digital delay locked loop circuit of claim 3, wherein the lookup table is an amplitude information table, and wherein determining the adjustment strategy based on the determination result signal and the lookup table comprises:
according to the judging result signal, searching the amplitude to be adjusted in the amplitude information table;
selecting a sub-delay circuit to be started according to the amplitude to be regulated;
and determining an adjustment strategy based on the magnitude of the amplitude to be adjusted and the sub-delay circuit to be started.
5. The novel all-digital delay locked loop circuit of claim 1, wherein the delay line comprises four sub-delay circuits, a first coarse delay circuit, a second coarse delay circuit, a first fine delay circuit, and a second fine delay circuit, respectively; the four sub-delay circuits are sequentially connected and the delay adjustment step sizes of the four sub-delay circuits are sequentially reduced, the delay adjustment step size of the first coarse adjustment delay circuit is largest, and the delay adjustment step size of the second fine adjustment delay circuit is smallest.
6. The novel all-digital delay locked loop circuit of claim 5, wherein an input clock signal is input from an input of the first coarse tuning delay circuit and a delayed output clock signal is output from an output of the second fine tuning delay circuit.
7. The novel all-digital delay locked loop circuit of claim 5, wherein the first coarse delay circuit comprises an LDU circuit comprising a plurality of first coarse delay units, each first coarse delay unit comprising two serially connected not gates.
8. The novel all-digital delay locked loop circuit of claim 5, wherein the second coarse delay circuit comprises a CCDU circuit comprising a controllable delay line circuit and an SR flip-flop coupled to the controllable delay line circuit.
9. The novel all-digital delay locked loop circuit of claim 5, wherein the first fine delay circuit comprises a CDU circuit comprising a plurality of first fine delay units, each first fine delay unit comprising a delay element, an and gate, and a data selector, an output of the delay element being connected to one input of the and gate, an output of the and gate being connected to one input of the data selector.
10. The novel all-digital delay locked loop circuit of claim 5, wherein the second fine delay circuit comprises an FDU circuit comprising a plurality of second fine delay units, each second fine delay unit comprising a plurality of nand gates in parallel.
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| CN202310318865.1A CN116346126A (en) | 2023-03-28 | 2023-03-28 | Novel all-digital delay phase-locked loop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118819592A (en) * | 2024-09-13 | 2024-10-22 | 合肥康芯威存储技术有限公司 | A firmware upgrade method for storage device and storage device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118819592A (en) * | 2024-09-13 | 2024-10-22 | 合肥康芯威存储技术有限公司 | A firmware upgrade method for storage device and storage device |
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