CN116346045B - Ultra-wideband low-noise amplifier based on noise cancellation and body bias technology - Google Patents
Ultra-wideband low-noise amplifier based on noise cancellation and body bias technology Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H03F2200/36—Indexing scheme relating to amplifiers the amplifier comprising means for increasing the bandwidth
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- H—ELECTRICITY
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- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The application discloses an ultra-wideband low-noise amplifier based on noise cancellation and body bias technology, which comprises an STD circuit and an NC circuit, wherein the STD circuit comprises a single-ended signal input end, a differential signal output end and a plurality of MOS amplifying tubes connected with each other, the MOS amplifying tubes are used for amplifying single-ended signals and outputting differential signals at two differential signal output ends, the NC circuit comprises two differential signal input ends, an output end and a plurality of MOS balance tubes, the MOS balance tubes are used for canceling common mode noise contained in the differential signals, the STD circuit and the NC circuit are combined in a current multiplexing mode, the symmetrical MOS amplifying tubes are connected in parallel, and the symmetrical MOS balance tubes are connected in parallel.
Description
Technical Field
The application relates to the technical field of radio frequency integrated circuits, in particular to an ultra-wideband low-noise amplifier based on noise cancellation and body bias technologies.
Background
Over the past few years, there has been an increasing demand for high-speed wireless communication systems. UWB (Ultra Wide Band) is popular as a new technology for low power consumption and high data rate transmission. The LNA (Low Noise Amplifier ) is the first important module in the UWB receiver architecture that amplifies the weak RF (Radio Frequency) signal of the antenna with minimal noise contribution while suppressing noise for subsequent circuit modules.
CMOS technology is considered a suitable solution, exhibiting a very high cost performance in terms of inductance quality factor and cut-off frequency, at its low manufacturing cost, and at a very high degree of integration. Among the various LNA structures based on CMOS technology, basic structures such as common source and common gate structures have been proposed. For wideband input impedance matching, for example, a resistive feedback amplifier achieves a wider band input impedance matching, but this structure reduces gain at high frequencies. Linearity is one of the most important parameters in high frequency systems, and nonlinear effects include harmonic distortion, gain reduction, cross modulation and intermodulation. The minimum and maximum input levels in the dynamic range depend on noise and nonlinearity, respectively. Therefore, the application provides a UWB front-end broadband LNA based on noise cancellation and high linearity.
Disclosure of Invention
The embodiment of the application provides an ultra-wideband low-noise amplifier based on noise cancellation and body bias technology, which is realized by combining low-noise low-power consumption high linearity together through designing an STD circuit and an NC circuit.
The embodiment of the application provides an ultra-wideband low-noise amplifier based on noise cancellation and body bias technology, which comprises the following components:
The STD circuit comprises a single-ended signal input end, two differential signal output ends and a plurality of MOS amplifying tubes connected with each other, wherein the MOS amplifying tubes are used for amplifying the single-ended signals input by the single-ended signal input end and outputting differential signals extracted from the single-ended signals at the two differential signal output ends;
The NC circuit comprises two differential signal input ends, an output end and a plurality of MOS balance tubes, wherein the MOS balance tubes are used for counteracting common mode noise included in differential signals input by the differential signal input ends, the STD circuit and the NC circuit are combined in a current multiplexing mode, the symmetrical MOS amplifier tubes are connected in parallel, and the symmetrical MOS balance tubes are connected in parallel.
The ultra-wideband low-noise amplifier based on the noise cancellation and body bias technology comprises an STD circuit and an NC circuit, wherein the STD circuit comprises a single-ended signal input end, two differential signal output ends and a plurality of MOS balance tubes connected with each other, the MOS balance tubes are used for amplifying the single-ended signal input by the single-ended signal input end and outputting differential signals extracted from the single-ended signal at the two differential signal output ends, the NC circuit comprises two differential signal input ends, two output ends and a plurality of MOS balance tubes, the MOS balance tubes are used for canceling common mode noise included in the differential signals input by the differential signal input ends, the STD circuit and the NC circuit are combined in a current multiplexing mode, the symmetrical MOS balance tubes are connected in parallel, noise cancellation is achieved by converting the single-ended signal into common mode signals through the arrangement of the STD circuit and the NC circuit, and the power consumption of the power supply can be further reduced through the voltage bias circuit, and the purpose of reducing the power consumption is achieved.
Drawings
FIG. 1 is a schematic diagram of an ultra wideband low noise amplifier based on noise cancellation and body bias techniques according to one embodiment of the present application;
FIG. 2 is a schematic diagram of noise cancellation of M1 of an STD circuit in an ultra-wideband low noise amplifier based on noise cancellation and body bias techniques according to one embodiment of the present application;
fig. 3 is a schematic structural diagram of an STD circuit in an ultra wideband low noise amplifier based on noise cancellation and body bias technology according to an embodiment of the present application;
FIG. 4 is a schematic diagram of noise cancellation of an NC circuit in an ultra-wideband low noise amplifier based on noise cancellation and body bias techniques according to another embodiment of the present application;
Fig. 5 is a schematic diagram of noise cancellation of M2 of an STD circuit in an ultra wideband low noise amplifier based on noise cancellation and body bias techniques according to another embodiment of the present application;
FIG. 6 is a schematic diagram of an ultra wideband low noise amplifier based on noise cancellation and body bias techniques according to another embodiment of the present application;
FIG. 7 is a schematic diagram of an ultra wideband low noise amplifier based on noise cancellation and body bias techniques according to yet another embodiment of the present application;
FIG. 8 is a schematic diagram of an ultra wideband low noise amplifier based on noise cancellation and body bias techniques according to yet another embodiment of the present application;
FIG. 9 is a schematic diagram of the structure of a PMOS amplifying tube and an NMOS amplifying tube in an ultra wideband low noise amplifier based on noise cancellation and body bias technology according to still another embodiment of the present application;
Fig. 10 is a schematic structural diagram of a dual NMOS amplifier in an ultra wideband low noise amplifier based on noise cancellation and body bias techniques according to yet another embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It should be noted that the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Over the past few years, there has been an increasing demand for high-speed wireless communication systems. UWB (Ultra Wide Band) is popular as a new technology for low power consumption and high data rate transmission. The system aims at providing seamless connection between consumer electronic devices for transmitting video, audio and other high-bandwidth data, and mainly aims at real-time positioning systems, mobile applications (including smart phones, wearable devices, consumer tags and the like), automobiles, smart homes and the like. In the current large background of the world, indoor positioning and local area network communication are being developed vigorously, and UWB research is experiencing a new wave. UWB-related research has gradually become a research hotspot in academia and industry in recent years.
The LNA (Low Noise Amplifier ) is the first important module in the UWB receiver architecture that amplifies the weak Radio Frequency RF (Radio Frequency) signal of the antenna with minimal noise contribution, while suppressing noise for subsequent circuit modules. LNA is used as the front end of UWB and gradually moves towards low power consumption, low noise and high linearity. CMOS technology is considered a suitable solution, exhibiting a very high cost performance in terms of inductance quality factor (Q) and cut-off frequency, at its low manufacturing cost, and at a very high degree of integration. With the advent of the 5G age in recent years, products have been developed toward miniaturization and low power consumption. Meanwhile, the channels are more and more crowded, and the requirements on linearity are also higher and higher. Researchers have continually weighed the trade-offs between gain, stability, noise figure, linearity, input and output impedance matching, and power consumption to design high performance LNAs. Among the various LNA structures based on CMOS technology, basic structures such as common source and common gate structures have been proposed. For wideband input impedance matching, for example, a resistive feedback amplifier achieves a wider band input impedance matching, but this structure reduces gain at high frequencies. To reduce power consumption, a current multiplexing architecture is one of the appropriate methods to build the RF front-end and reduce power consumption. Linearity is one of the most important parameters in high frequency systems, and nonlinear effects include harmonic distortion, gain reduction, cross modulation and intermodulation. The minimum and maximum input levels in the dynamic range depend on noise and nonlinearity, respectively. The index of linearity is therefore becoming more and more important in research in recent years.
Therefore, the application provides an ultra-wideband low-noise amplifier based on noise cancellation and body bias technology, and it can be understood that the body bias technology refers to the adjustment of the difference of substrate voltages by utilizing the body effect principle. The application integrates the trend of the current communication development, combines the low noise, low power consumption and high linearity together, and realizes a wideband LNA with an STD (Single-ENDED SIGNAL To DIFFERENTIAL SIGNAL) circuit and an NC (Noise Canceling, noise cancellation) circuit.
The application provides an ultra-wideband low-noise amplifier based on noise cancellation and body bias technology, which comprises an STD circuit and an NC circuit, wherein the STD circuit comprises a single-ended signal input end, two differential signal output ends and a plurality of MOS (metal oxide semiconductor) amplifying tubes connected with each other, the MOS amplifying tubes are used for amplifying single-ended signals input by the single-ended signal input end and outputting differential signals extracted from the single-ended signals at the two differential signal output ends, the NC circuit comprises two differential signal input ends, an output end and a plurality of MOS balance tubes, the MOS balance tubes are used for canceling common mode noise contained in the differential signals input by the differential signal input ends, the STD circuit and the NC circuit are combined in a current multiplexing mode, and the symmetrical MOS balance tubes are connected in parallel.
Embodiments of the present application will be further described below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a schematic structural diagram of an ultra-wideband low-noise amplifier based on noise cancellation and body bias technology according to an embodiment of the present application, where the ultra-wideband low-noise amplifier based on noise cancellation and body bias technology includes an STD circuit and an NC circuit, the STD circuit includes a single-ended signal input end, two differential signal output ends, and a plurality of MOS amplifiers connected to each other, the MOS amplifiers are configured to amplify a single-ended signal input by the single-ended signal input end and output differential signals extracted from the single-ended signal at the two differential signal output ends, the NC circuit includes two differential signal input ends, an output end, and a plurality of MOS balance tubes configured to cancel common mode noise included in the differential signals input by the differential signal input ends, where the STD circuit and the NC circuit are combined in a current multiplexing mode, the symmetrical MOS amplifiers are connected in parallel, and the symmetrical MOS balance tubes are connected in parallel.
As is well known, the main noise contribution of the LNA is from the channel thermal noise of the MOS amplifier, and may generally account for twenty to thirty percent of the total noise contribution, so the noise optimization of the present application is mainly developed for the channel thermal noise of the MOS amplifier. UWB operates at frequencies up to several GHz and therefore flicker noise is negligible and is not considered within the scope of the present application. Since the present application is directed to STD signals, noise from two MOS amplifiers needs to be cancelled to achieve the theoretically lowest noise figure. The current STD scheme is mainly provided with two schemes of CS-CS and CS-CG, and because CS-CS reverse amplification is obtained through the output of a common source of a previous stage, natural mismatch exists in the output of the CS-CS reverse amplification, the application selects to use CS-CG to generate a pair of differential signals and simultaneously carries out noise reduction treatment on two input tubes.
In an alternative embodiment, the design for the STD circuit in the present application is CS-CG, as shown in FIG. 2. The channel thermal noise of the common gate is inverted at the drain-source stage. Therefore, for the STD circuit, there is a natural advantage that channel thermal noise of the common gate can be reversely amplified by the gate of the drain-to-common source stage, and a pair of common mode noises in the same direction are output at the drain of the common source, so that the channel thermal noise of the MOS amplifier M1 is effectively offset at the differential end.
It can be understood that the STD circuit refers to a circuit for converting an input single-ended radio frequency signal into a differential signal, and includes a single-ended signal input end V in, two MOS amplifiers M1 and M2, an auxiliary tube M3, and two differential signal output ends, as shown in fig. 3, the STD circuit receives an ultra-wideband radio frequency signal, so that not only an ideal differential signal is obtained, but also two pairs of common mode noise are obtained at the output ends of the MOS amplifiers.
Because the differential signals output by the STD circuit still have quite large mismatch, and the noise at the output end of the MOS amplifier is greatly differentiated, the size of single-ended noise needs to be further reduced, the application provides the NC circuit which not only can be used for eliminating the unbalance of the output end, but also can further reduce the noise, and achieves the effect of achieving two purposes, and the structure of the NC circuit is shown in figure 4. The NC circuit comprises two differential signal input ends, wherein the differential signal output ends correspond to the differential signal input ends, and the NC circuit is similar to a classical five-tube OTA, but lacks a tail current source. The NC circuit comprises two differential signal input ends, differential signals are effectively amplified, but noise of the MOS amplifying tube enters the NC circuit in a common mode, so that common mode noise is effectively counteracted at the output end, and the noise is further reduced.
Because the MOS balance tube is arranged in the NC circuit, the NC circuit can offset common mode noise included in the differential signal, thereby achieving the effect of reducing noise. Referring to fig. 4, M3 to M4 and M1 to M2 may have fixed ratio values, so that the noise at the input end can be effectively cancelled, and in an ideal state, if the noise signals at the input end have equal amplitudes, the noise signals at the input end can be completely cancelled theoretically.
In another embodiment of the application, the STD circuit and the NC circuit are combined in a current multiplexing mode, so that the power consumption of the low-noise amplifier is reduced, symmetrical MOS (metal oxide semiconductor) amplifying tubes are connected in parallel, and symmetrical MOS balance tubes are connected in parallel, namely, the voltage of the substrate is biased by leakage current. In an alternative embodiment, referring to fig. 5, by connecting the substrates at the symmetrical ends of the NC circuit, on the one hand, the device-level difference is eliminated, and on the other hand, the unbalanced potential from the STD circuit is also completely eliminated at the point X, so that the NC circuit is in a completely symmetrical state in theory, that is, the body effect caused by the substrate voltage difference is reduced, thereby effectively reducing the signal output imbalance in the circuit.
In an alternative embodiment, the bias circuit is omitted in the present application to reduce unnecessary power consumption waste, and only the leakage current is used to bias the voltage of the substrate. As shown in fig. 6, the application connects symmetrical MOS transistors in parallel due to the differential circuit, so as to reduce the body effect caused by the substrate voltage difference. In the STD circuit, the R2 receives different voltages due to the asymmetry of both sides, and the static operating point of the output terminal is deviated due to the transmission to the NC circuit. However, the application successfully balances the difference of NC circuits and designs a symmetrical substrate self-bias circuit. As shown in fig. 7, in fig. 7 (a), the symmetrical MOS transistors are not connected in parallel, and in fig. 7 (b), the symmetrical MOS transistors are connected in parallel, and as shown in fig. 7 (b), the technical scheme of the present application eliminates the difference of device layers by connecting the substrates at the symmetrical ends of the NC circuit, and the unbalanced potential from the STD circuit at the other side is completely eliminated at the point X, so that the NC circuit is in a theoretically completely symmetrical state. Effectively avoids the problem of signal output imbalance in the circuit.
In yet another embodiment of the present application, the single-ended signal may be an input radio frequency signal, the MOS amplifier refers to a MOS transistor mainly used for amplifying the signal, and the MOS amplifier may be made of any type of MOS transistor in the related art, which is not specifically limited herein. The MOS balance tube is mainly used for balancing signals output by an output end in the NC circuit, and can be made of any type of MOS tube in the related technology, and is not particularly limited herein.
In an embodiment, referring to fig. 8, an ultra wideband low noise amplifier based on noise cancellation and body bias technology is further described, where an isolation inductor is disposed between a differential signal output terminal of the STD circuit and a differential signal input terminal of the NC circuit, so that the NC circuit obtains a relatively stable source voltage.
It is understood that the isolation inductor refers to any type of inductor in the related art, and is not specifically limited herein, and an isolation inductor is disposed between the differential signal output end of the STD circuit and the differential signal input end of the NC circuit, so that the STD circuit and the NC circuit are isolated from each other, and further, the NC circuit obtains a relatively stable source voltage.
In another embodiment of the application, shown in fig. 8, the STD circuit and NC circuit are ac isolated by large inductances into the L1 and L2 lines, so that M4 and M5 of the NC circuit achieve a relatively smooth source voltage, at which point the application can also be subsequently analyzed with approximate ac.
In an embodiment, referring to fig. 8, an ultra wideband low noise amplifier based on noise cancellation and body bias technology is further described, where a coupling capacitor is provided between a differential signal output terminal of the STD circuit and a differential signal input terminal of the NC circuit to couple a differential signal to the NC circuit.
It will be understood that, referring to fig. 8, the coupling capacitor refers to a coupling capacitor made of any material in the related art, and is not limited herein, and since the differential signal output end of the STD circuit is connected to the differential signal input end of the NC circuit, the coupling capacitor is disposed between the differential signal output end and the differential signal output end, that is, the coupling capacitors C 1 and C 2 are disposed, so that the differential signal is coupled to the NC circuit, and the differential signal output from the STD circuit of the previous stage can be coupled to the NC circuit of the next stage because the differential signal is an ac signal with a very high frequency, thereby reducing the interference of the dc signal in the STD circuit.
In an embodiment, referring to fig. 6, a further explanation is made on an ultra wideband low noise amplifier based on noise cancellation and body bias technology, where the MOS amplifier includes a first MOS amplifier, a second MOS amplifier, and a third MOS auxiliary transistor, and the STD circuit further includes an auxiliary transistor parasitic capacitor, where the parasitic capacitor is used to guide noise from the drain of the second MOS amplifier back to the gate of the second MOS amplifier.
It can be understood that the MOS amplifier includes a first MOS amplifier, a second MOS amplifier, and a third MOS auxiliary transistor, and the parasitic capacitance refers to any parasitic capacitance having a capacitive effect in the related art, where the parasitic capacitance generally refers to a capacitive characteristic of an inductor, a resistor, a chip pin, or the like, which is shown under a high frequency condition.
For channel thermal noise cancellation of M2, the noise source of the common source M2 may be led back to the gate by feedback, and then amplified and cancelled by other MOS amplifiers, for example, M3, where M3 serves to assist in noise cancellation. However, this method has a great limitation that it is easy to reduce the M2 channel while increasing the noise of the overall circuit. In an alternative embodiment, referring to fig. 5, the parasitic capacitance Cgd of the large-size auxiliary transistor is used to guide the noise at the Y point of the drain electrode M2 back to the X point of the gate electrode M2, on the one hand, the common source electrode is amplified reversely to cancel the noise, on the other hand, the noise is sent to the common gate electrode to amplify the noise, at this time, two common mode noises in the same direction are generated at the two output ends, and the characteristics of the differential circuit, namely the STD circuit, are used to effectively cancel the noise.
It is noted that, referring to fig. 5, the capacitance Cgs of M2 will also couple drain noise to the gate of M2, but Cgs will also couple noise to the gate of M2 at the source, and Cgd reaches 38f although Cgs is much larger than Cgd, so both have the ability to cancel the reverse noise of the drain-source of M2 at the gate. The resulting STD circuit is shown in fig. 6 for device reduction.
In an embodiment, referring to fig. 9, an ultra wideband low noise amplifier based on noise cancellation and body bias technology is further described, where the MOS amplifier includes a PMOS transistor and an NMOS transistor, and the substrate of the PMOS transistor and the substrate of the NMOS transistor are connected to each other.
In the current circuit design, low voltage and low power consumption are always a major trend in the development of the circuit design. In particular, UWB-related chips are currently being used in mobile phones and mobile positioning devices for wireless communications, and the requirement for power consumption may be of great importance. On the one hand, the power consumption can be reduced by optimizing a circuit, and the current magnitude can be reduced as much as possible. And meanwhile, the power consumption can be reduced by reducing the power supply voltage under the same performance premise.
It can be understood that the PMOS transistor refers to any PMOS transistor in the related art, and the NMOS transistor refers to any NMOS transistor in the related art. In an alternative embodiment, referring to fig. 9, the most simple inverter type amplifying circuit and the common source amplifier using a current source as a load are used, and for the inverter type amplifier, the substrate of the PMOS transistor and the substrate of the NMOS transistor are connected to each other, that is, a PN junction at the upper end of the PMOS transistor can be formed, and the NMOS transistor forms a diode by adopting the same principle, so as to form a simple loop. In order to prevent the current of the loop from being excessively large, a resistor needs to be connected after the NMOS tube, so long as the resistor achieves the effect of reducing the current of the loop.
In an embodiment, referring to fig. 10, an ultra wideband low noise amplifier based on noise cancellation and body bias technology is further described, where the MOS amplifier includes two NMOS transistors, and the two NMOS transistors are connected to a power supply terminal through a target resistor.
It is to be understood that the power supply terminal refers to any VDD power supply terminal in the related art, and is not particularly limited herein, and the target resistance refers to a resistance set by any device in the related art as long as the effect of lowering the substrate voltage can be achieved. Since the NPN-based MOS transistor configuration as shown in fig. 10 cannot generate a loop from VDD through NP, it is necessary to directly connect VDD to the target resistor to the MOS again, which corresponds to changing only the substrate voltage of the lower NMOS without changing the substrate voltage of the upper NMOS. In the embodiment of the application, as the two NMOS tubes are connected with the power supply end through the target resistor, that is, the substrate voltage can be adjusted by adjusting the size of the target resistor, thereby realizing the purpose of low voltage and low power consumption.
In one embodiment, an ultra wideband low noise amplifier based on noise cancellation and body bias techniques is further described with reference to fig. 6, where the STD circuit includes a bias auxiliary transistor for eliminating third order nonlinearities around the linearization window.
Improving linearization is a great trend in the current 5G-age communication development. At present, the bandwidth of information transmission is larger and larger, the situation that a plurality of channels are transmitted simultaneously can occur, and the linearization problem needs to be solved. Complementary CMOS can use NMOS and PMOS transistors to form opposite GM3 offset with each other at the same bias voltage to select a better bias voltage, MGTR (Multigated Transistor, multiple gate transistor) technology can eliminate third order nonlinearities around the linearization window by carefully designing the size and bias of the auxiliary transistors. In order to minimize power consumption, the bias auxiliary transistor can be designed in the weak inversion layer, but the main disadvantage is that the combined second order distortion coefficients can be accumulated instead of being ideally attenuated. The consequent second order distortion coefficients interact with the parasitic effects distributed in the circuit, which will inevitably constitute a dip of IP3 at high frequencies. The non-linear base current versus gate voltage IDS-VGS relationship of a MOS transistor can be modeled by a taylor series expansion around a specific VG bias point as follows:
Where v gs is the small signal gate-source voltage, n is any natural number, Representing the transconductance g m relative to the order n th. The most direct and effective way to reduce nonlinearity is to filter out all higher orders of g' m and above. It is well known that coefficients as in equation (1) play an important role in determining IMD (Intermodulation Distortion ) of an RF amplifier. In MGTR, these coefficients can be minimized by linearly superimposing in parallel CS FET transistors of appropriate bias and size, i.e., new field effect transistors with cold sources.
According to the nonlinear source of the MOS tube, the application mainly focuses on selecting a better static working point to obtain a region with a good static working point so as to achieve relatively better linearity performance. The source of the nonlinearity is mainly from the MOS amplifier in the STD circuit, so GM3 of the output node needs to be set near a zero value to obtain the theoretically optimal iip (Input REFERRED THIRD order intercept point, input reference third-order intermodulation point) index, as shown in fig. 6.
It should be noted that, referring to fig. 6, in the STD circuit, the common source needs to consider the co-action of the two MOS transistors M2 and M3, that is, the sum of GM3 of M2 and M3 is required. In the related art, parallel multi-gate transistors are generally used in single-frequency amplifying circuits, but in order to match a wider bandwidth in an ultra-wideband amplifying circuit, the auxiliary design is not so flexible, and certain linearity is sacrificed.
In one embodiment, an ultra wideband low noise amplifier based on noise cancellation and body bias techniques is further described, and isolation inductors are provided between parallel MOS amplifiers to reduce parasitic capacitance at the single-ended signal input.
In the front-end LNA field of UWB, multi-gate transistor technology has not been applied to wideband LNAs. Mainly because the parasitic power at the input end of the multi-gate transistor is larger, the high-frequency gain drops rapidly, and large-range matching is difficult to achieve at the frequency of-3 dB. In order to better integrate the multi-gate transistor technology into the multi-gate transistor, the application properly utilizes the isolation inductor to resonate with the multi-gate transistor technology so as to reduce the parasitic capacitance of the input end and realize larger range gain and input matching.
It can be understood that the isolation inductor refers to any type of inductor in the related art, the low noise amplifier receives the ultra-wideband transmitted radio frequency signal as the input of the STD circuit, and the isolation inductor is arranged between the parallel MOS amplifiers, so that the parasitic capacitance of the single-ended signal input end is reduced, and further, the power consumption of the low noise amplifier is reduced.
Claims (6)
1. An ultra-wideband low noise amplifier based on noise cancellation and body bias techniques, comprising:
The STD circuit comprises a single-ended signal input end, two differential signal output ends and a plurality of MOS amplifying tubes connected with each other, wherein the MOS amplifying tubes are used for amplifying the single-ended signals input by the single-ended signal input end and outputting common mode noise signals extracted from the single-ended signals at the two differential signal output ends;
The NC circuit comprises two differential signal input ends, an output end and a plurality of MOS balance tubes, wherein the MOS balance tubes are used for counteracting common mode noise included in differential signals input by the differential signal input ends, and the STD circuit and the NC circuit are combined in a current multiplexing mode;
The MOS amplifier comprises a first MOS amplifier, a second MOS amplifier and a third MOS auxiliary tube, wherein the third MOS auxiliary tube is used for assisting in counteracting noise;
the grid electrode of the first MOS amplifying tube is grounded through a first capacitor, a pull-up voltage is connected between the grid electrode of the first MOS amplifying tube and the first capacitor, the drain electrode of the first MOS amplifying tube is connected with one of the differential signal output ends, and the source electrode of the first MOS amplifying tube is grounded through an inductor;
the single-ended signal input end is connected between the first MOS amplifying tube and the inductor;
The grid electrode of the second MOS amplifying tube is connected between the first MOS amplifying tube and the inductor through a second capacitor and is connected with the single-ended signal input end, the drain electrode of the second MOS amplifying tube is connected with the other differential signal output end, and the source electrode of the second MOS amplifying tube is grounded;
The drain electrode of the third MOS auxiliary tube is connected between the drain electrode of the second MOS amplifying tube and the other differential signal output end, the source electrode of the third MOS auxiliary tube is grounded, the grid electrode of the third MOS auxiliary tube is connected with one end of a third capacitor, the other end of the third capacitor is connected with the second capacitor, and the other end of the third capacitor is connected between the first MOS amplifying tube and the inductor and is connected with the single-ended signal input end;
A coupling capacitor is arranged between the differential signal output end of the STD circuit and the differential signal input end of the NC circuit so as to couple the differential signal to the NC circuit;
One of the differential signal output ends of the STD circuit is connected with one of the differential signal input ends of the NC circuit through a first isolation inductor; the other differential signal output end of the STD circuit is connected with the other differential signal input end of the NC circuit through a second isolation inductor;
The MOS balance tubes comprise a fourth MOS balance tube, a fifth MOS balance tube, a sixth MOS balance tube, a seventh MOS balance tube, an eighth MOS balance tube, a ninth MOS balance tube, a tenth MOS balance tube and an eleventh MOS balance tube;
The source electrode of the fourth MOS balance tube is connected with the source electrode of the eighth MOS balance tube, the source electrode of the ninth MOS balance tube is connected to a connecting wire and is connected with one differential signal input end of the NC circuit, the connecting wire is a connecting wire for connecting the source electrode of the fourth MOS balance tube and the source electrode of the eighth MOS balance tube, and the source electrode of the fifth MOS balance tube is connected to the connecting wire and is connected with the other differential signal input end of the NC circuit;
The grid electrode of the fourth MOS balance tube is connected between the second isolation inductor and the other differential signal output end of the STD circuit through the first coupling capacitor, the grid electrode of the fourth MOS balance tube is also connected with the grid electrode of the ninth MOS balance tube, and the drain electrode of the fourth MOS balance tube is connected with the drain electrode of the sixth MOS balance tube;
the grid electrode of the fifth MOS balance tube is connected between the first isolation inductor and one of the differential signal output ends of the STD circuit through the second coupling capacitor, the grid electrode of the fifth MOS balance tube is also connected with the grid electrode of the eighth MOS balance tube, and the drain electrode of the fifth MOS balance tube is respectively connected with the drain electrode of the seventh MOS balance tube and the output end of the NC circuit;
The source electrode of the sixth MOS balance tube and the source electrode of the seventh MOS balance tube are both connected with power supply voltage, the grid electrode of the sixth MOS balance tube is connected with the grid electrode of the seventh MOS balance tube, and the grid electrode of the sixth MOS balance tube and the grid electrode of the seventh MOS balance tube are respectively connected between the drain electrode of the sixth MOS balance tube and the drain electrode of the fourth MOS balance tube;
The grid electrode of the eighth MOS balance tube is connected between the first isolation inductor and one of the differential signal output ends of the STD circuit through the second coupling capacitor, and the drain electrode of the eighth MOS balance tube is connected with the drain electrode of the tenth MOS balance tube;
the grid electrode of the ninth MOS balance tube is connected between the second isolation inductor and the other differential signal output end of the STD circuit through the first coupling capacitor, and the drain electrode of the ninth MOS balance tube is connected with the drain electrode of the eleventh MOS balance tube and the output end of the NC circuit respectively;
The source electrode of the tenth MOS balance tube and the source electrode of the eleventh MOS balance tube are both connected with the power supply voltage, the grid electrode of the tenth MOS balance tube is connected with the grid electrode of the eleventh MOS balance tube, the grid electrode of the tenth MOS balance tube and the grid electrode of the eleventh MOS balance tube are respectively connected between the drain electrode of the tenth MOS balance tube and the drain electrode of the eighth MOS balance tube, and the drain electrode of the eleventh MOS balance tube is connected with the output end of the NC circuit.
2. The ultra wideband low noise amplifier based on noise cancellation and body bias technique of claim 1, wherein the STD circuit further comprises a parasitic capacitance for introducing noise from the drain of the second MOS amplifier back to the gate of the second MOS amplifier.
3. The ultra-wideband low noise amplifier based on noise cancellation and body bias technology according to claim 1, wherein the MOS amplifier comprises a PMOS transistor and an NMOS transistor, the substrates of the PMOS transistor are connected to each other through a target resistor and the substrates of the NMOS transistor, and the target resistor is used for reducing the current of the loop.
4. The ultra-wideband low noise amplifier based on noise cancellation and body bias technology of claim 1, wherein the MOS amplifier comprises two NMOS transistors, and the two NMOS transistors are connected to a power supply terminal through a target resistor.
5. An ultra wideband low noise amplifier based on noise cancellation and body bias techniques as recited in claim 3, wherein said STD circuit further includes a bias auxiliary transistor for eliminating third order nonlinearities around the linearization window.
6. The ultra wideband low noise amplifier based on noise cancellation and body bias technique according to claim 5, wherein said bias auxiliary transistor is a field effect transistor with a cold source.
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| WO2017166109A1 (en) * | 2016-03-30 | 2017-10-05 | 武汉芯泰科技有限公司 | Low noise amplifier |
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| Title |
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| A Low-Power Self-Forward-Body-Bias CMOS LNA for 3–6.5-GHz UWB Receivers;Chen-Ming Li等;IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS;20100228;第100-101页 * |
| High Gain and Wideband CMOS ActiveBalun LNA in 0.18μm Technology for Ka-Band Applications;Raghu S等;IEEE India Council International Conference;20181218;第1页 * |
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