CN116325157A - Nitride-based semiconductor IC chip and manufacturing method thereof - Google Patents

Abstract

A nitride-based semiconductor integrated circuit (IC) chip (100) comprising at least one transistor (Q) and a temperature sensor (T) configured to sense the temperature of the transistor (Q). The transistor (Q) and the temperature sensor (T) are formed on a stacked semiconductor structure having a two-dimensional electron gas (2DEG) layer divided by one or more isolation regions (52) for One or more transistor regions (53) for forming said transistor (Q) and one or more temperature sensor regions (54) for forming said temperature sensor (T). The 2DEG layer has a relatively high temperature coefficient of resistance, which can provide a significant change in resistance with temperature. The resulting temperature sensor (T) has high temperature sensitivity and thus can relax the requirements on the accuracy of the measuring equipment and provide high measurement accuracy.

Description

Nitride-based semiconductor IC chip and manufacturing method thereof

technical field

The present invention generally relates to nitride-based semiconductor integrated circuit (IC) chips. More specifically, the present invention relates to nitride-based semiconductors with temperature sensing capabilities.

Background technique

Wide bandgap materials such as gallium nitride (GaN) have been widely used in high frequency power conversion systems due to low power loss and fast switching transitions. Compared to silicon metal oxide semiconductor field effect transistors (MOSFETs), GaN high electron mobility transistors (HEMTs) have a better figure of merit and more promising performance in high power and high frequency applications. Nitride-based HEMTs utilize a heterojunction interface between two nitride-based materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2DEG) region to satisfy high power /frequency device needs. In addition to HEMTs, examples of devices with heterostructures further include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), and modulation doped FETs (MODFETs).

Conventionally, the temperature of a transistor can be monitored by forming a pair of terminals extending from the gate electrode of the transistor to measure the change in resistance of the gate electrode with temperature. The gate electrode is usually made of titanium nitride (TiN), which has a relatively low temperature coefficient of resistance (TCR) of about 400 ppm/K and a small sheet resistance of about 30Ω/sq. The change in resistance with temperature is not sufficient to achieve the required measurement accuracy. Additionally, leakage current from the gate will affect measurement accuracy. To address these issues, one approach is to deposit a metal, such as platinum (Pt), over a dielectric layer on the gate electrode to form a ring-shaped thermistor around the gate electrode for temperature sensing. However, such methods require additional masking and fabrication steps, which increase cost and production lead time. Another approach is to form a metal (eg, aluminum (Al)) temperature sensor between the sources of the transistors. However, such methods require more complex routing designs.

Contents of the invention

According to an aspect of the present disclosure, there is provided a nitride-based semiconductor integrated circuit (IC) chip including at least one transistor and a temperature sensor configured to sense a temperature of the transistor. The transistor and the temperature sensor are formed on a stacked semiconductor structure comprising: a substrate; a first nitride-based semiconductor layer disposed over the substrate; and a second nitride-based semiconductor layer disposed on the above the first nitride-based semiconductor layer and having a bandgap greater than that of the first nitride-based semiconductor layer, such that two adjacent heterojunctions are formed between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer. a two-dimensional electron gas (2DEG) layer; wherein the 2DEG layer is divided by one or more isolation regions into a transistor region for forming a transistor and one or more temperature sensor regions for forming a temperature sensor; and wherein the temperature sensor comprises : a temperature sensing body comprising one or more bridges for connecting one or more temperature sensor regions to form a temperature sensing body; a first temperature sensing electrode electrically connected to the first temperature sensing body end; and a second temperature sensing electrode electrically connected to the second end of the temperature sensing body; wherein the transistor includes: at least one pair of drain electrode and source electrode disposed on the second nitride-based semiconductor layer above; and at least one gate structure disposed between the at least one pair of drain electrodes and source electrodes; and wherein the first temperature sensing electrode and the second temperature sensing electrode are used to form the drain electrode and the The blanket metal layer of the source electrode is patterned.

The nitride-based 2DEG layer has a relatively high temperature coefficient of resistance of about 9000 ppm/K and a high sheet resistance of greater than 600 Ω/sq, which can provide a significant change in resistance with temperature. The resulting 2DEG temperature sensor has high temperature sensitivity and thus can relax the requirement on the precision of the measurement equipment and provide high measurement accuracy. Furthermore, since the 2DEG temperature sensor elements are interconnected by ohmic metal or the 2DEG layer itself, this will not affect the wiring of the device itself. It is easier to optimize on-resistance and current uniformity than existing solutions.

Description of drawings

Aspects of the present disclosure can be readily understood from the following detailed description by referring to the accompanying drawings. Illustrations may not necessarily be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Due to manufacturing processes and tolerances, differences may exist between the process reproductions in this disclosure and the actual device. Common reference numbers may be used throughout the drawings and detailed description to refer to the same or similar components.

1A and 1B depict the structure of a nitride-based semiconductor chip according to various embodiments of the present invention;

2A and 2B depict the structure of a nitride-based semiconductor chip according to one embodiment of the present invention;

3A and 3B depict the structure of a nitride-based semiconductor chip according to another embodiment of the present invention;

4A and 4B depict the structure of a nitride-based semiconductor chip according to another embodiment of the present invention;

5A and 5B depict the structure of a nitride-based semiconductor chip 500 according to another embodiment of the present invention; and

6A to 6D depict different stages of a method for manufacturing a semiconductor chip according to the invention.

Detailed ways

In the following description, preferred examples of the present disclosure will be set forth as embodiments which should be considered as illustrative rather than restrictive. Certain details may be omitted so as not to obscure the disclosure; however, this disclosure has been written to enable one skilled in the art to practice the teachings herein without undue experimentation.

1A and 1B depict the structure of a nitride-based semiconductor chip 100 according to various embodiments of the present invention. FIG. 1A is a partial layout of a semiconductor chip 100 showing relationships among some elements, and FIG. 1B is a cross-sectional view taken along line AA' in FIG. 1A .

Referring to FIGS. 1A and 1B , a semiconductor chip 100 may include a transistor Q and a temperature sensor T configured to sense the temperature of the transistor Q. Referring to FIGS. The transistor Q and the temperature sensor T may be formed on a stacked semiconductor structure, which at least includes: a substrate 102; a first nitride-based semiconductor layer 104 disposed on the substrate 102; and a first nitride-based semiconductor layer 104 disposed on the first nitrogen The second nitride-based semiconductor layer 106 above the nitride-based semiconductor layer 104.

Exemplary materials for the nitride-based semiconductor layers 104 and 106 are selected such that the bandgap (ie, forbidden band width) of the nitride-based semiconductor layer 106 is greater than the bandgap of the nitride-based semiconductor layer 104, which makes its electron affinity different from each other and form a heterojunction between them. For example, when the nitride-based semiconductor layer 104 is an undoped GaN layer with a band gap of about 3.4 eV, the nitride-based semiconductor layer 106 may be an AlGaN layer with a band gap of about 4.0 eV. Thus, the nitride-based semiconductor layers 104 and 106 can function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, a multi-channel switching device may be used to include one or more GaN-based high electron mobility transistors (HEMTs).

The substrate 102 may be a semiconductor substrate. Exemplary materials for the substrate 102 may include, for example but not limited to, Si, p-doped Si, n-doped Si, SiC, GaN, sapphire, or other suitable semiconductor materials.

Exemplary materials of the nitride-based semiconductor layer 104 may include, for example but not limited to, nitrides or III-V group compounds such as GaN, AlN, InN, _{InxAlyGa (1-xy)} N (where x+y≤1), Al _y Ga _(1-y) N (where y≤1). Exemplary structures of the nitride-based semiconductor layer 104 may include, for example, but not limited to, a multilayer structure, a superlattice structure, and a composition gradient structure.

Exemplary materials of the nitride-based semiconductor layer 106 may include, for example but not limited to, nitrides or III-V compounds such as GaN, AlN, InN, In _{x Aly} Ga _(1-xy) N (where x+y≤1 ), _{AlyGa (1-y)} N (where y≤1).

In some embodiments, the semiconductor chip 100 may further include a buffer layer and a nucleation layer (not shown), or a combination thereof. A buffer layer and a nucleation layer may be disposed between the substrate 102 and the nitride-based semiconductor layer 104 . The buffer layer and the nucleation layer may be configured to reduce the lattice and thermal mismatch between the substrate 102 and the nitride-based semiconductor layer 104 , thereby addressing defects due to the mismatch/difference. The buffer layer may comprise III-V compounds. III-V compounds may include, for example, without limitation, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials of the buffer layer may also include, for example but not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. Exemplary materials for the nucleation layer may include, for example but not limited to, any of AlN or alloys thereof.

Transistor Q and temperature sensor T may be isolated from each other by one or more isolation regions 52 formed in the 2DEG region. Specifically, the 2DEG region may be divided by one or more isolation regions 52 into one or more transistor regions 53 for forming a transistor Q and one or more temperature sensor regions 54 for forming a temperature sensor T.

One or more transistor regions 53 may be arranged in an array having M rows and N columns, where M and N are positive integers.

Transistor Q may further include a plurality of gate structures 110 and a plurality of source/drain (S/D) electrodes 116 disposed on/on/over the stacked semiconductor structure. Each of the S/D electrodes 116 can function as a source electrode or a drain electrode depending on the device design. S/D electrodes 116 may be located at two opposite sides of corresponding gate structures 110, although other configurations may be used, especially when multiple source, drain or gate electrodes are employed in the device. Each of the gate structures 110 may be arranged such that each of the gate structures 110 is located between at least two S/D electrodes 116 .

In the exemplary illustration, for each of the transistors, adjacent S/D electrodes 116 are symmetrical about the gate structure 110 therebetween. In some embodiments, adjacent S/D electrodes 116 may optionally be asymmetrical with respect to the gate structure 110 therebetween. That is, one of the S/D electrodes 116 may be closer to the gate structure 110 than the other of the S/D electrodes 116 .

In some embodiments, each of the gate structures 110 may include an optional gate semiconductor layer and a gate metal layer. A gate semiconductor layer and a gate metal layer are stacked on the nitride-based semiconductor layer 106 . The gate semiconductor layer is between the nitride-based semiconductor layer 106 and the gate metal layer. The gate semiconductor layer and the gate metal layer can form a Schottky barrier. In some embodiments, transistor Q may further include an optional dielectric layer (not shown) between the p-type doped III-V compound semiconductor layer and the gate metal layer.

Specifically, the gate semiconductor layer may be a p-type doped III-V compound semiconductor layer. The p-type doped III-V compound semiconductor layer may create at least one p-n junction with the nitride-based semiconductor layer 106 to deplete the 2DEG region such that at least one section of the 2DEG region corresponding to a location under the corresponding gate structure 110 has Different properties (eg different electron concentration) than the rest of the 2DEG region and thus blocked. Due to such mechanisms, transistor Q may have a normally-off characteristic for forming an enhancement mode device that is normally off when its gate electrode is at substantially zero bias. In other words, when no voltage is applied to the gate electrode or the voltage applied to the gate electrode is less than the threshold voltage (ie, the minimum voltage required to form an inversion layer under the gate structure 110), the gate structure 110 is kept under the gate structure 110. The segment of the 2DEG region is blocked and therefore no current passes through it. Furthermore, by providing a p-type doped III-V compound semiconductor layer, gate leakage current is reduced and an increase in threshold voltage during an off-state is achieved.

In some embodiments, the p-type doped III-V compound semiconductor layer may be omitted such that transistor Q is a depletion device, meaning that transistor Q is normally on at zero gate-source voltage.

Exemplary materials for p-type doped III-V compound semiconductor layers may include, for example but not limited to, p-doped III-V group nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type type InGaN, p-type AlInGaN, or a combination thereof. In some embodiments, the p-doped material is achieved by using p-type impurities such as Be, Mg, Zn, Cd, and Mg.

In some embodiments, the gate electrode may comprise a metal or a metal compound. The gate electrode can be formed as a single layer, or as multiple layers of the same or different compositions. Exemplary materials of metals or metal compounds may include, for example but not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metal compounds. In some embodiments, exemplary materials for the gate electrode may include, for example but not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

In some embodiments, the optional dielectric layer may be formed from a single layer or multiple layers of dielectric material. Exemplary dielectric materials may include, for example, without limitation, _one or more oxide layers, _SiOx layers, _SiNx layers, high-k dielectric materials (e.g., _HfO2 , _Al2O3 , _TiO2 , HfZrO, _Ta2 O ₃ , HfSiO ₄ , ZrO ₂ , ZrSiO ₂ , etc.) or combinations thereof.

In some embodiments, S/D electrodes 116 may comprise, for example but not limited to, metals, alloys, doped semiconductor materials (eg, doped crystalline silicon), compounds such as silicides and nitrides, other conductive materials, or combinations thereof. Exemplary materials for the S/D electrodes 116 may include, for example, without limitation, Ti, AlSi, TiN, or combinations thereof. S/D electrode 116 may be a single layer, or multiple layers of the same or different composition. In some embodiments, the S/D electrode 116 may form an ohmic contact with the nitride-based semiconductor layer 106 . Ohmic contact can be achieved by applying Ti, Al or other suitable materials to the S/D electrodes 116 . In some embodiments, each of S/D electrodes 116 is formed from at least one conformal layer and a conductive fill. A conformal layer may coat the conductive fill. Exemplary materials for the conformal layer are such as, but not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. Exemplary materials for the conductive filler may include, for example but not limited to, AlSi, AlCu, or combinations thereof.

The temperature sensor T may include: a temperature sensing body 550 including a temperature sensor region 54; a first temperature sensing electrode 551 disposed at a first end of the temperature sensing body 550; and a second temperature sensing electrode 552, It is disposed at the second end of the temperature sensing body 550 .

Since the temperature sensing body 550 is formed of a nitride-based 2DEG region, it may have a relatively high temperature coefficient of resistance of about 9000 ppm/K, which may provide a significant change in resistance with temperature.

In case there is more than one temperature sensor region 54 , the temperature sensing body 550 may further include a bridge (not shown) for connecting the temperature sensor regions 54 in series to form the temperature sensing body 550 . In some embodiments, the bridge can be a conductive stripline formed in the 2DEG region such that the temperature sensing body 550 can act as a monolithic 2DEG resistor. In some embodiments, the bridge can be a metal strip line formed above the stacked semiconductor structure, such as formed on the nitride-based semiconductor layer 106 .

The first temperature sensing electrode 551 and the second temperature sensing electrode 552 may be formed over the stacked semiconductor structure. In some embodiments, the first temperature sensing electrode 551 and the second temperature sensing electrode 552 may be formed on the nitride-based semiconductor layer 106 .

In some embodiments, the first temperature sensing electrode 551 and the second temperature sensing electrode 552 may include, for example but not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds (such as silicide and nitrogen compounds), other conductive materials, or combinations thereof. Exemplary materials of the first temperature sensing electrode 551 and the second temperature sensing electrode 552 may include, for example but not limited to, Ti, AlSi, TiN, or a combination thereof. The first temperature sensing electrode 551 and the second temperature sensing electrode 552 may be a single layer, or a plurality of layers having the same or different compositions. In some embodiments, the first temperature sensing electrode 551 and the second temperature sensing electrode 552 may form ohmic contacts with the nitride-based semiconductor layer 106 . Ohmic contact may be achieved by applying Ti, Al, or other suitable materials to the first temperature sensing electrode 551 and the second temperature sensing electrode 552 . In some embodiments, each of the first temperature sensing electrode 551 and the second temperature sensing electrode 552 is formed of at least one conformal layer and a conductive filler. A conformal layer may coat the conductive fill. Exemplary materials for the conformal layer are such as, but not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. Exemplary materials for the conductive filler may include, for example but not limited to, AlSi, AlCu, or combinations thereof.

In some embodiments, the first and second temperature sensing electrodes and the S/D electrode 116 are formed by patterning the same blanket metal layer disposed on the nitride-based semiconductor layer 106 .

2A and 2B depict the structure of a nitride-based semiconductor chip 200 according to one embodiment of the present invention. FIG. 2A is a partial layout of a semiconductor chip 200 showing relationships among some elements, and FIG. 2B is a cross-sectional view taken along line AA' in FIG. 2A. The stacked semiconductor structure of the nitride-based semiconductor chip 200 may be similar to the stacked semiconductor structure of the nitride-based semiconductor chip 100 . For the sake of brevity, the same or similar elements in FIGS. 2A and 2B are given the same reference numerals as in FIGS. 1A and 1B and will not be described in further detail.

Referring to FIGS. 2A and 2B , the nitride-based semiconductor chip 200 may include a transistor Q2 and a temperature sensor T2 configured to sense the temperature of the transistor Q2 . Transistor Q2 may comprise a 2×1 array of transistor regions including transistor region 2531 and transistor region 2532 . The transistor regions 2531 and 2532 may be vertically aligned with each other and horizontally spaced apart.

The temperature sensor T2 may have a temperature sensing body 2550 including a temperature sensor region 254 . The temperature sensor region 254 may be vertically aligned with the transistor regions 2531 , 2532 and positioned between the transistor region 2531 and the transistor region 2532 .

The temperature sensor T2 may further include a first temperature sensing electrode 2551 disposed at a first end of the temperature sensing body 2550 and a second temperature sensing electrode 2552 disposed at a second end of the temperature sensing body 2550 . Specifically, the first temperature sensing electrode 2551 is electrically connected to a first end of the temperature sensor area 254 , and the second temperature sensing electrode 2552 is electrically connected to a second end of the temperature sensor area 254 .

3A and 3B depict the structure of a nitride-based semiconductor chip 300 according to another embodiment of the present invention. FIG. 3A is a partial layout of a semiconductor chip 300 showing relationships among some elements, and FIG. 3B is a cross-sectional view taken along line AA' in FIG. 3A. The stacked semiconductor structure of the nitride-based semiconductor chip 300 is similar to that of the nitride-based semiconductor chip 100 . For the sake of brevity, the same or similar elements in FIGS. 3A and 3B are given the same reference numerals as in FIGS. 1A and 1B and will not be described in further detail.

Referring to FIGS. 3A and 3B , the nitride-based semiconductor chip 300 may include a transistor Q3 and a temperature sensor T3 configured to sense the temperature of the transistor Q3 . Transistor Q3 may comprise a 1×2 array of transistor regions 3531 and 3532 . The transistor regions 3531 and 3532 may be horizontally aligned and vertically spaced apart from each other.

The temperature sensor T3 may have a temperature sensing body 3550 including a temperature sensor area 3541 , a temperature sensor area 3542 , a temperature sensor area 3543 and a temperature sensor area 3544 . The temperature sensor areas 3541, 3542 may be horizontally aligned and vertically spaced apart from each other. The temperature sensor areas 3543, 3544 may be horizontally aligned and vertically spaced apart from each other. The temperature sensor regions 3541 , 3544 can both be vertically aligned with the transistor region 3532 and positioned at two opposite sides of the transistor region 3532 , respectively. The temperature sensor regions 3542, 3543 can both be vertically aligned with the transistor region 3531 and positioned at two opposite sides of the transistor region 3531, respectively.

The temperature sensing body 3550 may further include a vertical bridge 3561 electrically connecting the second end of the temperature sensor area 3541 and the first end of the temperature sensor area 3542 . The temperature sensing body 3550 may further include a horizontal bridge 3562 electrically connecting the second end of the temperature sensor area 3542 and the first end of the temperature sensor area 3543 . The temperature sensing body 3550 may further include a vertical bridge 3563 electrically connecting the second end of the temperature sensor area 3543 and the first end of the temperature sensor area 3544 .

The temperature sensor T3 may further include a first temperature sensing electrode 3551 disposed at a first end of the temperature sensing body 3550 and a second temperature sensing electrode 3552 disposed at a second end of the temperature sensing body 3550 . Specifically, the first temperature sensing electrode 3551 is electrically connected to a first end of the temperature sensor region 3541 , and the second temperature sensing electrode 3552 is electrically connected to a second end of the temperature sensor region 3544 .

4A and 4B depict the structure of a nitride-based semiconductor chip 400 according to another embodiment of the present invention. FIG. 4A is a partial layout of a semiconductor chip 400 showing relationships among some elements, and FIG. 4B is a cross-sectional view taken along line AA' in FIG. 4A. The stacked semiconductor structure of the nitride-based semiconductor chip 400 is similar to that of the nitride-based semiconductor chip 100 . For the sake of brevity, the same or similar elements in FIGS. 4A and 4B are given the same reference numerals as in FIGS. 1A and 1B and will not be described in further detail.

4A and 4B, the semiconductor chip 400 may include a transistor Q4 and a temperature sensor T4. Transistor Q4 may comprise a 1×2 array of transistor regions 4531 and 4532 . The transistor regions 4531 and 4532 may be horizontally aligned and vertically spaced apart from each other.

The temperature sensor T4 may have a temperature sensing body 4550 including a temperature sensor region 4541 , a temperature sensor region 4542 , a temperature sensor region 4543 and a temperature sensor region 4544 . The temperature sensor regions 4541 , 4542 can both be vertically aligned with the transistor region 4531 and positioned at two opposite sides of the transistor region 4531 , respectively. The temperature sensor regions 4543, 4544 may both be vertically aligned with the transistor region 4532 and positioned at two opposite sides of the transistor region 4532, respectively. The temperature sensor areas 4541, 4543 may be horizontally aligned and vertically spaced apart from each other. The temperature sensor areas 4542, 4544 may be horizontally aligned and vertically spaced apart from each other.

The temperature sensing body 4550 may further include a horizontal bridge 4561 electrically connecting the second end of the temperature sensor area 4541 and the first end of the temperature sensor area 4542 . The temperature sensing body 4550 may further include a horizontal bridge 4562 electrically connecting the second end of the temperature sensor area 4542 and the first end of the temperature sensor area 4543 . The temperature sensing body 4550 may further include a horizontal bridge 4563 electrically connecting the second end of the temperature sensor area 4543 and the first end of the temperature sensor area 4544 .

The temperature sensor T4 may further include a first temperature sensing electrode 4551 disposed at a first end of the temperature sensing body 4550 and a second temperature sensing electrode 4552 disposed at a second end of the temperature sensing body 4550 . Specifically, the first temperature sensing electrode 4551 is electrically connected to a first end of the temperature sensor region 4541 , and the second temperature sensing electrode 4552 is electrically connected to a second end of the temperature sensor region 4544 .

5A and 5B depict the structure of a nitride-based semiconductor chip 500 according to another embodiment of the present invention. FIG. 5A is a partial layout of a semiconductor chip 500 showing relationships among some elements, and FIG. 5B is a cross-sectional view taken along line AA' in FIG. 5A. The stacked semiconductor structure of the nitride-based semiconductor chip 500 is similar to that of the nitride-based semiconductor chip 100 . For the sake of brevity, the same or similar elements in FIGS. 5A and 5B are given the same reference numerals as in FIGS. 1A and 1B and will not be described in further detail.

5A and 5B, a semiconductor chip 500 may include a transistor Q5 and a temperature sensor T5. Transistor Q5 may comprise an MxN array of transistor regions 553_mn, where m=1, . . . , M and n=1, . . . , N.

Temperature sensor T5 may have a temperature sensing body 5550 comprising a PxQ array of temperature sensor regions 554_pq, where p=1, . . . , P and q=1, . . . , Q. P is an integer equal to M, and Q is an integer smaller than N by 1. That is, P=M and Q=N-1. Preferably, N is an even number and Q is an odd number.

Each row of temperature sensor regions can be vertically aligned with a corresponding row of transistor regions, and each temperature sensor region can be positioned between two adjacent transistor regions.

The temperature sensing body 5550 may further include horizontal bridges 556H_r for connecting all temperature sensor areas in the same row, where r=1, . . . , R and R is the total number of horizontal bridges. The temperature sensing body 4550 may further include vertical bridges 556V_s for providing connections between adjacent rows of temperature sensor regions, where s = 1, . . . , S and S is the total number of vertical bridges.

The temperature sensor T5 may further include a first temperature sensing electrode 5551 disposed at a first end of the temperature sensing body 5550 and a second temperature sensing electrode 5552 disposed at a second end of the temperature sensing body 5550 . Specifically, the first temperature sensing electrode 5551 is electrically connected to the first end of the temperature sensor region 554_11 (ie, p=1 and q=1), and the second temperature sensing electrode 5552 is electrically connected to the end of the temperature sensor region 554_PQ. The second end (ie, p=P and q=Q).

The different stages of a method for manufacturing a semiconductor chip according to the invention are illustrated in FIGS. 6A to 6D and described below. Hereinafter, deposition techniques may include, for example but not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), plasma assisted vapor deposition, epitaxial growth, or other suitable processes. The process for forming the passivation layer used as a planarization layer typically includes a chemical mechanical polishing (CMP) process. Processes for forming conductive vias typically include forming vias in a passivation layer and filling the vias with a conductive material. Processes for forming conductive traces typically include photolithography, exposure and development, etching, other suitable processes, or combinations thereof.

Referring to Figure 6A, a substrate 102 (typically about 0.7 to 1.2 mm thick) is provided.

Referring to FIG. 6B , two nitride-based semiconductor layers 104 and 106 may then be formed on the substrate 102 using the deposition techniques described above. The nitride-based semiconductor layer 104 serves as a primary current channel, and the nitride-based semiconductor layer 106 serves as a barrier layer. Accordingly, a 2DEG region is formed adjacent to the heterojunction interface between the nitride-based semiconductor layer 104 and the nitride-based semiconductor layer 106 . The formation of the nitride-based semiconductor layers 104 and 106 may include depositing a GaN or InGaN material layer with a thickness of generally about 0.01 μm to about 0.5 μm to form a conductive region, and depositing a material layer composed of AlGaN, wherein the Al fraction (ie, the Al content , such that the Al fraction plus the Ga fraction equals 1) is in the range of about 0.1 to about 1.0, and the thickness is in the range of about 0.01 μm to about 0.03 μm to form the barrier layer.

Referring to FIG. 6C , isolation regions 52 are formed in nitride-based semiconductor layers 104 and 106 . The isolation region 52 may be formed by implanting nitrogen (N) to break the lattice structure of the barrier layer 106 to prevent the formation of 2DEG.

Referring to FIG. 6D , one or more gate structures 110 , S/D electrodes 116 and a pair of temperature sensing electrodes 551 , 552 are then formed on the nitride-based semiconductor layer 106 . The gate structure 110 can be formed, for example, by depositing a p-type GaN material on the surface of the nitride-based semiconductor layer 106, etching the gate structure 110 with the p-type GaN material, and forming, for example, tantalum (Ta), titanium (Ti ), titanium nitride (TiN), tungsten (W) or tungsten silicide (WSi ₂ ) and other refractory metal contacts. It should be understood that other known methods and materials for providing the gate structure 110 may also be used. The temperature sensing electrodes 551 , 552 and the S/D electrodes 116 may be formed of any known ohmic contact metal such as Ti and/or Al along with a capping metal such as Ni, Au, Ti or TiN. The thickness of the metal layer and the gate layer are each preferably about 0.01 μm to about 1.0 μm, and are then annealed at a high temperature (eg, 800° C.) for 60 seconds.

It should be understood that passivation and routing (conductive) layers may then be deposited and etched to form connections between the temperature sensing electrodes 551/552, the gate structure 110 and the electrodes 116 with external circuitry.

The embodiment was chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated . Although methods disclosed herein have been described with reference to certain operations performed in a particular order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the disclosure. Accordingly, the order and grouping of operations is not limiting unless specifically indicated herein. Although the devices disclosed herein have been described with reference to specific structures, shapes, materials, compositions of matter and relationships, etc., such descriptions and illustrations are not limiting. Modifications may be made to adapt a particular situation to the aim, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the appended claims.

Claims (20)

1. A nitride-based semiconductor integrated circuit (IC) chip comprising at least one transistor and a temperature sensor configured to sense the temperature of the transistor, Wherein the transistor and the temperature sensor are formed on a stacked semiconductor structure, the stacked semiconductor structure includes: Substrate; a first nitride-based semiconductor layer disposed over the substrate; and a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a band gap larger than that of the first nitride-based semiconductor layer so as to be adjacent to the first nitride-based semiconductor layer A heterojunction between the layer and the second nitride-based semiconductor layer forms a two-dimensional electron gas (2DEG) layer; wherein the 2DEG layer is divided by one or more isolation regions into one or more transistor regions for forming the transistors and one or more temperature sensor regions for forming the temperature sensors; and Wherein said temperature sensor comprises: a temperature sensing body comprising one or more bridges for connecting said one or more temperature sensor regions to form said temperature sensing body; a first temperature sensing electrode electrically connected to the first end of the temperature sensing body; and a second temperature sensing electrode electrically connected to the second end of the temperature sensing body; wherein said transistors include: at least one pair of a drain electrode and a source electrode disposed over the second nitride-based semiconductor layer; and at least one gate structure disposed between the at least one pair of drain and source electrodes; and Wherein the first temperature sensing electrode and the second temperature sensing electrode are formed by patterning the blanket metal layer used to form the drain electrode and the source electrode. 2. The nitride-based semiconductor IC chip according to claim 1, wherein the first temperature sensing electrode and the second temperature sensing electrode are in ohmic contact with the second nitride-based semiconductor layer . 3. The nitride-based semiconductor IC chip according to claim 2, wherein: the one or more transistor regions include a first transistor region and a second transistor region vertically aligned with the first transistor region and horizontally spaced apart from the first transistor region; and The one or more temperature sensor regions include a first temperature sensor vertically aligned with and positioned between the first transistor region and the second transistor region sensor area. 4. The nitride-based semiconductor IC chip according to claim 2, wherein: The one or more transistor regions include a first transistor region and a second transistor region horizontally aligned with the first transistor region and vertically spaced apart from the first transistor region; The one or more temperature sensor zones include a first temperature sensor zone, a second temperature sensor zone, a third temperature sensor zone, and a fourth temperature sensor zone; the first temperature sensor zone and the second temperature sensor zone are horizontally aligned and vertically spaced apart from each other; the third temperature sensor zone and the fourth temperature sensor zone are horizontally aligned and vertically spaced apart from each other; the first temperature sensor region and the fourth temperature sensor region are each vertically aligned with the second transistor region and are respectively positioned at two opposite sides of the second transistor region; the second temperature sensor region and the third temperature sensor region are each vertically aligned with the first transistor region and are respectively positioned at two opposite sides of the first transistor region; The one or more bridges include: a first vertical bridge electrically connecting the second end of the first temperature sensor zone to the first end of the second temperature sensor zone; a first horizontal bridge, It electrically connects the second end of the second temperature sensor area with the first end of the third temperature sensor area; a second vertical bridge electrically connects the second end of the third temperature sensor area with the The first end of the fourth temperature sensor zone. 5. The nitride-based semiconductor IC chip according to claim 2, wherein: The one or more transistor regions include a first transistor region and a second transistor region horizontally aligned with the first transistor region and vertically spaced apart from the first transistor region; The one or more temperature sensor zones include a first temperature sensor zone, a second temperature sensor zone, a third temperature sensor zone, and a fourth temperature sensor zone; the first temperature sensor region and the second temperature sensor region are each vertically aligned with the first transistor region and are respectively positioned at two opposite sides of the first transistor region; the third temperature sensor region and the fourth temperature sensor region are each vertically aligned with the second transistor region and are respectively positioned at two opposite sides of the second transistor region; the first temperature sensor zone and the third temperature sensor zone are horizontally aligned and vertically spaced apart from each other; the second temperature sensor zone and the fourth temperature sensor zone are horizontally aligned and vertically spaced apart from each other; The one or more bridges include: a first horizontal bridge electrically connecting the second end of the first temperature sensor region to the first end of the second temperature sensor region; a first vertical bridge, It electrically connects the second end of the second temperature sensor area and the first end of the third temperature sensor area; a second horizontal bridge electrically connects the second end of the third temperature sensor area and the The first end of the fourth temperature sensor zone. 6. The nitride-based semiconductor IC chip according to any one of claims 1 to 5, wherein the 2DEG layer has a temperature coefficient of resistance substantially equal to 9000 ppm/K. 7. The nitride-based semiconductor IC chip according to any one of claims 1 to 5, wherein the substrate is made of silicon. 8. The nitride-based semiconductor IC chip according to any one of claims 1 to 5, wherein the first nitride-based semiconductor layer is made of gallium nitride. 9 . The nitride-based semiconductor IC chip according to claim 1 , wherein the first nitride-based semiconductor layer is made of aluminum gallium nitride. 10. The nitride-based semiconductor IC chip according to any one of claims 1 to 5, wherein the first temperature sensing electrode and the second temperature sensing electrode are made of titanium. 11. A method for manufacturing a nitride-based semiconductor integrated circuit (IC) chip comprising at least one transistor and at least one temperature sensor for sensing the temperature of said transistor, characterized in that said method comprises: growing a first nitride-based semiconductor layer on the substrate; A second nitride-based semiconductor layer is grown on the first nitride-based semiconductor layer, the second nitride-based semiconductor layer has a band gap larger than that of the first nitride-based semiconductor layer so that adjacent to the A heterojunction between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer forms a two-dimensional electron gas (2DEG) layer; One or more isolation regions are formed in the first nitride-based semiconductor layer and the second nitride-based semiconductor layer to divide the 2DEG layer into one or more temperature regions for forming the temperature sensor. a sensing region and one or more transistor regions for forming said transistor; forming one or more bridges to connect the one or more temperature sensor regions in series to form a temperature sensing body of the temperature sensor; forming a first temperature sensing electrode electrically connected to the first end of the temperature sensing body; forming a second temperature sensing electrode electrically connected to the second end of the temperature sensing body; forming at least one pair of a drain electrode and a source electrode disposed over the second nitride-based semiconductor layer; and forming a gate structure disposed between the drain electrode and the source electrode; Wherein the first temperature sensing electrode and the second temperature sensing electrode are formed by patterning the blanket metal layer used to form the drain electrode and the source electrode. 12. The method according to claim 11, wherein the first temperature sensing electrode and the second temperature sensing electrode are in ohmic contact with the second nitride-based semiconductor layer. 13. The method of claim 12, wherein, the one or more transistor regions include a first transistor region and a second transistor region vertically aligned with the first transistor region and horizontally spaced apart from the first transistor region; and The one or more temperature sensor regions include a first temperature sensor vertically aligned with and positioned between the first transistor region and the second transistor region sensor area. 14. The method of claim 12, wherein, The one or more transistor regions include a first transistor region and a second transistor region horizontally aligned with the first transistor region and vertically spaced apart from the first transistor region; The one or more temperature sensor zones include a first temperature sensor zone, a second temperature sensor zone, a third temperature sensor zone, and a fourth temperature sensor zone; the first temperature sensor zone and the second temperature sensor zone are horizontally aligned and vertically spaced apart from each other; the third temperature sensor zone and the fourth temperature sensor zone are horizontally aligned and vertically spaced apart from each other; the first temperature sensor region and the fourth temperature sensor region are each vertically aligned with the second transistor region and are respectively positioned at two opposite sides of the second transistor region; the second temperature sensor region and the third temperature sensor region are each vertically aligned with the first transistor region and are respectively positioned at two opposite sides of the first transistor region; The one or more bridges include: a first vertical bridge electrically connecting the second end of the first temperature sensor region to the first end of the second temperature sensor region; a first horizontal bridge, It electrically connects the second end of the second temperature sensor area with the first end of the third temperature sensor area; a second vertical bridge electrically connects the second end of the third temperature sensor area with the The first end of the fourth temperature sensor zone. 15. The method of claim 12, wherein, The one or more transistor regions include a first transistor region and a second transistor region horizontally aligned with the first transistor region and vertically spaced apart from the first transistor region; The one or more temperature sensor zones include a first temperature sensor zone, a second temperature sensor zone, a third temperature sensor zone, and a fourth temperature sensor zone; the first temperature sensor region and the second temperature sensor region are each vertically aligned with the first transistor region and are respectively positioned at two opposite sides of the first transistor region; the third temperature sensor region and the fourth temperature sensor region are each vertically aligned with the second transistor region and are respectively positioned at two opposite sides of the second transistor region; the first temperature sensor zone and the third temperature sensor zone are horizontally aligned and vertically spaced apart from each other; the second temperature sensor zone and the fourth temperature sensor zone are horizontally aligned and vertically spaced apart from each other; The one or more bridges include: a first horizontal bridge electrically connecting the second end of the first temperature sensor region to the first end of the second temperature sensor region; a first vertical bridge, It electrically connects the second end of the second temperature sensor area and the first end of the third temperature sensor area; a second horizontal bridge electrically connects the second end of the third temperature sensor area and the The first end of the fourth temperature sensor zone. 16. The method according to any one of claims 11 to 15, characterized in that the 2DEG layer has a temperature coefficient of resistance substantially equal to 9000 ppm/K. 17. The method according to any one of claims 11 to 15, characterized in that the substrate is made of silicon. 18. The method according to any one of claims 11 to 15, wherein the first nitride-based semiconductor layer is made of gallium nitride. 19. The method according to any one of claims 11-15, wherein the first nitride-based semiconductor layer is made of aluminum gallium nitride. 20. The method according to any one of claims 11 to 15, wherein the first temperature sensing electrode and the second temperature sensing electrode are made of titanium.

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