CN116320557A

CN116320557A - Control method and electronic equipment

Info

Publication number: CN116320557A
Application number: CN202310262312.9A
Authority: CN
Inventors: 陈培雯; 乔巧
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2023-03-14
Filing date: 2023-03-14
Publication date: 2023-06-23

Abstract

The application discloses a control method and electronic equipment, wherein the method comprises the following steps: obtaining a first signal output by a sensor; processing the first signals through a control chip to obtain a plurality of second signals; wherein the plurality of second signals are for providing to a processor to cause the processor to obtain target data from the second signals; the different second signals are used to obtain different target data.

Description

Control method and electronic equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a control method and an electronic device.

Background

The basis of vibration analysis is the data acquisition of the sensor. For example, for high-frequency vibration, three data of displacement, velocity, and acceleration are required.

At present, a multi-path sampling mode is adopted, and signals acquired by a sensor are subjected to differential sampling through multi-path sampling hardware so as to obtain multi-path signals.

However, this solution requires the laying of multiple sampling hardware, resulting in higher hardware wiring complexity.

Disclosure of Invention

In view of this, the present application provides a control method and an electronic device, as follows:

a control method, comprising:

obtaining a first signal output by a sensor;

processing the first signals through a control chip to obtain a plurality of second signals;

wherein the plurality of second signals are for providing to a processor to cause the processor to obtain target data from the second signals; the different second signals are used to obtain different target data.

In the above method, preferably, the processing, by the control chip, the first signal to obtain a plurality of second signals includes:

and sampling the first signals according to a plurality of sampling frequencies by the control chip to obtain a plurality of second signals, wherein the signal frequencies of the second signals are different.

the first identifier is set to be a first value through the control chip, and the first value is used for indicating the control chip to output the first signal to a first bus, so that the control chip processes the first signal on the first bus to obtain a plurality of second signals.

In the above method, preferably, before setting the first flag to the first value by the control chip, the method further includes:

and setting a second identifier to a second value through the control chip, wherein the second value is used for indicating the control chip to convert the first signal into a target format.

In the above method, preferably, after the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further includes:

resetting the first identifier;

wherein after setting the first flag to the first value by the control chip, the method further comprises:

monitoring whether the duration of the first flag set to the first value reaches a target duration;

re-executing the following steps when the duration reaches the target duration: and setting the first identifier to be a first value through the control chip.

In the above method, preferably, the second signal corresponds to a channel identifier;

wherein after the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further comprises:

and storing the second signal into a register corresponding to the channel identifier through the control chip according to the channel identifier, so that the second signal is read from the register corresponding to the channel identifier by the processor through a second bus, and the second bus is connected between the control chip and the processor.

The above method, preferably, further comprises:

resetting the first identifier and the second identifier through the control chip.

In the above method, preferably, before the first signal is processed by the control chip to obtain a plurality of second signals, the method further includes:

and processing the first signal of the alternating current type to obtain the first signal of the direct current type.

An electronic device, comprising:

a sensor for outputting a first signal;

the control chip is used for obtaining the first signal; processing the first signal to obtain a plurality of second signals; wherein the plurality of second signals are for providing to a processor to cause the processor to obtain target data from the second signals; the different second signals are used to obtain different target data.

In the electronic device, the control chip is a field programmable gate array FPGA (Field Programmable Gate Array).

According to the control method and the electronic device disclosed by the application, the control chip is configured between the sensor and the processor, and the control chip processes the first signals output by the sensor into a plurality of second signals, so that the processor can obtain different target data for each second signal. Therefore, the multipath signal acquisition is realized without arranging a plurality of sensors, and the signal is split through the control chip, so that the processor can process the split signals to obtain corresponding target data, the hardware layout of the target data obtained in the electronic equipment is reduced, and the hardware complexity in the electronic equipment is further reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a control method according to a first embodiment of the present application;

FIGS. 2, 3 and 4 are respectively exemplary diagrams of embodiments of the present application;

FIG. 5 is another flow chart of a control method according to the first embodiment of the present application;

FIG. 6 is another exemplary diagram of an embodiment of the present application;

fig. 7 is a schematic structural diagram of an electronic device according to a second embodiment of the present application;

FIG. 8 is a diagram showing an example of a structure of the present application for signal splitting processing in the vibration analysis field;

FIG. 9 is an exemplary diagram of a split multi-path signal waveform suitable for use in the vibration analysis field of the present application;

fig. 10 is an exemplary diagram of identification states and processing stages of an FPGA suitable for use in the vibration analysis field of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Referring to fig. 1, a flowchart of a control method according to an embodiment of the present application is shown, where the method may be configured in an electronic device, such as a computer or a server, having a control chip and a processor. The technical scheme in the embodiment is mainly used for reducing the hardware complexity of obtaining the target data in the electronic equipment.

Specifically, the method in this embodiment may include the following steps:

step 101: a first signal of the sensor output is obtained.

The sensor may be a sensor capable of acquiring vibration data. For example, a vibration sensor disposed on a target object such as a moving object, the vibration sensor being capable of collecting vibration data generated by vibration of the target object, and the vibration sensor outputting the vibration data, i.e., a first signal. Based on this, the first signal output by the sensor is received in this embodiment.

Step 102: and processing the first signals through the control chip to obtain a plurality of second signals, wherein the plurality of second signals are used for being provided for the processor so that the processor can obtain target data according to the second signals.

Wherein the second, different signal is used to obtain different target data.

Specifically, the control chip may be connected to the sensor, so that after the sensor outputs the first signal, the first signal may be transmitted to the control chip, and the control chip processes the first signal, so as to obtain a plurality of second signals, thereby implementing multi-path acquisition of vibration data, and then the control chip provides the obtained plurality of second signals to a processor connected to the control chip, and the processor obtains corresponding target data according to each second signal.

For example, as shown in fig. 2, the control chip may be a field programmable gate array FPGA (Field Programmable Gate Array), the processor is a central processor CPU (Central Processing Unit), the FPGA is respectively connected with the vibration sensor and the CPU, the FPGA branches the first signal output by the vibration sensor to obtain a plurality of second signals, and the plurality of second signals are provided to the CPU, and the CPU respectively processes each of the second signals to obtain corresponding target data, such as displacement data of the target object, speed data of the target object, acceleration data of the target object, and the like.

As can be seen from the above, in the control method provided in the first embodiment of the present application, by configuring the control chip between the sensor and the processor, the control chip processes the first signal output by the sensor into a plurality of second signals, so that the processor can obtain different target data for each of the second signals. Therefore, in this embodiment, multiple sensors are not required to be provided to realize multiple signal acquisition, and the control chip is used to perform signal splitting, so that the processor can process multiple split signals to obtain corresponding target data, thereby reducing the hardware layout of the electronic device for obtaining the target data, and further reducing the hardware complexity in the electronic device.

In addition, in the embodiment, the processing of the signal branching is executed by the control chip, so that the situation that the operation pressure of the processor is overlarge due to the fact that the processor executes the signal branching and the target data acquisition is avoided, and the processing rate of the processor is improved.

In one implementation manner, when the control chip processes the first signals to obtain a plurality of second signals in step 102, the following manner may be implemented:

and through the control chip, the first signals are sampled according to a plurality of sampling frequencies to obtain a plurality of second signals, and the signal frequencies of the second signals are different.

The plurality of sampling frequencies are different from each other, so that the control chip can obtain second signals with different signal frequencies after respectively sampling the first signals according to the different sampling frequencies.

For example, as shown in fig. 3, the FPGA samples the first signal output from the vibration sensor at the first sampling frequency, the second sampling frequency, and the third sampling frequency, respectively, thereby obtaining a plurality of second signals having different signal frequencies, and provides the plurality of second signals to the CPU, and the CPU processes each of the second signals, respectively, to obtain corresponding target data, such as displacement data of the target object, velocity data of the target object, acceleration data of the target object, and the like.

Wherein the first sampling frequency is a frequency greater than 0 and less than 10Hz, the second sampling frequency is a frequency greater than or equal to 10Hz and less than 1000Hz, and the third sampling frequency is a frequency greater than or equal to 1000Hz, thereby realizing signal output in a low frequency range (2-50 Hz), an intermediate frequency range (2-5 KHz) and a high frequency range (2-50 KHz).

In one implementation, when the control chip processes the first signals to obtain a plurality of second signals in step 102, the following manner may be implemented:

the first identifier is set to a first value through the control chip, and the first value is used for indicating the control chip to output a first signal to the first bus, so that the control chip processes the first signal on the first bus to obtain a plurality of second signals.

The first bus may be a serial bus on the control chip, and may be used for signal processing.

For example, the first identifier may be nRD identifier, and the first value may be 1, which indicates that the FPGA needs to output the first signal to the first bus, so that the FPGA samples the first signal on the first bus according to a plurality of different sampling frequencies, so as to obtain a plurality of second signals with different signal frequencies, and the CPU processes the second signals with different signal frequencies respectively, so as to obtain different target data.

The first flag may also be set to other values, such as 0, indicating that the FPGA does not need to be processed.

Further, before the first flag is set to the first value by the control chip in step 102, the second flag may be set to the second value by the control chip, where the second value is used to instruct the control chip to convert the first signal into the target format.

Specifically, the second value is used to instruct the control chip to convert the first signal from an analog format to a digital format.

For example, the second identifier may be a CONV identifier, and the second value may be 1, so as to indicate that the FPGA needs to perform format conversion on the first signal output by the vibration sensor through an Analog-to-digital converter ADC (Analog-to-Digital Converter) mounted on the circuit board of the FPGA, so as to obtain a first signal in a digital format, so that signal splitting of the subsequent FPGA and signal processing of the CPU are facilitated.

It should be noted that, after the control chip finishes converting the first signal into the target format, the third flag, such as EOC, may be set to 0 to indicate that the control chip finishes converting the first signal into the target format.

In addition, in this embodiment, the third flag may be set by the control chip to a third value, where the third value is used to point to one of the ADCs on the control chip, so that after the ADC converts the first signal into the target format, the converted first signal is output to the first bus, so that the control chip processes the first signal on the first bus to obtain a plurality of second signals.

For example, the third identifier is an nCS identifier, and the third value may be an identifier, such as a code, of one of the ADCs mounted on the circuit board where the FPGA is located, so that the ADC pointed by the third value on the FPGA outputs the first signal after analog-to-digital conversion to the first bus, so that the FPGA samples the first signal on the first bus according to a plurality of different sampling frequencies, so as to obtain a plurality of second signals with different signal frequencies, and the CPU processes the second signals with different signal frequencies, so as to obtain different target data.

Based on the above implementation manner, after the control chip processes the first signal on the first bus to obtain a plurality of second signals, in this embodiment, the first identifier may be reset by the control chip, so that the first identifier is other values, such as 0, to indicate that the FPGA does not need to process, and the first identifier is set to the first value only when the control chip is required to split only the signal.

Further, in this embodiment, after the first flag is set to the first value by the control chip in step 102, whether the duration of the first flag set to the first value reaches the target duration may be monitored, and if the duration reaches the target duration, the first flag is set to the first value by the control chip in step 102 again.

The target duration may be a duration of a processing cycle preset in the control chip, such as a clock cycle CLK (Clock Cycle). Therefore, since the control chip is reset after obtaining the second signal, in this embodiment, after setting the first flag to the first value, whether the control chip branches the first signal to obtain a plurality of second signals in the target duration may be monitored by monitoring whether the duration of the first flag set to the first value reaches the target duration, if the control chip does not obtain the second signals in the target duration, the first flag may be reset to the first value in this embodiment, so as to instruct the control chip to branch the first signal again until the control chip obtains the plurality of second signals.

In addition, in this embodiment, a loop-out condition may be set, for example, in a case where the number of times of resetting the first flag exceeds the number of times threshold, for example, 10 times, but the control chip still does not obtain the plurality of second signals, the first flag is not reset to the first value, that is, the current branching process of the first signal is stopped, and further, a failure signal may be output to the processor to indicate that the signal acquisition fails.

For example, the first identifier may be a nRD identifier, the first value may be 1, the second identifier may be a CONV identifier, the second value may be 1, the third identifier is an nCS identifier, the third value may be an identifier of one of the ADCs mounted on the circuit board where the FPGA is located, so that the ADC pointed by the third value on the FPGA converts the first signal into a digital format, and outputs the converted first signal to the first bus, so that the FPGA samples the first signal on the first bus according to a plurality of different sampling frequencies, so as to obtain a plurality of second signals with different signal frequencies, and after obtaining the second signal, resets the nRD identifier to 0. In this process, the continuous monitor nRD identifies whether the duration set to 1 exceeds one clock cycle, if the duration exceeds one clock cycle, the FPGA still does not obtain the second signal, then the reset nRD identifies 1 to re-trigger the ADC pointed to by the third value on the FPGA to convert the first signal to digital format, and outputs the converted first signal onto the first bus until the FPGA samples the first signal on the first bus at a plurality of different sampling frequencies, respectively, to obtain the second signal at a plurality of different signal frequencies, or the number of times the reset nRD identifies 1 exceeds the count threshold.

Based on the above implementation manner, the second signal corresponds to a channel identifier, such as an identifier representing a different signal frequency, that is, representing a different sampling frequency, so as to uniquely characterize the second signal.

Based on this, in step 102, after the control chip processes the first signal on the first bus to obtain a plurality of second signals, the second signals may also be saved by the control chip into registers corresponding to the channel identifiers according to the channel identifiers, so that the second signals are read by the processor from the registers corresponding to the channel identifiers through the second bus, where the second bus is connected between the control chip and the processor.

For example, the different sampling frequencies correspond to different channel identifications, such as channel identification 1, channel identification 2 and channel identification 3, based on which the FPGA, after obtaining the second signals of the plurality of different signal frequencies, saves each of the second signals in the respective registers, such as register a, register b and register c, respectively, according to the respective channel identifications, whereby the CPU can read the respective second signals from the respective registers a, register b and register c, respectively, according to channel identification 1, channel identification 2 and channel identification 3, respectively, through the second bus S between the FPGA and the CPU, as shown in fig. 4, whereby the CPU processes the second signals of the different signal frequencies, respectively, to obtain different target data, such as displacement data, velocity data and acceleration data.

Based on the above implementation manner, in this embodiment, the first identifier and the second identifier may also be reset by the control chip, for example, the first identifier is reset to 0 and the second identifier is reset to 0, so that the next signal splitting process is performed by the control chip.

In one implementation, before the first signal is processed by the control chip to obtain a plurality of second signals in step 102, the following steps may be further included, as shown in fig. 5:

step 103: and processing the first signal of the alternating current type to obtain a first signal of the direct current type.

In this embodiment, a dc blocking filter may be disposed in front of the control chip, and the ac type first signal output by the sensor is subjected to dc filtering to obtain a dc type first signal, and then the dc type first signal is split by the control chip to obtain a plurality of second signals.

For example, a blocking filter L is arranged in front of the FPGA, the first signal in the analog format output by the vibration sensor is converted into direct current, then the ADC converts the first signal in the direct current into digital format, and the converted first signal is output to the first bus, so that the FPGA samples the first signal on the first bus according to a plurality of different sampling frequencies to obtain a plurality of second signals with different signal frequencies, after obtaining the second signals, each second signal is stored in a corresponding register according to a corresponding channel identifier, such as a register a, a register b and a register c, so that the CPU can read the corresponding second signals from the corresponding registers a, b and c according to the channel identifier 1, the channel identifier 2 and the channel identifier 3, respectively, through a second bus S between the FPGA and the CPU, as shown in fig. 6, so that the CPU processes the second signals with different signal frequencies, respectively, and obtains different target data, such as displacement data, velocity data and acceleration data.

Referring to fig. 7, a schematic structural diagram of an electronic device according to a second embodiment of the present application may include the following structure:

a sensor 701 for outputting a first signal.

A control chip 702 for obtaining a first signal; the first signal is processed to obtain a plurality of second signals. The control chip 702 is an FPGA.

A processor 703 for obtaining target data from the second signal; the second, different signal is used to obtain different target data.

As can be seen from the above, in the electronic device provided in the second embodiment of the present application, by configuring the control chip between the sensor and the processor, the control chip processes the first signal output by the sensor into a plurality of second signals, so that the processor can obtain different target data for each second signal. Therefore, in this embodiment, multiple sensors are not required to be provided to realize multiple signal acquisition, and the control chip is used to perform signal splitting, so that the processor can process multiple split signals to obtain corresponding target data, thereby reducing the hardware layout of the electronic device for obtaining the target data, and further reducing the hardware complexity in the electronic device.

Taking the field of vibration analysis as an example, the basis of vibration analysis is data acquisition of a sensor, and displacement peak-to-peak value, velocity effective value, acceleration peak value and high-frequency acceleration envelope effective value are the most frequently required effective data, wherein the same-signal difference sampling is used. Low frequency vibration (< 10 Hz) is measured using displacement; the medium frequency vibration (10-1000 Hz) adopts speed measurement; high frequency vibrations (> 1000 Hz) are measured using acceleration. For high-frequency vibration, three data including displacement, speed and acceleration are needed to be obtained, and the following two modes exist in the prior art:

in one mode, a multi-path sampling mode is adopted, and one analog signal adopts a multi-path difference sampling mode, but the defects of high hardware cost and complex field wiring are generated.

In another way, one path of high-speed sampling is adopted, and software analyzes the data, but a high calculation force requirement on the CPU is generated, and a large amount of calculation pressure is generated.

Aiming at the problems, the application provides a path of analog quantity virtual channel acquisition scheme, and the signal frequency is adjustable by simulating multiple channels through hardware. In addition, the sampling signals are preprocessed through the FPGA, and the needed frequency signals can be selected according to the set frequency range. The specific scheme is as follows:

firstly, FPGA is used as a core of acquisition, and triggering, acquisition and preprocessing are completed in the FPGA. As shown in fig. 8, the sensor transmits the collected vibration data to the GAIN of the operational amplifier for proportional amplification, and then, after being calibrated by CAL (CALibration), the sensor transmits the vibration data in a digital format to the ADC connected to the FPGA for analog-to-digital conversion, the FPGA respectively samples the vibration data according to different sampling frequencies, the sampled data with multiple different signal frequencies are provided to the CPU through the local bus (local), and the CPU obtains corresponding displacement data, velocity data and acceleration data.

The FPGA simulates a plurality of channels according to a set sampling frequency and a set frequency value from a sampling rate signal of 250KHz, namely, respectively adopts the channels, and specific channel identifications, frequency ranges and corresponding signal frequencies are shown in table 1. In addition, the signal is converted into a direct current type by a pre-cut-off filter before sampling.

Table 1 channels and frequencies

Channel identification	Frequency range	Signal frequency
				1	2-50Hz	Low frequency:<10Hz
2	2-5KHz	intermediate frequency: 10-1000 Hz
			3	2-50KHz	>1000Hz

The signal waveforms corresponding to the plurality of channel identifications based on this result are shown in fig. 9.

The identification state and the processing stage of the FPGA are as shown in fig. 10:

stage 0→idle: i.e., start=0, all signals are set to inactive (waiting for Start to be set to 1);

stage 1→convs: set CONV, reset Flag (for waiting 7 cycles);

stage 2→eoc: (waiting for nEOC to be zero), nEOC to be 0 indicates that the ADC has completed data conversion;

stage 3→read_set: reset CONV, set nCS and nRD. And holds one CLK;

stage 4→read_res: resetting nRD, namely placing the data converted by the ADC into a corresponding register (a plurality of groups of corresponding data registers are placed according to the value of the channel identifier CH-Enable);

stage 6→write_set: all signals are set to be invalid, which indicates that the current data processing is finished.

Stage 7→write: setting nCS, nWR, BUS _control, data_out, etc. to initial values;

stage 8→release: reset nCS, nWR, nRD to facilitate the next data processing.

Therefore, by adopting the technical scheme, the system can be used for sampling all the way, the on-site wiring is simple, and the hardware cost is low. In addition, the data preprocessing and the channel simulation are performed through hardware, so that CPU resources are not occupied. In addition, the data obtained from the CPU in the application are processed, so that the entering threshold of software in the CPU is reduced, and the popularization of schemes is facilitated.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method, comprising:

obtaining a first signal output by a sensor;

2. The method of claim 1, processing, by a control chip, the first signal to obtain a plurality of second signals, comprising:

3. The method of claim 1 or 2, processing the first signal by a control chip to obtain a plurality of second signals, comprising:

4. The method of claim 3, prior to setting the first flag to the first value by the control chip, the method further comprising:

5. The method of claim 3, after the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further comprising:

resetting the first identifier;

6. A method according to claim 3, the second signal corresponding to a channel identification;

7. The method of claim 4, further comprising:

8. The method of claim 1, further comprising, prior to processing the first signal by a control chip to obtain a plurality of second signals:

9. An electronic device, comprising:

a sensor for outputting a first signal;

10. The electronic device of claim 9, the control chip being a field programmable gate array FPGA.