CN116318084A - Differential hysteresis comparison circuit and method - Google Patents

Abstract

The present disclosure provides a differential hysteresis comparison circuit and method, the differential hysteresis comparison circuit comprising: a differential input circuit for inputting a first differential signal and a second differential signal; the positive feedback hysteresis circuit is connected with the differential input circuit and is used for comparing the first differential signal with the second differential signal to obtain a differential comparison result, outputting a first comparison result signal when the differential comparison result is larger than a first threshold voltage, and outputting a second comparison signal when the differential comparison result is smaller than a second threshold voltage, wherein the first threshold voltage is larger than the second threshold voltage; and the output stage circuit is connected with the positive feedback hysteresis circuit and is used for converting the first comparison result signal or the second comparison result signal into a single-ended signal for output.

Description

Differential hysteresis comparator circuit and method

technical field

The present disclosure relates to the technical field of integrated circuits, in particular to a differential hysteresis comparison circuit and method.

Background technique

In the process of signal generation and transmission, due to the noise of the power supply voltage and the interference of environmental noise, the signal will appear noise. The existence of noise will affect the accuracy of the signal and cause problems such as bit errors. When a signal with noise is input into the comparator, especially when the noise amplitude of the signal near the threshold voltage of the comparator is large, the output of the comparator will flip multiple times, which will cause bit errors and affect The accuracy of the signal, although the traditional hysteresis comparator can reduce the bit error rate to a certain extent, but it is difficult to realize the hysteresis of the differential signal.

Contents of the invention

In view of the above problems, the present invention provides a differential hysteresis comparator circuit to solve the above technical problems.

One aspect of the present disclosure provides a differential hysteresis comparison circuit, including: a differential input circuit for inputting a first differential signal and a second differential signal; a positive feedback hysteresis circuit connected to the differential input circuit for comparing the The first differential signal and the second differential signal are used to obtain a differential comparison result, when the differential comparison result is greater than the first threshold voltage, the first comparison result signal is output, and when the differential comparison result is less than the second threshold voltage, the output For the second comparison signal, the first threshold voltage is greater than the second threshold voltage; the output stage circuit is connected to the positive feedback hysteresis circuit, and is used to convert the first comparison result signal or the second comparison result signal into Single-ended signal output.

Optionally, the differential input circuit includes: a first differential input circuit, including a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is connected to the first voltage signal, and the gate of the second transistor M2 is connected to Inputting a second voltage signal, the first voltage signal and the second voltage signal form a first differential signal; the second differential input circuit includes a third transistor M3 and a fourth transistor M4, the gate of the third transistor M3 is connected to input a third voltage signal, the gate of the fourth transistor M4 is connected to a fourth voltage signal, and the third voltage signal and the fourth voltage signal form a second differential signal; the first transistor M1, the The drains of the second transistor M2 are respectively connected to the positive feedback hysteresis circuit, and the first differential signal is input to the positive feedback hysteresis circuit; the drains of the third transistor M3 and the fourth transistor M4 are respectively connected to input into the positive feedback hysteresis circuit, and input the second differential signal into the positive feedback hysteresis circuit.

Optionally, the positive feedback hysteresis circuit includes: a fifth transistor M5, the gate of which is connected to the drain to form a diode connection, and the drain of which is connected to the drain of the first transistor M1 and the drain of the third transistor M3 the sixth transistor M6, its gate is connected to the gate of the fifth transistor M5 and connected to the first output terminal, and its drain is connected to the drain of the second transistor M2 and the drain of the fourth transistor M4 pole; the seventh transistor M7, the gate of which is connected to the gate of the eighth transistor M8 and connected to the second output terminal, and the drain of which is connected to the drain of the third transistor M3 and the drain of the first transistor M1; The eighth transistor M8, whose gate is connected to the drain to form a diode connection, and whose drain is connected to the drain of the fourth transistor M4 and the drain of the second transistor M2; the ninth transistor M9, whose drain is connected to the second transistor M2 The sources of a transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are connected, their sources are grounded, and their gates input a bias voltage Vbias; the fifth transistor M5, The sources of the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 input an operating voltage V _DD , the fifth transistor M5 is connected to the drain of the seventh transistor M7, and the sixth transistor M5 is connected to the drain of the seventh transistor M7. The sixth transistor M6 is connected to the drain of the eighth transistor M8.

Optionally, the voltage value of the threshold voltage V _TH is the first threshold voltage or the second threshold voltage; wherein, when the difference comparison result is greater than the first threshold voltage, the threshold voltage V _TH becomes the second threshold voltage Two threshold voltages; when the difference comparison result is less than the second threshold voltage, the threshold voltage becomes the second threshold voltage.

Optionally, the output stage circuit includes: a tenth transistor M10, the drain of which is connected to the single-ended output terminal, the source of which is grounded, and the gate of which is connected to the gate of the eleventh transistor M11; the eleventh transistor M11, Its gate is connected to the drain to form a diode connection, and its source is grounded; the gate of the twelfth transistor M12 is connected to the first output terminal, its source is input with the operating voltage V _DD , and its drain is connected to the single terminal output terminal; the thirteenth transistor M13, the gate of which is connected to the second output terminal, the source of which is input with the working voltage V _DD , and the drain of which is connected to the drain of the eleventh transistor M11.

Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10 and the tenth A transistor M11 is an NMOS transistor; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12 and the thirteenth transistor M13 For the PMOS tube.

Another aspect of the present disclosure provides a differential hysteresis comparison method, which is applied to the differential hysteresis comparison circuit described in the first aspect, and the method includes: using a differential input circuit to input a first differential signal and a second differential signal; using a positive The feedback hysteresis circuit compares the first differential signal with the second differential signal to obtain a differential comparison result, and outputs the first comparison result signal when the differential comparison result is greater than the first threshold voltage, and outputs the first comparison result signal when the differential comparison result is less than the second When the threshold voltage is low, output a second comparison signal, the first threshold voltage is greater than the second threshold voltage; use the output stage circuit to convert the first comparison result signal or the second comparison result signal into a single-ended signal output.

Optionally, including: when the differential comparison result is greater than the first threshold voltage, changing the threshold voltage V _TH of the positive feedback hysteresis circuit to a second threshold voltage; when the differential comparison result is less than the second threshold voltage , changing the threshold voltage V _TH of the positive feedback hysteresis circuit to a first threshold voltage.

Optionally, the first threshold voltage is:

The second threshold voltage is:

Wherein, n=(W/L) ₆ /(W/L) ₅ ＝(W/L) ₈ /(W/L) ₇ , β=μ ₀ C _ox (W/L) 1, 2, 3 _{, 4} , μ ₀ C _ox is the device model parameters of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, W/L is the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the fourth transistor M4 The device width-to-length ratio of the eight transistor M8, I ₉ represents the current of the ninth transistor M9.

The above at least one technical solution adopted in the embodiments of the present disclosure can achieve the following beneficial effects:

An embodiment of the present disclosure provides a differential hysteresis comparator circuit. The influence of the common mode noise in the input signal can be reduced by making a difference through the differential input circuit. When the input signal of the hysteresis comparison circuit rises from low to high and exceeds the first threshold voltage V _T ⁺ , the single-ended output terminal of the hysteresis comparison circuit The output is high level, because the first threshold voltage of the hysteresis comparison circuit is different from the second threshold voltage, even if the noise amplitude of the input signal near the first threshold voltage is large, as long as it is not lower than the second threshold voltage, the output will not Send positive flip to ensure the accuracy of the signal. Similarly, when the input signal of the hysteresis comparator circuit drops from high to low to less than the first threshold voltage V _T ^- , the output of the single-ended output terminal is a low level, and due to the hysteresis characteristic, the accuracy of the signal is guaranteed and the circuit is improved. anti-interference ability.

Description of drawings

For a more complete understanding of the present disclosure and its advantages, reference should now be made to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 schematically shows a differential hysteresis comparison circuit diagram provided by an embodiment of the present disclosure;

FIG. 2 schematically shows an equivalent circuit of a hysteresis comparison circuit provided by an embodiment of the present disclosure;

FIG. 3 schematically shows a signal waveform diagram of a differential hysteresis comparison circuit provided by an embodiment of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present disclosure. The terms "comprising", "comprising", etc. used herein indicate the presence of stated features, steps, operations and/or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

All terms (including technical and scientific terms) used herein have the meaning commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted to have a meaning consistent with the context of this specification, and not be interpreted in an idealized or overly rigid manner.

A differential hysteresis comparison circuit provided by an embodiment of the present disclosure includes a differential input circuit, a positive feedback hysteresis circuit and an output stage circuit. Wherein, the differential input circuit is used to input the first differential signal and the second differential signal; the positive feedback hysteresis circuit is connected to the differential input circuit and used to compare the first differential signal and the second differential signal to obtain a differential comparison As a result, when the differential comparison result is greater than the first threshold voltage, the first comparison result signal is output, and when the differential comparison result is less than the second threshold voltage, the second comparison signal is output, and the first threshold voltage is greater than the second threshold voltage. Threshold voltage; an output stage circuit, connected to the positive feedback hysteresis circuit, for converting the first comparison result signal or the second comparison result signal into a single-ended signal output.

FIG. 1 schematically shows a differential hysteresis comparison circuit diagram provided by an embodiment of the present disclosure.

As shown in FIG. 1 , in the embodiment of the present disclosure, the differential input circuit includes a first differential input circuit and a second differential input circuit. The first differential input circuit includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is connected to the first voltage signal V _a , the gate of the second transistor M2 is connected to the second voltage signal V _c , the first The voltage signal V _a and the second voltage signal V _c form a first differential signal V _a -V _c , and convert the first differential signal V _a -V _c into a current signal I _a -I _c ; the second differential input circuit includes a second differential signal The third transistor M3 and the fourth transistor M4, the gate of the third transistor M3 is connected to the third voltage signal V _d , the gate of the fourth transistor M4 is connected to the fourth voltage signal V _b , the third voltage signal V _d and the fourth The voltage signal V _b forms the second differential signal V _d -V _b , and converts the voltage signal V _d -V _b into a current signal I _d -I _b ; the drains of the first transistor M1 and the second transistor M2 are connected to positive feedback The hysteresis circuit inputs the first differential signal V _a -V _c to the positive feedback hysteresis circuit; the drains of the third transistor M3 and the fourth transistor M4 are connected to the positive feedback hysteresis circuit, and inputs the second differential signal V to the positive feedback hysteresis circuit _d -V _b . The first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are NMOS transistors.

In the embodiment of the present disclosure, the positive feedback hysteresis circuit includes: a fifth transistor M5, the gate of which is connected to the drain to form a diode connection, and the drain of which is connected to the drain of the first transistor M1 and the drain of the third transistor M3; Six transistors M6, the gate of which is connected to the gate of the fifth transistor M5 and connected to the first output terminal V _o1 , the drain of which is connected to the drain of the second transistor M2 and the drain of the fourth transistor M4; the seventh transistor M7, Its gate is connected to the gate of the eighth transistor M8 and connected to the second output terminal V _o2 , its drain is connected to the drain of the third transistor M3 and the drain of the first transistor M1; the gate of the eighth transistor M8 is connected to the gate of the eighth transistor M8 The drain is connected to form a diode connection, and its drain is connected to the drain of the fourth transistor M4 and the drain of the second transistor M2; the ninth transistor M9, its drain is connected to the first transistor M1, the second transistor M2, the third transistor M3 It is connected to the source of the fourth transistor M4, its source is grounded, and its gate inputs the bias voltage Vbias; the sources of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 input the operating voltage V _DD , the fifth transistor M5 is connected to the drain of the seventh transistor M7, and the drain of the sixth transistor M6 is connected to the eighth transistor M8. The ninth transistor M9 is an NMOS transistor, and the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 and the eighth transistor M8 are PMOS transistors.

Specifically, the voltage value of the threshold voltage V _TH is the first threshold voltage or the second threshold voltage; wherein, when the differential comparison result is greater than the first threshold voltage V _T ⁺ , the threshold voltage V _TH becomes the second threshold voltage V _T ^- ; When the differential comparison result is less than the second threshold voltage V _T ^- , the threshold voltage V _TH becomes the second threshold voltage V _T ^- , V _T ^- <V _T ⁺ .

In this embodiment, the first threshold voltage is:

The second threshold voltage is:

Wherein, n=(W/L) ₆ /(W/L) ₅ ＝(W/L) ₈ /(W/L) ₇ , β=μ ₀ C _ox (W/L) 1, 2, 3 _{, 4} , μ ₀ C _ox is the device model parameters of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, W/L is the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the fourth transistor M4 The device width-to-length ratio of the eight transistor M8, I ₉ represents the current of the ninth transistor M9.

FIG. 2 schematically shows an equivalent circuit of a hysteresis comparison circuit provided by an embodiment of the present disclosure.

As shown in Figure 2, the current flowing through M1 tube is I _a , the current flowing through M2 tube is I _c , the current flowing through M3 tube is I _d , the current flowing through M4 tube is I _b , and the current flowing through M5 tube The current flowing through the M6 tube is I ₅ , the current flowing through the M6 tube is I ₆ , the current flowing through the M7 tube is I ₇ , the current flowing through the M8 tube is I ₈ , and the NMOS tube M9 provides the current I ₉ for the circuit. The first differential input circuit and the second differential input circuit are superimposed to realize (V _a -V _c )+(V _d -V _b ), that is, (V _a -V _c )-(V _c -V _d ), and The voltage signal (V _a -V _b )-(V _c -V _d ) is transformed into (I _a -I _b )-(I _c -I _d ).

When the value of (V _a +V _d )-(V _c +V _b ), that is, the value of (V _a -V _b )-(V _c -V _d ) is much smaller than V _T ^- , M1 and M3 are cut off, and M2 , M4 is turned on, so M7 and M8 will be turned on, and M5 and M6 will be cut off. I ₉ all flow through M2, M4 and M8, the second output terminal V _o2 of the hysteresis comparison circuit outputs a low level, and the first output terminal V _o1 outputs a high level. As the value of (V _a -V _b )-(V _c -V _d ) increases gradually, the current of I ₉ begins to flow through M1 and M3, when the sum of the current of M1 and the current of M3 I _a +I _d = When I ₇ , the value of (V _a -V _b )-(V _c -V _d ) reaches the threshold voltage V _T ⁺ .

When this state is exceeded, that is, (V _a -V _b )-(V _c -V _d )>V _T ⁺ , most of the current I ₉ flows through M1, M3 and M5, and the second output terminal V _o2 of the hysteresis comparator circuit is determined by A low level transitions to a high level, and the first output terminal V _o1 transitions from a high level to a low level. At this time, the threshold voltage of the hysteresis comparison circuit is switched to V _T ^- , and V _T ^- <V _T ⁺ , even if (V _a -V _b )-(V _c -V _d ) falls below V _T ⁺ , as long as it is greater than V _T ^- , the output will not flip.

Similarly, when the value of (V _a +V _d )-(V _c +V _b ), that is, the value of (V _a -V _b )-(V _c -V _d ) is far greater than V _T ⁺ , M2 and M4 are cut off , M1 and M3 are turned on, so M5 and M6 will be turned on, and M7 and M8 will be cut off. I ₉ all flow through M1, M3 and M5, the second output terminal V _o2 of the hysteresis comparator circuit outputs a high level, and the first output terminal V _o1 outputs a low level. As the value of (V _a -V _b )-(V _c -V _d ) decreases gradually, the current of I ₉ starts to flow through M2 and M4, when the sum of the current of M2 and the current of M4 is I _c +I _b =I ₆ , the value of (V _a -V _b )-(V _c -V _d ) reaches the threshold voltage V _T ^- .

When this state is exceeded, that is, (V _a -V _b )-(V _c -V _d )<V _T ^- , most of the current I ₉ flows through M2, M4 and M8, and the second output terminal V _o2 of the hysteresis comparison circuit is determined by A high level transitions to a low level, and the first output terminal V _o1 transitions from a low level to a high level. At this time, the threshold voltage of the hysteresis comparison circuit is switched to V _T ⁺ , and even if (V _a -V _b )-(V _c -V _d ) rises to be greater than V _T ^- , but as long as it is less than V _T ⁺ , the output will not occur Flip.

As shown in FIG. 1 , in the embodiment of the present disclosure, the output stage circuit includes: a tenth transistor M10, the drain of which is connected to the single-ended output terminal V _out , the source of which is grounded, and the gate of which is connected to the gate of the eleventh transistor M11 pole connection; the eleventh transistor M11, its gate is connected to the drain to form a diode connection, and its source is grounded; the twelfth transistor M12, its gate is connected to the first output terminal V _o1 , and its source is input with the operating voltage V _DD , its drain is connected to the single-ended output terminal V _out ; the thirteenth transistor M13, its gate is connected to the second output terminal V _o2 , its source is input with the operating voltage V _DD , and its drain is connected to the drain of the eleventh transistor M11 pole. The tenth transistor M10 and the eleventh transistor M11 are NMOS transistors; the twelfth transistor M12 and the thirteenth transistor M13 are PMOS transistors.

In this embodiment, when the second output terminal V _o2 of the hysteresis comparison circuit is at a low level and the first output terminal V _o1 is at a high level, M12 is turned off, and M13 is turned on to transmit VDD to the drain and gate of M11 and the gate of M10, so that M10 is turned on, and the output Vout is pulled down to VSS; when the second output terminal V _o2 of the hysteresis comparison circuit is at a high level and the first output terminal V _o1 is at a low level, M13, M11 and M10 cuts off and M12 is turned on, and the output V _out is pulled down to VDD. The output stage circuit can convert the differential output of the hysteresis comparator circuit into a single-ended output, and at the same time form a push-pull structure through the PMOS transistor M12 and the NMOS transistor M10 to provide a reasonable output voltage swing.

According to a differential hysteresis comparison circuit provided by an embodiment of the present disclosure, the comparison of differential signals is realized through two sets of differential input pairs, the hysteresis comparison circuit is used to perform hysteresis comparison on the differential signals, and then the differential result is converted into a single-ended signal through the output stage circuit and output. The influence of noise on signal accuracy is reduced, and simple and effective hysteresis comparison can be performed on differential signals.

Another aspect of the present disclosure provides a differential hysteresis comparison method, which is applied to the differential hysteresis comparison circuit shown in FIG. 1 , and the method includes S1-S3.

S1, using the differential input circuit to input the first differential signal and the second differential signal.

S2. Using the positive feedback hysteresis circuit to compare the first differential signal V _a -V _c and the second differential signal V _d -V _b to obtain a differential comparison result (V _a -V _b )-(V _c -V _d ). When the differential comparison result (V _a -V _b )-(V _c -V _d ) is greater than the first threshold voltage V _T ⁺ , the first comparison result signal is output, that is, the first output terminal V _o1 outputs a low level, and the second The output terminal V _o2 outputs a high level, M13, M11 and M10 are cut off and M12 is turned on, and the output V _out will output VDD; when the differential comparison result is less than the second threshold voltage V _T ^- , the second comparison signal is output, that is, the first output Terminal V _o1 outputs a high level, the second output terminal V _o2 outputs a low level, M12 is turned off, M13 is turned on, and VDD is transmitted to the drain and gate of M11 and the gate of M10, so that M10 is turned on, and Vout is output Pulled low to VSS.

S3, using the output stage circuit to convert the first comparison result signal or the second comparison result signal into a single-ended signal for output.

In this method, when the differential comparison result is greater than the first threshold voltage V _T ⁺ , the threshold voltage V _TH of the positive feedback hysteresis circuit is changed to the second threshold voltage V _T ^- ; when the differential comparison result is less than the second threshold voltage V _T ^- , the threshold voltage V _TH of the positive feedback hysteresis circuit is changed to the first threshold voltage V _T ⁺ .

FIG. 3 schematically shows a signal waveform diagram of a differential hysteresis comparison circuit provided by an embodiment of the present disclosure.

As shown in Figure 3, the differential hysteresis comparison circuit provided by the embodiment of the present disclosure converts the differential output of the hysteresis comparison circuit into a single-ended output, and forms a push-pull structure through the PMOS transistor M12 and the NMOS transistor M10 to provide a reasonable output voltage swing. . The method reduces the influence of noise on signal accuracy, and can perform simple and effective hysteresis comparison on differential signals.

Those skilled in the art can understand that various combinations and/or combinations of the features described in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teaching of the present disclosure, the various embodiments of the present disclosure and/or the features described in the claims can be combined and/or combined in various ways. All such combinations and/or combinations fall within the scope of the present disclosure.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereto, it should be understood by those skilled in the art that other modifications may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Various changes in form and details have been made to this disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims, but also by the equivalents of the appended claims.

Claims (9)

1. A differential hysteresis comparison circuit, comprising:

a differential input circuit for inputting a first differential signal and a second differential signal;

the positive feedback hysteresis circuit is connected with the differential input circuit and is used for comparing the first differential signal with the second differential signal to obtain a differential comparison result, when the differential comparison result is larger than a first threshold voltage, a first comparison result signal is output, and when the differential comparison result is smaller than a second threshold voltage, a second comparison signal is output, and the first threshold voltage is larger than the second threshold voltage;

and the output stage circuit is connected with the positive feedback hysteresis circuit and is used for converting the first comparison result signal or the second comparison result signal into a single-ended signal for output.

2. The differential hysteresis comparison circuit of claim 1, wherein the differential input circuit comprises:

the first differential input circuit comprises a first transistor M1 and a second transistor M2, wherein a first voltage signal is connected to the grid electrode of the first transistor M1, a second voltage signal is connected to the grid electrode of the second transistor M2, and the first voltage signal and the second voltage signal form a first differential signal;

the second differential input circuit comprises a third transistor M3 and a fourth transistor M4, wherein the grid electrode of the third transistor M3 is connected with a third voltage signal, the grid electrode of the fourth transistor M4 is connected with a fourth voltage signal, and the third voltage signal and the fourth voltage signal form a second differential signal;

drains of the first transistor M1 and the second transistor M2 are respectively connected to the positive feedback hysteresis circuit, and the first differential signal is input to the positive feedback hysteresis circuit; the drains of the third transistor M3 and the fourth transistor M4 are also respectively connected to the positive feedback hysteresis circuit, and the second differential signal is input to the positive feedback hysteresis circuit.

3. The differential hysteresis comparison circuit of claim 2 wherein said positive feedback hysteresis circuit comprises:

a fifth transistor M5 having a gate connected to a drain to form a diode connection, and a drain connected to the drain of the first transistor M1 and the drain of the third transistor M3;

a sixth transistor M6 having a gate connected to the gate of the fifth transistor M5 and connected to the first output terminal, and a drain connected to the drain of the second transistor M2 and the drain of the fourth transistor M4;

a seventh transistor M7 having a gate connected to the gate of the eighth transistor M8 and connected to the second output terminal, and a drain connected to the drain of the third transistor M3 and the drain of the first transistor M1;

an eighth transistor M8, the gate of which is connected to the drain to form a diode connection, and the drain of which is connected to the drain of the fourth transistor M4 and the drain of the second transistor M2;

a ninth transistor M9 having a drain connected to sources of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, a source grounded, and a gate input bias voltage Vbias;

the sources of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 input an operating voltage V _DD The fifth transistor M5 is connected to the drain of the seventh transistor M7, and the sixth transistor M6 is connected to the drain of the eighth transistor M8.

4. A differential hysteresis comparison circuit according to claim 3, wherein said threshold voltage V _TH Is the first threshold voltage or the second threshold voltage;

wherein when the differential comparison result is greater than a first threshold voltage, the threshold voltage V _TH Becomes the second threshold voltage; when the differential comparison result is smaller than the second threshold voltage, the threshold voltage V _TH Becomes the second threshold voltage.

5. A differential hysteresis comparison circuit according to claim 3, wherein said output stage circuit comprises:

a tenth transistor M10 having a drain connected to the single-ended output terminal, a source grounded, and a gate connected to the gate of the eleventh transistor M11;

an eleventh transistor M11 having a gate connected to the drain to form a diode connection and a source connected to ground;

a twelfth transistor M12 having its gate connected to the first output terminal and its source for inputting the operating voltage V _DD The drain electrode of the single-ended output terminal is connected with the single-ended output terminal;

thirteenth transistor M13 having its gate connected to the second output terminal and its source input operating voltage V _DD The drain of which is connected to the drain of the eleventh transistor M11.

6. The differential hysteresis comparison circuit according to claim 5, wherein the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are NMOS transistors; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are PMOS transistors.

7. A differential hysteresis comparison method applied to the differential hysteresis comparison circuit according to claims 1 to 6, characterized in that the method comprises:

inputting a first differential signal and a second differential signal by using a differential input circuit;

comparing the first differential signal with the second differential signal by utilizing a positive feedback hysteresis circuit to obtain a differential comparison result, outputting a first comparison result signal when the differential comparison result is larger than a first threshold voltage, and outputting a second comparison signal when the differential comparison result is smaller than a second threshold voltage, wherein the first threshold voltage is larger than the second threshold voltage;

and converting the first comparison result signal or the second comparison result signal into a single-ended signal by using an output stage circuit to output.

8. The differential hysteresis comparison method of claim 7, comprising:

when the differential comparison result is larger than the first threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is increased _TH Becomes the second threshold voltage;

when the differential comparison result is smaller than the second threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is reduced _TH Becomes the first threshold voltage.

9. The differential hysteresis comparison method of claim 7, wherein the first threshold voltage is:

the second threshold voltage is:

wherein n= (W/L) ₆ /(W/L) ₅ ＝(W/L) ₈ /(W/L) ₇ ，β＝μ ₀ C _ox (W/L) _{1，2，3，4} ，μ ₀ C _ox For the device model parameters of the first, second, third and fourth transistors M1, M2, M3 and M4, W/L is the device aspect ratio of the fifth, sixth, seventh and eighth transistors M5, M6, M7 and M8, I ₉ The current of the ninth transistor M9 is shown.

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