CN116318028A

CN116318028A - Low-power consumption crystal oscillator driving circuit with self-checking function

Info

Publication number: CN116318028A
Application number: CN202310314774.0A
Authority: CN
Inventors: 孙洋
Original assignee: Wuxi Xijie Microelectronics Co ltd
Current assignee: Wuxi Xijie Microelectronics Co ltd
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-06-23

Abstract

The application discloses a low-power consumption crystal oscillator driving circuit with a self-checking function, which relates to the field of circuits, wherein the crystal oscillator circuit comprises a variable gain driving module, a shaping module and a frequency self-checking module; the OSCI end and the OSCO end of the variable gain driving module are connected in parallel with the crystal oscillator module and are used for controlling the crystal oscillator module to start oscillation and adjusting driving gain according to a gain feedback signal of the frequency self-checking module; the shaping module is connected in parallel with the OSCI and OSCO ends and is used for converting the OSCI and OSCO signals into square wave signals; the frequency self-checking module is connected with the output end of the shaping module and is used for detecting the frequency of the square wave signal, outputting a state signal of the crystal oscillator according to the actually measured frequency and updating a gain feedback signal. According to the scheme, the working frequency of the crystal oscillator can be detected in real time, the gain feedback signal is timely generated according to the detected frequency to change the driving current of the crystal oscillator, the starting time of the crystal oscillator can be shortened, the gain can be reduced after the crystal oscillator is stable, and the system loss is reduced.

Description

Low-power consumption crystal oscillator driving circuit with self-checking function

Technical Field

The embodiment of the application relates to the technical field of oscillators, in particular to a low-power consumption crystal oscillator driving circuit with a self-checking function.

Background

The quartz crystal resonator is called crystal oscillator for short, which is a piezoelectric device capable of mutually converting mechanical energy and electric energy, and the energy conversion occurs at a resonance frequency point. The crystal oscillator belongs to a passive device, and the crystal oscillator can generate oscillation by matching a crystal oscillator driving circuit in the circuit. The crystal oscillator has extremely high frequency stability and is widely applied to the field of electronic communication.

In the related art, a crystal oscillator circuit adopts a classical Pierce oscillator structure, and a feedback resistor is connected in parallel with an inverter in an internal mode, so that the inverter is in a linear region and is used as an amplifier. However, the gain of the inverter affects the start-up time, and the larger the gain, the shorter the start-up time, so that the power consumption has to be increased in order to obtain a shorter start-up time of the crystal oscillator. The crystal oscillator circuit is not fully integrated in the circuit due to the fact that the external crystal oscillator is matched with the internal driving circuit, and therefore unstable factors exist when the circuit works normally, for example, the crystal oscillator is detached due to impact on the circuit, and poor contact is caused when the welding spot is unstable. The related art cannot monitor the working condition of the crystal oscillator in real time, and cannot ensure the stable operation of the circuit.

Disclosure of Invention

The embodiment of the application provides a low-power consumption crystal oscillator driving circuit with a self-checking function, which solves the problems of long starting time, high power consumption and instability of a crystal oscillator. The crystal oscillator driving circuit is connected to an external crystal oscillator circuit through two multiplexing ports; the crystal oscillator driving circuit comprises a variable gain driving module, a shaping module and a frequency self-checking module;

the oscillation input OSCI end and the oscillation output OSCO end of the variable gain driving module are connected in parallel with the crystal oscillator module and are used for controlling the crystal oscillator module to start oscillation and adjusting driving gain according to a gain feedback signal of the frequency self-checking module;

the shaping module is connected in parallel with the OSCI end and the OSCO end and is used for converting the OSCI signal and the OSCO signal of the variable gain driving module from sine wave signals to square wave signals and outputting the square wave signals;

the frequency self-checking module is connected with the output end of the shaping module and is used for detecting the frequency of the square wave signal output by the shaping module, outputting a state signal of the crystal oscillator according to the actual measurement frequency and the preset frequency, and updating the gain feedback signal.

Specifically, the variable gain driving module comprises an amplifier module and a feedback resistor connected in parallel with the input end and the output end; the amplifier module is used for providing oscillation starting energy for the crystal oscillator circuit, and a feedback channel is formed between the feedback resistor and the crystal oscillator module to determine the oscillation frequency.

Specifically, the amplifier module is a common source amplifier taking a current source as a load, and comprises at least two current sources and an NMOS tube N0;

the outputs of the at least two current sources are commonly connected with the source electrode of N0, and the OSCO end of the amplifier module is led out from the source electrode; a controllable switch is arranged on a first current source I1 in the current sources, and the controllable switch and a second current source I2 are connected to the source electrode of the NMOS tube together;

the controllable switch is connected to the frequency self-checking module, and is controlled to be opened or closed according to the received gain feedback signal, and the grid input end of N0 is led out as the OSCI end of the amplifier module.

Specifically, the shaping module comprises a signal comparator, a first schmitt trigger and a first inverter; the output of the signal comparator is cascaded with the first schmitt trigger, and the first inverter is cascaded with the output end of the first schmitt trigger and outputs a converted square wave signal;

the signal comparator is of a common-source common-gate current mirror structure and comprises PMOS (P-channel metal oxide semiconductor) tubes P1 and P2 which are connected in a common-gate mode, NMOS (N-channel metal oxide semiconductor) tubes N1 and N2 which are connected in a common-source mode, a grid electrode of the P1 is connected with a drain electrode of the N1, a source electrode of the P2 is connected with a drain electrode of the N2, and a conversion level signal is output;

the common source output of the NMOS tube is grounded through a third current source I3; the gate of N1 is connected with the OSCI signal, and the gate of N2 is connected with the OSCO signal.

Specifically, when the OSCI signal voltage is greater than the OSCO signal voltage, N2 is cut off, and the output conversion level signal is a high level signal; when the OSCI signal voltage is smaller than the OSCO signal voltage, N1, P1 and P2 are turned off, and the output transition level signal is a low level signal.

Specifically, the first schmitt trigger and the first inverter perform processing shaping based on an input conversion level signal and output a converted square wave signal; when the level signal is converted into a high level signal, the square wave signal is high level; when the transition level signal is a low level signal, the square wave signal is low level.

Specifically, when the square wave signal frequency input into the frequency self-checking module is larger than the set frequency, outputting a crystal oscillator abnormal state signal; when the square wave signal frequency is smaller than the set frequency, outputting a crystal oscillator normal state signal;

when the frequency self-checking module outputs a crystal oscillator normal state signal, a first gain feedback signal for reducing driving gain is generated and fed back to the variable gain driving module; when the frequency self-checking module outputs the abnormal state signal of the crystal oscillator, a second gain feedback signal for increasing the gain is generated and fed back to the variable gain driving module.

Specifically, the frequency self-checking module comprises a first detection branch, a second detection branch and a state detection branch which are connected in parallel;

the first detection branch comprises an NMOS tube N2 and a PMOS tube P2 which are connected in a common-gate and common-source mode, square wave signals are input into the common-gate, the common-source output is connected with a second Schmitt trigger, and the output of the second Schmitt trigger is connected with a second inverter; the drain electrode of the P2 is connected with an input power supply VDD, and the drain electrode of the N2 is grounded through a fourth current source I4;

the second detection branch comprises an NMOS tube N3 and a PMOS tube P3 which are connected in a common-gate and common-source mode, square wave signals are input into the common-gate, the common-source output is connected with a third Schmitt trigger, and the output of the third Schmitt trigger is connected with a third inverter; the drain of P3 connects the input power supply VDD and the drains of the cascaded fifth current sources I5, N3 to ground.

Specifically, the outputs of the second inverter and the third inverter are connected to the state detection branch.

Specifically, the state detection branch circuit comprises a NAND gate, a fourth inverter and a first AND gate which are sequentially cascaded; the outputs of the second inverter and the third inverter are connected with the input of the first NAND gate, and the first NAND gate outputs a state signal of the crystal oscillator; and the input of the first AND gate is respectively connected with the fourth reverse output and the square wave signal output of the shaping module.

The beneficial effects that technical scheme that this application embodiment provided include at least: when the crystal oscillator frequency is detected to be too low, the driving capability of the variable gain driving module is increased, the crystal oscillator is started by using larger driving current, and the starting time is shortened;

when the frequency is detected to be normal, the driving capability of the variable gain driving module is reduced, the normal vibration of the crystal oscillator is ensured, and the power consumption of the whole system is reduced;

when the currently detected crystal oscillator frequency is larger than a preset value, the crystal oscillator works normally, and when the currently detected crystal oscillator frequency is smaller than the preset value, a state signal ERROR of the crystal oscillator frequency ERROR is output, the output of the CLKOUT is stopped, and the disturbance of a digital circuit at the back is prevented from being caused by an ERROR waveform;

and whether the clock source can be cut to the crystal oscillator or whether the clock source is to be cut to other clock sources from the crystal oscillator is judged through detecting the ERROR signal, so that the stability of the whole system is improved.

Drawings

FIG. 1 is a classical Pierce oscillator configuration

FIG. 2 is a low power consumption crystal oscillator driving circuit with self-checking function provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a variable gain driving module according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the structure of an amplifier module provided herein;

fig. 5 is a schematic structural diagram of a shaping module according to an embodiment of the present application;

FIG. 6 is a graph of OSCI-OSCO versus output CK 1;

FIG. 7 is a waveform diagram of obtaining a CK1 signal from sampled OSCI and OSCO signals;

fig. 8 is a schematic structural diagram of a frequency self-checking module according to an embodiment of the present application;

FIG. 9 is a schematic diagram of the configuration of the state detection leg after adding a TFF trigger;

FIG. 10 is a timing diagram of each point bit recorded by using a low power consumption crystal oscillator drive circuit with self-checking function.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

As shown in fig. 1, the classical Pierce oscillator structure adopts a feedback resistor RF in parallel with an inverter INV in the driving circuit part, so that the inverter is in a linear region and is used as an amplifier. However, the gain of the inverter affects the start-up time of the crystal oscillator module (the gain is inversely proportional to the start-up time of the crystal oscillator), and setting a larger gain must achieve fast start-up at the expense of system power consumption. In addition, the crystal oscillator circuit is not fully integrated in the circuit due to the fact that the external crystal oscillator is matched with the internal driving circuit, and therefore unstable factors exist when the circuit works normally, such as crystal oscillator desoldering caused by impact of the circuit, poor contact caused by unstable welding points during working and the like. The related art cannot monitor the working condition of the crystal oscillator in real time.

In view of the above problems, referring to fig. 2, the low power consumption crystal oscillator driving circuit with self-checking function provided in the present application is connected to an external crystal oscillator circuit through two multiplexing ports (port 1 and port 2). C (C) _L1 And C _L2 Is an external load capacitor, which is connected to both ends of the crystal oscillator module, and then is connected with the driving circuit together with the crystal oscillator module through the port 1 and the port 2. The built-in crystal oscillator driving circuit comprises a variable gain driving module, a shaping module and a frequency self-checking module. The OSCI end and the OSCO end of the variable gain driving module are connected with the crystal oscillator module in parallel through multiplexing ports and are used for exciting and controlling the crystal oscillator module to start oscillation and adjusting driving gain according to a gain feedback signal of the frequency self-checking module.

The two sampling ends of the shaping module are connected in parallel with the OSCI end and the OSCO end of the variable gain driving module, and are used for sampling the OSCI signal and the OSCO signal of the variable gain driving module and converting the OSCI signal and the OSCO signal into square wave signals from sine wave signals to be output.

The frequency self-checking module is connected with the output end of the shaping module and is used for detecting the frequency of the square wave signal output by the shaping module, outputting a state signal of the crystal oscillator according to the actual measurement frequency and the preset frequency, and updating the gain feedback signal. The status signal is used for indicating a specific working state of the crystal oscillator module, such as too low frequency, too high frequency or crystal oscillator damage. The gain feedback signal acts on the variable gain driving module reversely and is used for changing the driving gain and realizing the function of self-adaptive adjustment.

Referring to fig. 3, a schematic structure diagram of a variable gain driving module provided in the present application includes an amplifier module and a feedback resistor RF connected in parallel to input (OSCI) and output (OSCO) ends of the amplifier module. The amplifier module is used for providing oscillation starting energy for the crystal oscillator closed-loop circuit system, and exciting and maintaining the crystal oscillator module to start oscillation, and the formula is as follows:

A(f)＝|A(f)|*e ^jfα(f)

and a feedback channel is formed between the feedback resistor RF and the crystal oscillator module and is used for determining the oscillation frequency of the crystal oscillator, and the formula is as follows:

B(f)＝|B(f)|*e ^jfβ(f)

in order to meet the barkhausen criterion, then the closed loop gain should be greater than 1 and the total phase shift 360 °, from which it is possible to obtain:

|a (f) |b (f) |gtoreq 1, and α (f) +β (f) =2pi

It can thus be determined that the open loop gain of the amplifier module should be much greater than 1 and that the time to reach settling depends on the magnitude of this open loop gain.

Fig. 4 is a schematic structural diagram of an amplifier module provided in the present application, and in one possible implementation, the amplifier module adopts a common source amplifier structure using current sources as loads, and the common source amplifier structure includes at least two current sources and an NMOS tube N0. The outputs of at least two current sources (illustrated in fig. 4 as current sources I1 and I2) are commonly connected to the source of N0 and lead out of the OSCO terminal of the amplifier module at the source. A controllable switch S1 is arranged on a first current source I1 in the current sources, and the controllable switch S1 and a second current source I2 are connected to the source electrode of the NMOS tube together. The controllable switch S1 is connected to the gain feedback signal output of the frequency self-checking module, and is controlled to be opened or closed according to the received gain feedback signal, and the grid input end of N0 is led out as the OSCI end of the amplifier module.

When the controllable switch s1=1, the switch is closed, the current i=i1+i2;

when the controllable switch s1=0, the switch is opened, and the current i=i2;

transconductance of a semiconductor device

Gain A _V ＝g _m ×R _o The method comprises the steps of carrying out a first treatment on the surface of the Where U is carrier mobility, cox is the unit gate capacitance size, and W and L are the width and length of the MOS.

It can be seen that the larger the current I, the larger the transconductance of the op-amp, and the larger the gain. So when s1=1, both gain and power consumption are large, the power consumption is equal to VDD (i1+i2); when s1=0, both gain and power consumption are small, equal to vdd×i2.

The first current source I1 and the second current source I2 may be provided by a reference circuit outside the module, and may be generated by a module similar to Bandgap, and the detailed description thereof will not be repeated in this application. Moreover, the present application shows only one possible form of variable gain drive module, and NMOS transistor N0 may be replaced by a current source.

Fig. 5 is a schematic structural diagram of a shaping module according to an embodiment of the present application, where the shaping module includes a signal comparator, a first schmitt trigger, and a first inverter. The output of the signal comparator is cascaded with a first schmitt trigger, and the first inverter is cascaded with the output end of the first schmitt trigger and outputs a converted square wave signal.

The signal comparator is of a common-source common-gate current mirror structure and comprises PMOS (P-channel metal oxide semiconductor) tubes P1 and P2 which are connected in a common-gate mode, NMOS (N-channel metal oxide semiconductor) tubes N1 and N2 which are connected in a common-source mode, a grid electrode of the P1 is connected with a drain electrode of the N1, a source electrode of the P2 is connected with a drain electrode of the N2, and a conversion level signal is output. The current mirror structure can convert high-level large-voltage signals into low-level small-voltage signals, and then the signals are converted through the Schmitt trigger and the inverter, so that the power consumption of the whole system is reduced.

The common source output of the NMOS transistor is grounded through a third current source I3 (provided externally). The gate of N1 is connected to the sampled OSCI signal and the gate of N2 is connected to the sampled OSCO signal. Because P1 and P2 are two PMOS tubes with the same size, when the OSCI signal voltage is the same as the OSCO signal voltage, V _GSP1 ＝V _GSP2 At this time, P1 and P2 are in the saturation region, and the currents flowing through the two gate inputs of OSCI and OSCO are equal, and are also in the saturation region, I _DSN1 ＝I _DSN2 =0.5×i3. I.e. both left and right paths are split into a current of 0.5 i3.

When the OSCI signal voltage is larger than the OSCO signal voltage, N2 is cut off, P2 enters a deep linear region at the moment, vout outputs high level, and after being processed and shaped by a first Schmitt trigger and a first inverter, a conversion level signal (square wave signal) output by CK1 is high level (VDD); when OSCI signal voltage is smaller than OSCI signal voltage, N1, P1 and P2 are cut off, no current flows out through P2, so that Vout outputs a low level, and after SMT and INV processing shaping, a transition level signal (square wave signal) output by CK1 is a low level (GND). Referring to FIG. 6, a graph of OSCI-OSCO versus output CK1 is shown. Fig. 7 is a waveform diagram of obtaining a CK1 signal from sampled OSCI and OSCO signals.

It should be noted that the signal comparator structure is not limited to the above-mentioned current mirror structure, and may be implemented in the form of a source follower, a schmitt trigger, an inverter, etc., and the embodiment of the present application is not limited thereto.

The frequency self-checking module is mainly used for detecting the working state of the crystal oscillator module in real time and reminding and self-correcting when the crystal oscillator module is abnormal. Therefore, when the square wave signal frequency of the input frequency self-checking module is larger than the set frequency, the module outputs a crystal oscillator abnormal state signal; when the square wave signal frequency is smaller than the set frequency, the module outputs a crystal oscillator normal state signal.

When the frequency self-checking module detects that the crystal oscillator frequency is normal, the driving gain of the variable gain driving module can be properly reduced, normal oscillation is ensured, and the power consumption of the module is reduced. Specifically, a first gain feedback signal for reducing the driving gain is generated and fed back to the variable gain driving module. When the frequency self-checking module detects that the crystal oscillator frequency is too low, a second gain feedback signal for increasing the gain is generated and fed back to the variable gain driving module, so that the driving gain of the variable gain driving module is increased, the crystal oscillator module is started by using larger driving current, and the starting time of the crystal oscillator is shortened.

The crystal oscillator state signal output is represented by an ERROR signal, and when error=0, the crystal oscillator driving module works normally; when error=1, this indicates that the crystal oscillator driving module works abnormally. In addition, the frequency self-checking module is also provided with a CLKOUT output which represents the converted square wave signal. When the frequency of CK1 is greater than the set frequency, CLKOUT is output CK1, at which time error=0; when the frequency of CK1 is smaller than the set frequency, CLKOUT outputs 0 (no waveform diagram is output), error=1.

Referring specifically to fig. 8, a schematic structural diagram of a frequency self-checking module according to an embodiment of the present application is provided. The module comprises a first detection branch, a second detection branch and a state detection branch which are connected in parallel.

The first detection branch circuit comprises an NMOS tube N2 and a PMOS tube P2 which are connected in a common-gate and common-source mode, square wave signals CK1 are input into the common-gate, a common-source output V1 is connected with a second Schmitt trigger, and an output V3 of the second Schmitt trigger is connected with a second inverter. The drain electrode of P2 is connected with the input power supply VDD, and the drain electrode of N2 is grounded through a fourth current source I4.

The second detection branch circuit comprises an NMOS tube N3 and a PMOS tube P3 which are connected in a common-gate and common-source mode, square wave signals CK1 are input into the common-gate, a common-source output V2 is connected with a third Schmitt trigger, and an output V4 of the third Schmitt trigger is connected with a third inverter. The drain of P3 connects the input power supply VDD and the drains of the cascaded fifth current sources I5, N3 to ground.

The outputs of the second inverter and the third inverter are connected with a state detection branch, and the state detection branch comprises a NAND gate, a fourth inverter and a first AND gate which are sequentially cascaded. The outputs of the second inverter and the third inverter are connected to the input of the first NAND gate. The first NAND gate output V5 is a status signal (ERROR signal) representing the crystal oscillator. The input of the first AND gate is respectively connected with the output of the fourth reverse direction and the square wave signal output CK1 of the shaping module.

When ck1=gnd (low level), P2 and P3 are on, and N2 and N3 are off. At this time v1=vdd, V2 rises from 0, and the rising speed depends on the ground capacitance C2 and the current I5.

When CK1 = GND is long enough, the voltage of V2 rises above the trip point of SMT, then V4 will output 0 (low) at this time, V5 will output 0, reset the T flip-flop, Q outputs 0 when the T flip-flop is reset, ERROR = 1, indicating that CK1 is wrong in frequency, and CLKOUT will be pulled to 0 at this time.

When ck1=vdd (high level), P1 and P2 are turned off, and N1 and N2 are turned on. V2=gnd at this time, V1 decreases from VDD, and the rate of decrease depends on the ground capacitance C1 and the magnitude of the current I4.

When CK1 = VDD is long enough, then V1 will be below the SMT toggle point, then V3 will output 1 (high), V5 will output 0 (low), then ERROR = 1, indicating that CK1 is wrong in frequency, and CLKOUT will be pulled to 0.

In the above embodiment, the detection frequency of CK1 is set by configuring the inversion points of I4, I5, C1, C2 and SMT, and the V1 and V2 signals are processed using SMT instead of INV, because the hysteresis function of SMT can enhance the anti-interference capability, and prevent the error from being caused by noise and burr errors.

By way of example, setting the frequency of the crystal oscillator to Fosc, the duty cycle requirement to be 40% < duty cycle <60%, then it is possible to obtain:

high level time

Low level time

V _smt Is the switching voltage of the schmitt trigger, substituted by +.>

Obtaining F _OSC The values are as follows:

similar calculation

Substituted into->

Obtaining F _OSC The values are as follows:

assuming that the crystal oscillator frequency is 1MHz, the flip point of SMT is designed to be 0.5 x VDD, the working voltage is 5V, and T can be obtained based on the above _{High height} <600ns and T _{Low and low} <600ns, substituting and calculating to obtain the size of each resistance value: c1 =c2=0.24 pf, i4=i5=1ua. If and only if T is satisfied _{High height} <600ns and T _{Low and low} <600ns, ERROR will output 0 and clkout will output CK1. When either condition is not met, error=1, indicating that the frequency is in ERROR at this time, CLKOUT outputs 0.

In other embodiments, to prevent the output disturbance of CLKOUT caused by the sudden rise and fall of the crystal oscillator frequency, several TFF triggers are added to the frequency self-checking module as a warm up delay time. Fig. 9 is a schematic diagram of a structure after a state detection branch is added into a TFF flip-flop, the outputs of the first and second detection branches are connected with an and gate, the output of the and gate is respectively input with a plurality of TFF flip-flops in cascade, V6 of the output of the flip-flop outputs an ERROR signal through an inverter, the V6 signal is output again through the inverter, the output of the and gate CK1 signal is output as two outputs of a second nand gate, and the output of the second nand gate is used as the clock input of the first cascade flip-flop.

Based on the above circuit configuration, if the number of configuration flip-flops is n, then when the frequency satisfies the condition, it is necessary to count 2 again ⁿ After a period of oscillation, the ERROR can only change from 1 to 0, and as soon as the frequency is below the preset value, the ERROR will change to 1. This 2 ⁿ The oscillation period is called the arm up time. The setting of the arm up time can increase the stability of the output signal of the system.

Stage T1: CK1 (square wave) frequency is normal, V1 is always higher than SMT flip point, V2 is always lower than SMT flip point, v3=0, v4=1. V5=1, error=0, clkout normally outputs the waveform of CK1 at this time.

Stage T2: CK1 frequency is abnormal, high level time is too long, at this time V1 falls below SMT turning point, V2 is below SMT turning point, v3=1, v4=1, V5 outputs 0, at this time ERROR immediately becomes 1, clkout outputs 0.

Stage T3: CK1 frequency returns to normal, V1 is always above SMT flip point, V2 is always below SMT flip point, v3=0, v4=1. V5=1 at this time, error is now in the arm up state, still equal to 1, clkout output 0.

Stage T4: the normal frequency time of CK1 exceeds the duration of the arm up, the arm up time is ended, ERROR is changed from 1 to 0, and CK1 is output by CLKOUT.

Stage T5: CK1 frequency is abnormal, low level time is too long, at this time V1 is always higher than SMT turning point, V2 rises above SMT turning point, V3 outputs 1, V4 outputs 1, V5 outputs 0, at this time ERROR immediately becomes 1, clkout outputs 0.

Stage T6: CK1 frequency returns to normal, V1 is always above SMT flip point, V2 is always below SMT flip point, v3=0, v4=1. V5=1 at this time, error is now in the arm up state, still equal to 1, clkout output 0.

And in the T7 stage, the normal frequency time of CK1 exceeds the norm up time, the norm up time is ended, ERROR is changed from 1 to 0, and CK1 is output by CLKOUT.

Based on the above working principle, during the process of starting the circuit crystal oscillator module, when the crystal oscillator frequency is detected to be too low during starting, error=1 is generated, a second gain feedback signal for increasing gain is generated based on the ERROR signal and acts on the controllable switch S1, and the first current source I1 is conducted by the switch closed based on the second gain feedback signal by the S1, and the driving current i=i1+i2 at the moment accelerates starting and shortens the crystal oscillator stabilizing time. When the crystal oscillator is started and works stably, the error=0, a first gain feedback signal for reducing the gain is generated based on the ERROR signal, and S1 is disconnected, so that the driving current I=I2 is reduced, and the overall power consumption of the circuit is reduced.

The foregoing describes preferred embodiments of the present invention; it is to be understood that the invention is not limited to the specific embodiments described above, wherein devices and structures not described in detail are to be understood as being implemented in a manner common in the art; any person skilled in the art will make many possible variations and modifications, or adaptations to equivalent embodiments without departing from the technical solution of the present invention, which do not affect the essential content of the present invention; therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. The low-power consumption crystal oscillator driving circuit with the self-checking function is characterized in that the crystal oscillator driving circuit is connected to an external crystal oscillator circuit through two multiplexing ports; the crystal oscillator driving circuit comprises a variable gain driving module, a shaping module and a frequency self-checking module;

2. The crystal oscillator driving circuit with self-checking function according to claim 1, wherein the variable gain driving module comprises an amplifier module and a feedback resistor connected in parallel with an input end and an output end; the amplifier module is used for providing oscillation starting energy for the crystal oscillator circuit, and a feedback channel is formed between the feedback resistor and the crystal oscillator module to determine the oscillation frequency.

3. The self-checking low power consumption crystal oscillator driving circuit according to claim 2, wherein the amplifier module is a common source amplifier using current sources as loads, and comprises at least two current sources and an NMOS tube N0;

4. The self-checking function low power consumption crystal oscillator driving circuit according to claim 1, wherein the shaping module comprises a signal comparator, a first schmitt trigger and a first inverter; the output of the signal comparator is cascaded with the first schmitt trigger, and the first inverter is cascaded with the output end of the first schmitt trigger and outputs a converted square wave signal;

5. The crystal oscillator driving circuit with self-checking function according to claim 4, wherein when OSCI signal voltage is greater than OSCO signal voltage, N2 is cut off, and the output transition level signal is a high level signal; when the OSCI signal voltage is smaller than the OSCO signal voltage, N1, P1 and P2 are turned off, and the output transition level signal is a low level signal.

6. The self-test low power consumption crystal oscillator driving circuit according to claim 5, wherein the first schmitt trigger and the first inverter perform processing shaping based on the input conversion level signal and output a converted square wave signal; when the level signal is converted into a high level signal, the square wave signal is high level; when the transition level signal is a low level signal, the square wave signal is low level.

7. The self-test function-equipped low power consumption crystal oscillator driving circuit according to claim 1, wherein when the square wave signal frequency inputted into the frequency self-test module is greater than a set frequency, outputting a crystal oscillator abnormal state signal; when the square wave signal frequency is smaller than the set frequency, outputting a crystal oscillator normal state signal;

8. The crystal oscillator driving circuit with self-checking function according to claim 7, wherein the frequency self-checking module comprises a first detection branch, a second detection branch and a state detection branch which are connected in parallel;

9. The self-test low power consumption crystal oscillator driving circuit according to claim 8, wherein the outputs of the second inverter and the third inverter are connected to the state detection branch.

10. The self-checking function of claim 9, wherein the state detection branch comprises a nand gate, a fourth inverter and a first and gate in cascade; the outputs of the second inverter and the third inverter are connected with the input of the first NAND gate, and the first NAND gate outputs a state signal of the crystal oscillator; and the input of the first AND gate is respectively connected with the fourth reverse output and the square wave signal output of the shaping module.