CN116314234B - Manufacturing method of semiconductor device and CMOS image sensor - Google Patents

Abstract

The present application provides a manufacturing method of a semiconductor device and a CMOS image sensor. The method includes: providing a base, the base includes a substrate, a first device, a second device, a first barrier layer and a dielectric layer, and the first barrier layer is located on the second On the exposed surface of the second device, the dielectric layer is located on the exposed surface of the first device, the substrate and the first barrier layer; part of the dielectric layer is removed to form the first groove and the second groove in the dielectric layer, the second A trench exposes the first device, and a second trench exposes the first barrier layer; forming a protection structure covering the first trench, and then removing the exposed first barrier layer through the second trench, so that the second device Partially exposed; the protective structure is removed by etching, and the substrate from which the protective structure is removed is subjected to post-etching treatment to obtain a semiconductor device. The present application solves the problem of damaging metal silicide devices during the process of forming contact holes of metal silicide devices and non-metal silicide devices.

Description

Manufacturing method of semiconductor device and CMOS image sensor

technical field

The present application relates to the technical field of semiconductors, and in particular, to a manufacturing method of a semiconductor device and a CMOS image sensor.

Background technique

There are two types of areas in 55CIS (55nm CMOS image sensor), which are Salicide area (self-aligned silicide area) and Non-Salicide area (non-self-aligned silicide area). The metal silicide device has one more barrier layer than the metal silicide device on the Salicide area, so in the process of forming the contact hole through the metal silicide device and the non-metal silicide device, the contact hole of the metal silicide device will be caused Excessive engraving will damage the metal silicide device.

The above information disclosed in the Background section is only to enhance the understanding of the background of the technology described herein, therefore, the Background may contain certain information which is not formed in the country for those skilled in the art. known prior art.

Contents of the invention

The main purpose of the present application is to provide a manufacturing method of a semiconductor device and a CMOS image sensor to solve the problem in the prior art that metal silicide devices are damaged during the process of forming contact holes of metal silicide devices and non-metal silicide devices.

According to an aspect of an embodiment of the present invention, a semiconductor manufacturing method is provided, including: providing a base, the base includes a substrate, a first device, a second device, a first barrier layer, and a dielectric layer, wherein the The first device and the second device are disposed on the substrate at intervals, the first device is a device obtained by a salicide process, and the second device is not processed by a salicide process processing the obtained device, the first barrier layer is located on the exposed surface of the second device, and the dielectric layer is located on the exposed surfaces of the first device, the substrate and the first barrier layer; removing Part of the dielectric layer to form a first trench and a second trench in the dielectric layer, wherein the first trench exposes part of the first device, and the second trench exposing a portion of the first barrier layer; forming a protection structure covering the first trench, and then removing the exposed first barrier layer through the second trench, so that a portion of the second device Exposing: removing the protective structure by etching, and performing post-etching treatment on the substrate from which the protective structure has been removed, to obtain a semiconductor device.

Optionally, providing a substrate includes: providing the substrate, the substrate including a first device region and a second device region arranged at intervals; forming a first gate structure located on the first device region, located on the The first source region and the first drain region on both sides of the first gate structure, and the second gate structure on the second device region, and the second gate structure on both sides of the second gate structure The second source region and the second drain region, the second gate structure, the second source region and the second drain region form the second device; forming the first barrier layer on the surface, and treating the substrate formed with the first barrier layer by a salicide process, so that the first source region is far away from the surface of the substrate forming a first silicide layer, forming a second silicide layer on the surface of the first drain region away from the substrate, and forming a third silicide layer on the surface of the first gate structure away from the substrate material layer, the first gate structure, the first source region, the first drain region, the first silicide layer, the second silicide layer and the third silicide layer Constructing the first device; stacking a second barrier layer and the dielectric layer sequentially on the exposed surfaces of the substrate, the first device and the first barrier layer to obtain the substrate.

Optionally, the first barrier layer that only covers the second source region is a first barrier structure, the first barrier layer that only covers the second gate structure is a second barrier structure, and only covers The first barrier layer of the second drain region is a third barrier structure, removing part of the dielectric layer to form a first trench and a second trench in the dielectric layer, including: A patterned first mask layer is formed on the surface of the dielectric layer away from the first barrier layer; using the patterned first mask layer as a mask, the dielectric layer and the first barrier layer are sequentially etched. two barrier layers, to form a first sub-trench, a second sub-trench, a third sub-trench, a fourth sub-trench, a fifth sub-trench and A sixth sub-trench, wherein the first sub-trench exposes a part of the surface of the first silicide layer, the second sub-trench exposes a part of the surface of the third silicide layer, the The third sub-trench exposes part of the surface of the second silicide layer, the fourth sub-trench exposes part of the first barrier structure, and the fifth sub-trench exposes the second barrier structure. part of the third barrier structure is exposed, the sixth sub-trench exposes part of the third barrier structure, the first sub-trench, the second sub-trench and the third sub-trench constitute the first trench, the fourth sub-trench, the fifth sub-trench and the sixth sub-trench constitute the second trench; the patterned first mask layer is removed.

Optionally, forming a protection structure covering the first trench, and then removing the exposed first barrier layer through the second trench, so that part of the second device is exposed, includes: The first sub-trench, the second sub-trench, and the third sub-trench are filled with photoresist to form the protection structure; along the fourth sub-trench, the fifth sub-trench and the sixth sub-trench, etching the substrate on which the protective structure is formed, to remove the exposed first barrier layer, so that the second source region, the second drain A part of the surface of the region and the second gate structure is exposed.

Optionally, forming a first gate structure on the first device region and forming a second gate structure on the second device region includes: sequentially stacking a gate oxide layer on the substrate and a polysilicon layer; forming a patterned second mask layer on the surface of the polysilicon layer away from the gate oxide layer; using the patterned second mask layer as a mask, sequentially etching the polysilicon layer and The gate oxide layer is used to form a first gate portion and a first gate oxide portion on the first device region, and to form a second gate portion and a second gate oxide portion on the second device region, so The first gate portion and the first gate oxide portion constitute the first gate structure, and the second gate portion and the second gate oxide portion constitute the second gate structure; patterning is removed The second mask layer.

Optionally, etching and removing the protective structure includes: etching and removing the protective structure by using a plasma etching method.

Optionally, after the semiconductor device is obtained, the method further includes: respectively filling the first trench and the third trench with a conductive material, and the first trench after filling the conductive material is formed A first contact hole, the second contact hole is formed by filling the second trench with the conductive material, and the third trench is the second trench after the exposed first barrier layer is removed.

Optionally, the material of the first barrier layer includes TEOS oxide, and the material of the dielectric layer includes silicon oxide.

Optionally, the material of the second barrier layer includes silicon nitride.

According to another aspect of the embodiments of the present invention, there is also provided a CMOS image sensor, including: a semiconductor device manufactured by any one of the manufacturing methods described above.

In the embodiment of the present invention, since the second device has one more layer of the first barrier layer than the first device, the application first removes part of the dielectric layer in the process of forming the contact hole penetrating through the first device and the second device , forming a first trench exposing the first device and a second trench exposing the first barrier layer, filling the first trench with a protective structure and then continuing to remove the exposed first barrier layer, so that the second device is exposed, engraved In the process of etching the first barrier layer, the protection structure protects the first device from damage, avoiding the problem of excessive damage to the first device in the process of removing the first barrier layer and exposing the second device, while ensuring the protection of the first device Both the semiconductor device and the second device can be exposed, which facilitates successful subsequent formation of contact holes and ensures a high manufacturing yield of the semiconductor device. Moreover, the present application performs post-etching treatment after etching and removing the protective structure, which can remove the thin oxide layer formed on the exposed surface of the second device during the removal process, thereby ensuring the contact hole resistance of the entire semiconductor device lower.

Description of drawings

The accompanying drawings constituting a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application, and do not constitute an improper limitation of the present application. In the attached picture:

FIG. 1 shows a schematic flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application;

2 to 5 respectively show the structural schematic diagrams obtained after each process step of the manufacturing method of the semiconductor device according to the embodiment of the present application;

FIG. 6 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

FIG. 7 shows a schematic structural diagram of a semiconductor device according to another embodiment of the present application.

Wherein, the above-mentioned accompanying drawings include the following reference signs:

10. Substrate; 11. First device; 12. Second device; 13. First barrier layer; 14. Dielectric layer; 15. First gate part; 16. Third silicide layer; 17. Second gate 19, the first source region; 20, the first drain region; 21, the second source region; 22, the second drain region; 23, the first silicide layer; 24, the second silicide layer ; 25, the second barrier layer; 26, the first trench; 27, the second trench; 28, the first mask layer; 29, the first sub-trench; 30, the second sub-trench; 31, the third Sub-groove; 32. Fourth sub-groove; 33. Fifth sub-groove; 34. Sixth sub-groove; 35. Carbon coating; 36. Dielectric anti-reflection coating; 37. Bottom anti-reflection coating ; 38, photoresist layer; 39, protective structure; 40, the seventh sub-trench; 41, the eighth sub-trench; 42, the ninth sub-trench; 43, the third trench; 44, the first contact hole 45. The second contact hole; 46. The dielectric structure; 47. The first gate oxide portion; 48. The second gate oxide portion; 49. The isolation structure; 50. The first sidewall; 51. The second sidewall.

Detailed ways

It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

It should be noted that the terms "first" and "second" in the description and claims of the present application and the drawings are used to distinguish similar objects, and not necessarily used to describe a specific order or sequence . It should be understood that the data so used may be interchanged under appropriate circumstances for the embodiments of the application described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the another element through a third element.

As mentioned in the background technology, in the prior art, the process of forming contact holes of metal silicide devices and non-metal silicide devices damages metal silicide devices. In order to solve the problem, a typical implementation of the present application Provided are a manufacturing method of a semiconductor device and a CMOS image sensor.

According to an embodiment of the present application, a method for manufacturing a semiconductor device is provided.

FIG. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application. As shown in Figure 1, the method includes the following steps:

In step S101, as shown in FIG. 2 , a substrate is provided, and the substrate includes a substrate 10, a first device 11, a second device 12, a first barrier layer 13, and a dielectric layer 14, wherein the first device 11 and the The second devices 12 are disposed on the substrate 10 at intervals, the first device 11 is a device obtained by a salicide process, and the second device 12 is not processed by a salicide process. In the obtained device, the first barrier layer 13 is located on the exposed surface of the second device 12, and the dielectric layer 14 is located on the first device 11, the substrate 10 and the first barrier layer 13 on exposed surfaces;

Those skilled in the art can use any suitable process to manufacture the substrate. In order to further ensure that the manufacturing process of the substrate is relatively simple, and to further ensure that the substrate is relatively easy to obtain, according to a specific embodiment of the present application , providing a substrate, comprising: providing the substrate 10, the substrate 10 including first device regions and second device regions arranged at intervals; forming a first gate structure located on the first device 11 region, located on The first source region 19 and the first drain region 20 on both sides of the first gate structure, and the second gate structure located on the second device region, located on both sides of the second gate structure The second source region 21 and the second drain region 22 on the side, the second gate structure, the second source region 21 and the second drain region 22 form the second device 12; The first barrier layer 13 is formed on the exposed surface of the second device 12, and the substrate 10 formed with the first barrier layer 13 is processed by a salicide process, so that the first A first silicide layer 23 is formed on the surface of the source region 19 away from the substrate 10, a second silicide layer 24 is formed on the surface of the first drain region 20 away from the substrate 10, and the A third silicide layer 16 is formed on the surface of the first gate structure away from the substrate 10, the first gate structure, the first source region 19, the first drain region 20, the The first silicide layer 23, the second silicide layer 24 and the third silicide layer 16 constitute the first device 11; in the substrate 10, the first device 11 and the first The second barrier layer 25 and the dielectric layer 14 are sequentially stacked on the exposed surface of the barrier layer 13 to obtain the substrate.

In the embodiment, the first gate structure, the first source region 19 and the first drain region 20 are first formed in the first device region, and the second gate structure, the second source region and the second device region are formed in the second device region. The electrode region 21 and the second drain region 22 of the second device 12, after that, the first barrier layer 13 is formed on the exposed surface of the second device 12, and then the substrate 10 formed with the first barrier layer 13 is self-aligned Silicide process, since the second device 12 has been covered by the first barrier layer 13, a metal silicide film is only formed on the surface of the first gate structure, the first source region 19 and the first drain region 20 , to obtain the first silicide layer 23, the second silicide layer 24 and the third silicide layer 16 to form the first device 11, which can ensure that the on-resistance of the first device is smaller than that of the second device. through impedance.

It should be noted that the first device area is a Salicide area, corresponding to a peripheral area of the CMOS image sensor, and the second device area is a Non-Salicide area, corresponding to a pixel area of the CMOS image sensor. The first device is a metal silicide device, and the second device is a non-metal silicide device.

In addition, in addition to the first device region and the second device region arranged at intervals, the substrate also includes an isolation structure 49. As shown in FIG. 2, the isolation structure 49 is located between the first device region and the second device region . The isolation structure 49 may be shallow trench isolation.

In actual application, the surface of the dielectric layer 14 away from the substrate 10 is a plane.

In an embodiment of the present application, forming the first gate structure on the region of the first device 11 and forming the second gate structure on the region of the second device include: A gate oxide layer (not shown in the figure) and a polysilicon layer are sequentially stacked on it; a patterned second mask layer is formed on the surface of the polysilicon layer away from the gate oxide layer; the patterned second The mask layer is a mask, and the polysilicon layer and the gate oxide layer are sequentially etched to form the first gate oxide part 47 and the first gate part 15 on the first device region. Forming the second gate oxide portion 48 and the second gate portion 17 on the second device region; removing the patterned second mask layer, and forming the first gate oxide portion 47, the The side wall material is formed on the exposed surfaces of the first gate part 15, the second gate oxide part 48 and the second gate part 17; the side wall material is etched by anisotropic etching method, so as to First spacers 50 are formed on the sidewalls of the first gate oxide portion 47 and the first gate portion 15 , and on the sides of the second gate oxide portion 48 and the second gate portion 17 A second sidewall 51 is formed on the wall. As shown in FIG. The second gate portion 17 , the second gate oxide portion 48 and the second spacer 51 constitute the second gate structure. In the above-described embodiment, by stacking a gate oxide layer, a polysilicon layer, and a patterned second mask layer on the substrate, and then using the second mask layer as a mask, the polysilicon layer is sequentially etched. layer and the gate oxide layer, the first gate part, the second gate part, the first gate oxide part and the second gate oxide part can be formed at the same time through a photomask, and further It is ensured that the process of forming the base is relatively easy to realize, and the manufacturing cost is low.

Of course, in the process of forming the first gate structure and the second gate structure, they may also be formed by etching respectively through two photomasks.

In an actual application process, the second mask layer may be a single-layer film structure or a multi-layer film structure.

Step S102, as shown in FIG. 4 , removing part of the dielectric layer 14 to form a first trench 26 and a second trench 27 in the dielectric layer 14, wherein the first trench 26 makes A part of the first device 11 is exposed, and the second trench 27 exposes a part of the first barrier layer 13;

Specifically, the first barrier layer 13 that only covers the second source region 21 is a first barrier structure, and the first barrier layer 13 that only covers the second gate structure is a second barrier structure, The first barrier layer 13 covering only the second drain region 22 is a third barrier structure, and part of the dielectric layer 14 is removed to form the first trench 26 and the second trench 26 in the dielectric layer 14. The second groove 27 includes: as shown in FIG. 3, a patterned first mask layer 28 is formed on the surface of the dielectric layer 14 away from the first barrier layer 13; as shown in FIG. 3 and FIG. 4, Using the patterned first mask layer 28 as a mask, sequentially etch the dielectric layer 14 and the second barrier layer 25 to form a The first sub-groove 29, the second sub-groove 30, the third sub-groove 31, the fourth sub-groove 32, the fifth sub-groove 33 and the sixth sub-groove 34, wherein the first sub-groove The trench 29 exposes part of the surface of the first silicide layer 23, the second sub-trench 30 exposes a part of the surface of the third silicide layer 16, and the third sub-trench 31 exposes the Part of the surface of the second silicide layer 24 is exposed, the fourth sub-trench 32 exposes part of the first barrier structure, and the fifth sub-trench 33 exposes part of the second barrier structure, so The sixth sub-trench 34 exposes part of the third barrier structure, and the first sub-trench 29, the second sub-trench 30 and the third sub-trench 31 constitute the first trench. Groove 26, the fourth sub-trench 32, the fifth sub-trench 33 and the sixth sub-trench 34 form the second trench 27, and the remaining dielectric layer 14 forms a dielectric structure 46; The patterned first mask layer 28 is removed.

Those skilled in the art can choose any suitable material to form the first barrier layer 13, the second barrier layer 25 and the dielectric layer 14. In the embodiment of the present application, the material of the first barrier layer 13 Including TEOS oxide, the material of the dielectric layer 14 includes silicon oxide. The material of the second barrier layer 25 includes silicon nitride. Due to the high selectivity between oxide and silicon nitride and between TEOS oxide and silicon nitride, the first sub-trench, the second sub-trench, and the During the process of the third sub-trench, the fourth sub-trench, the fifth sub-trench and the sixth sub-trench, it can more accurately stop on the surface of the first device and the first barrier layer 13 surface, further avoiding the problem of over-etch damage to devices on the semiconductor.

The materials of the first silicide layer 23, the second silicide layer 24, and the third silicide layer 16 can be the same or different, and the first silicide layer 23, the second silicide layer 24, and the The materials of the third silicide layer 16 respectively include metal silicide. In the embodiment of the present application, the materials of the first silicide layer 23, the second silicide layer 24 and the third silicide layer 16 Both are nickel silicides. Certainly, the materials of the first silicide layer 23 , the second silicide layer 24 and the third silicide layer 16 are not limited to nickel silicide, and may also be other metal silicide materials.

In another embodiment, the material of the first barrier layer 13 is TEOS oxide, the material of the dielectric layer 14 is silicon oxide, and the material of the second barrier layer 25 is silicon nitride. Materials of the first gate portion 15 and the second gate portion 17 are polysilicon respectively.

The first mask layer 28 may be a single-layer film structure or a multi-layer film structure. In the embodiment of the present application, as shown in FIG. 3, the first mask layer 28 is a multi-layer film structure. They are a carbon coating 35 , a dielectric antireflection coating 36 , a bottom antireflection coating 37 and a photoresist layer 38 stacked in sequence along the direction away from the dielectric layer 14 .

Step S103, forming a protective structure 39 covering the first trench 26, and then removing the exposed first barrier layer 13 through the second trench 27, so that part of the second device 12 is exposed;

By forming a protection structure covering the first trench, the problem of over-engraving the first device during the process of removing the first barrier layer is avoided, which ensures a high manufacturing yield of the semiconductor device, and can obtain a semiconductor device with better quality .

According to yet another specific embodiment of the present application, a protective structure 39 covering the first trench 26 is formed, and then the exposed first barrier layer 13 is removed through the second trench 27, so that the The partial exposure of the second device 12 includes: as shown in FIG. 5, filling photoresist in the first sub-trench 29, the second sub-trench 30 and the third sub-trench 31 to form The protection structure 39 ; etching the substrate on which the protection structure 39 is formed along the fourth sub-trench 32 , the fifth sub-trench 33 and the sixth sub-trench 34 , so as to remove the exposed first barrier layer 13, so that the second source region 21, the second drain region 22 and part of the surface of the second gate structure are exposed, wherein, removing the exposed The fourth sub-trench 32 behind the first barrier layer 13 forms a seventh sub-trench 40, and the fifth sub-trench 33 after removing the exposed first barrier layer 13 forms an eighth sub-trench 41. The sixth sub-trench 34 after removing the exposed first barrier layer 13 forms the ninth sub-trench 42, the seventh sub-trench 40, the eighth sub-trench 41 and the ninth sub-trench The groove 42 constitutes a third trench 43 .

Specifically, as shown in FIG. 5, photoresist is filled in the first sub-trench 29, the second sub-trench 30, and the third sub-trench 31 to form the protection structure 39, including : forming a photoresist material layer on the exposed surface of the dielectric structure 46 formed with the first trench 26 and the second trench 27, and the photoresist material layer fills up the first trench Groove and the second trench, and cover the exposed surface of the dielectric structure 46; perform one of the following: in the case of the photoresist material layer being a positive resist, filling in the second trench The photoresist material layer is exposed, so that the unexposed photoresist material layer remains to form the protective structure 39; Exposing the photoresist material layer outside the photoresist material layer in the second groove, so that only the photoresist material layer in the second groove is removed, forming The protective structure 39 .

In step S104 , as shown in FIG. 5 and FIG. 6 , the protection structure 39 is etched away, and the substrate from which the protection structure 39 has been removed is subjected to post-etching treatment to obtain a semiconductor device.

In a specific embodiment, etching and removing the protective structure 39 includes: etching and removing the protective structure 39 by using a plasma etching method. In this embodiment, the protective structure 39 is etched and removed by plasma etching, which has less pollution to the semiconductor device after etching, less etching residues, and a higher etching rate.

In addition, as shown in FIG. 6, after obtaining the semiconductor device, the method further includes: as shown in FIG. 6 and FIG. 7, filling conductive material in the first trench 26 and the third trench 43 respectively , the first trench 26 filled with the conductive material forms a first contact hole 44, the second trench 27 filled with the conductive material forms a second contact hole 45, and the third trench 43 It is the second trench 27 after removing the exposed first barrier layer. By filling the first groove and the third groove with a conductive material to form a contact hole, electrical extraction of the first device and the second device is realized.

Specifically, filling conductive material in the first trench 26 and the third trench 43 respectively includes: filling the first sub-trench 29, the second sub-trench 30, the third sub-trench Sub-trench 31, the seventh sub-trench 40, the eighth sub-trench 41, the ninth sub-trench 42 and the remaining surface of the dielectric layer 14 are filled with the conductive material, so The conductive material fills the first sub-trench 29, the second sub-trench 30, the third sub-trench 31, the seventh sub-trench 40, the eighth sub-trench 41, and The ninth sub-trench 42 ; removing the conductive material covering the surface of the dielectric layer 14 .

The method for manufacturing a semiconductor device firstly provides a substrate 10, a first device 11 obtained through a salicide process, a second device 12 obtained without a salicide process, a first barrier layer 13 and the substrate of the dielectric layer 14, wherein the first device 11 and the second device 12 are spaced apart on the substrate 10, and the first barrier layer 13 is located on the exposed surface of the second device 12 On the surface, the dielectric layer 14 is located on the exposed surfaces of the first device 11, the substrate 10 and the first barrier layer 13; afterward, part of the dielectric layer 14 is removed to form a The first trench 26 in the dielectric layer 14 and exposing the first device 11 is formed, and the second trench 27 extending into the dielectric layer 14 and exposing the second device 12 is formed; The protection structure 39 of the first trench 26 is then removed through the second trench 27 to expose the first barrier layer 13; finally, the protection structure 39 is removed by etching and post-etching treatment is performed to obtain a semiconductor device. Since the second device 12 has one more layer of the first barrier layer 13 than the first device 11, in the process of forming the contact hole penetrating through the first device 11 and the second device 12 in this application, part of the dielectric layer 14 is removed first, Forming the first trench 26 exposing the first device 11 and the second trench 27 exposing the first barrier layer 13, filling the first trench 26 with a protective structure 39 and then continuing to remove the exposed first barrier layer 13, so that The second device 12 is exposed, and the protective structure 39 protects the first device 11 from damage during the process of etching the first barrier layer 13, avoiding excessive damage during the process of removing the first barrier layer 13 and exposing the second device 12 The problem of the first device 11 ensures that the first device 11 and the second device 12 can be exposed at the same time, which facilitates the subsequent successful formation of contact holes and ensures a high manufacturing yield of semiconductor devices. Moreover, the present application performs post-etching treatment after etching and removing the protective structure 39, which can remove the thin oxide layer formed on the exposed surface of the second device 12 during the removal process, thereby ensuring the contact holes of the entire semiconductor device Lower resistance.

According to another typical embodiment of the present application, there is also provided a CMOS image sensor, including: a semiconductor device fabricated by any one of the fabrication methods described above.

The CMOS image sensor includes the semiconductor device manufactured by the method described above. Since the second device 12 has one more layer of first barrier layer 13 than the first device 11, the present application is formed through the first device 11 and the first barrier layer 13. In the process of the contact hole of the second device 12, part of the dielectric layer 14 is first removed to form the first trench 26 exposing the first device 11 and the second trench 27 exposing the first barrier layer 13, and to the first trench 26 After filling the protection structure 39 in the middle, continue to remove the exposed first barrier layer 13, so that the second device 12 is exposed. During the process of etching the first barrier layer 13, the protection structure 39 protects the first device 11 from damage, avoiding Remove the first barrier layer 13 to expose the second device 12 to the problem of over-damaging the first device 11, while ensuring that both the first device 11 and the second device 12 can be exposed, which facilitates the subsequent successful formation of contact holes and ensures The production yield of the semiconductor device is high, thereby ensuring the high production yield of the CMOS image sensor. Moreover, the present application performs post-etching treatment after etching and removing the protective structure 39, which can remove the thin oxide layer formed on the exposed surface of the second device 12 during the removal process, thereby ensuring the contact holes of the entire semiconductor device The resistance value is relatively low, thereby ensuring better performance of the CMOS image sensor.

In the embodiments of the present invention, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed technical content can be realized in other ways. Wherein, the device embodiments described above are only illustrative. For example, the division of the units may be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or may be Integrate into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of units or modules may be in electrical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage media include: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes. .

From the above description, it can be seen that the embodiments described in the present application have achieved the following technical effects:

The method for manufacturing a semiconductor device described in this application firstly provides a substrate, a first device obtained through a salicide process, a second device obtained without a salicide process, and a first barrier layer. and a substrate of a dielectric layer, wherein the first device and the second device are spaced apart on the substrate, the first barrier layer is located on the exposed surface of the second device, and the dielectric layer is located on the on the exposed surfaces of the first device, the substrate, and the first barrier layer; afterward, part of the dielectric layer is removed to form a structure protruding into the dielectric layer and exposing the first device. the first trench, and forming a second trench protruding into the dielectric layer and exposing the second device; then forming a protection structure covering the first trench, and then removing the exposed part through the second trench The first barrier layer; finally etching to remove the protection structure and performing post-etching treatment to obtain a semiconductor device. Since the second device has one more layer of the first barrier layer than the first device, in the process of forming the contact hole penetrating through the first device and the second device, this application first removes part of the dielectric layer to form a barrier layer that exposes the first device. The first trench and the second trench exposing the first barrier layer, filling the first trench with a protective structure and then continuing to remove the exposed first barrier layer, so that the second device is exposed, and the process of etching the first barrier layer The protection structure described in the above protects the first device from damage, avoids the problem of excessive damage to the first device in the process of removing the first barrier layer and exposing the second device, and at the same time ensures that both the first device and the second device can be exposed , to facilitate subsequent successful formation of contact holes, ensuring a high manufacturing yield of semiconductor devices. Moreover, the present application performs post-etching treatment after etching and removing the protective structure, which can remove the thin oxide layer formed on the exposed surface of the second device during the removal process, thereby ensuring the contact hole resistance of the entire semiconductor device lower.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims (8)

1. A method of fabricating a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a substrate, a first device, a second device, a first barrier layer and a dielectric layer, the first device and the second device are arranged on the substrate at intervals, the first device is a device obtained through self-aligned silicide process treatment, the second device is a device obtained through no self-aligned silicide process treatment, the first barrier layer is positioned on the exposed surface of the second device, and the dielectric layer is positioned on the exposed surfaces of the first device, the substrate and the first barrier layer;

removing part of the dielectric layer to form a first groove and a second groove which are positioned in the dielectric layer, wherein the first groove exposes part of the first device, and the second groove exposes part of the first barrier layer;

forming a protection structure covering the first groove, and removing the exposed first barrier layer through the second groove to expose part of the second device;

etching to remove the protective structure, and performing post-etching treatment on the substrate from which the protective structure is removed to obtain a semiconductor device,

providing a substrate comprising:

providing the substrate, wherein the substrate comprises a first device region and a second device region which are arranged at intervals;

forming a first gate structure on the first device region, a first source region and a first drain region on both sides of the first gate structure, and forming a second gate structure on the second device region, a second source region and a second drain region on both sides of the second gate structure, the second source region and the second drain region forming the second device;

forming the first barrier layer on the exposed surface of the second device, and processing the substrate with the first barrier layer by adopting a self-aligned silicide process to form a first silicide layer on the surface of the first source region away from the substrate, a second silicide layer on the surface of the first drain region away from the substrate and a third silicide layer on the surface of the first gate structure away from the substrate, wherein the first gate structure, the first source region, the first drain region, the first silicide layer, the second silicide layer and the third silicide layer form the first device;

sequentially stacking a second barrier layer and the dielectric layer on the exposed surfaces of the substrate, the first device and the first barrier layer to obtain the substrate,

the first barrier layer covering only the second source region is a first barrier structure, the first barrier layer covering only the second gate structure is a second barrier structure, the first barrier layer covering only the second drain region is a third barrier structure, and a portion of the dielectric layer is removed to form a first trench and a second trench in the dielectric layer, comprising:

forming a patterned first mask layer on the surface of the dielectric layer away from the first barrier layer;

sequentially etching the dielectric layer and the second barrier layer by taking the patterned first mask layer as a mask to form a first sub-groove, a second sub-groove, a third sub-groove, a fourth sub-groove, a fifth sub-groove and a sixth sub-groove which are positioned in the dielectric layer and the second barrier layer, wherein the first sub-groove exposes part of the surface of the first silicide layer, the second sub-groove exposes part of the surface of the third silicide layer, the third sub-groove exposes part of the surface of the second silicide layer, the fourth sub-groove exposes part of the first barrier structure, the fifth sub-groove exposes part of the second barrier structure, the sixth sub-groove exposes part of the third barrier structure, and the first sub-groove, the second sub-groove and the third sub-groove form the first groove, the fourth sub-groove and the sixth sub-groove form the second groove;

and removing the patterned first mask layer.

2. The method of claim 1, wherein forming a protective structure overlying the first trench, and thereafter removing the exposed first barrier layer through the second trench to expose portions of the second device, comprises:

filling photoresist in the first sub-groove, the second sub-groove and the third sub-groove to form the protection structure;

and etching the substrate with the protective structure along the fourth sub-groove, the fifth sub-groove and the sixth sub-groove to remove the exposed first barrier layer so that part of the surfaces of the second source electrode region, the second drain electrode region and the second grid electrode structure are exposed.

3. The method of claim 1, wherein forming a first gate structure over the first device region and forming a second gate structure over the second device region comprises:

sequentially stacking a gate oxide layer and a polysilicon layer on the substrate;

forming a patterned second mask layer on the surface of the polysilicon layer far away from the gate oxide layer;

sequentially etching the polysilicon layer and the gate oxide layer by taking the patterned second mask layer as a mask to form a first gate part and a first gate oxide part on the first device region, and a second gate part and a second gate oxide part on the second device region, wherein the first gate part and the first gate oxide part form the first gate structure, and the second gate part and the second gate oxide part form the second gate structure;

and removing the patterned second mask layer.

4. A method according to any one of claims 1 to 3, wherein etching away the protective structure comprises:

and etching and removing the protective structure by adopting a plasma etching method.

5. A method according to any one of claims 1 to 3, characterized in that after obtaining the semiconductor device, the method further comprises:

and filling conductive materials in the first groove and the third groove respectively, wherein the first groove filled with the conductive materials forms a first contact hole, the second groove filled with the conductive materials forms a second contact hole, and the third groove is the second groove after the exposed first barrier layer is removed.

6. A method according to any of claims 1 to 3, wherein the material of the first barrier layer comprises TEOS oxide and the material of the dielectric layer comprises silicon oxide.

7. A method according to any of claims 1 to 3, wherein the material of the second barrier layer comprises silicon nitride.

8. A CMOS image sensor, comprising: a semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 7.