CN116306474A - Method, device, equipment and storage medium for verifying access of network on chip - Google Patents
Method, device, equipment and storage medium for verifying access of network on chip Download PDFInfo
- Publication number
- CN116306474A CN116306474A CN202310091520.7A CN202310091520A CN116306474A CN 116306474 A CN116306474 A CN 116306474A CN 202310091520 A CN202310091520 A CN 202310091520A CN 116306474 A CN116306474 A CN 116306474A
- Authority
- CN
- China
- Prior art keywords
- verification
- network
- chip
- path
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000012795 verification Methods 0.000 claims abstract description 213
- 238000012360 testing method Methods 0.000 claims abstract description 34
- 230000037361 pathway Effects 0.000 claims abstract description 22
- 238000004088 simulation Methods 0.000 claims description 31
- 238000004590 computer program Methods 0.000 claims description 16
- 230000005540 biological transmission Effects 0.000 claims description 12
- 210000001503 joint Anatomy 0.000 claims description 8
- 230000006399 behavior Effects 0.000 claims description 5
- 230000000007 visual effect Effects 0.000 abstract description 7
- 230000006870 function Effects 0.000 description 14
- 238000012545 processing Methods 0.000 description 11
- 238000004891 communication Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000011161 development Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 239000003999 initiator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The application discloses a method, a device, equipment and a storage medium for verifying a network-on-chip access, which relate to the technical field of integrated circuits and comprise the following steps: extracting architecture information of a network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information; selecting a target pathway from the verification environment through the graphical user interface and determining target pathway parameters; and running the corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip. Therefore, corresponding verification environments can be generated only by filling different architecture information files in the face of different network-on-chip, verification is performed without generating the verification environments independently for each network-on-chip, and repeated workload and verification period of a verification engineer are reduced; the visual graphical user interface is provided, so that a verification engineer can randomly select a verification passage and passage parameters, the operation is convenient, and the passage verification diversity is realized.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method, an apparatus, a device, and a storage medium for path verification of a network on chip.
Background
With the development of integrated circuits, soC (system on a chip) is increasingly moving toward large scale, high integration, high complexity, high performance, and low power consumption. In order to efficiently implement task processing, numerous IPs on the SoC propose high performance indexes such as high bandwidth, low latency, etc. for the processed data. At this time, on-chip interconnection tends to be a key to the breakthrough of the performance of the whole SoC. Nocs (Network on Chip) are used as a bus interconnect architecture for connecting multiple hosts and slaves to achieve high performance communication of the overall system. The method is highly configurable and structured, and a high-efficiency, high-flexibility and extensible solution is provided for the system by referencing some concepts of the general network. Network-on-chip solutions are now the main direction of development for SoC interconnects.
In order to meet the performance requirements of socs, networks on chip are increasingly being used. The network on chip provided by each manufacturer is used as a mature universal IP (intellectual property core), has huge self-functions and has been fully verified. Therefore, in SoC, the most important of the network-on-chip verification work is how to quickly implement the full-path verification work. The challenges faced by the path verification of the network on chip in the current SoC are: the variety of path types, where a path refers to the path that a master sees to a slave through a NoC. The variety of path types requires that the verification engineer perform different tests based on the path characteristics of each master-slave at the time of verification. However, as the number of hosts and slaves increases, and the types of protocols increase, how to ensure the completeness of the verification of each path is a problem that needs to be considered by a verification engineer. In addition, if a certain host or the characteristics of the host are changed, all the path verification related to the host needs to be changed. In the early stages of the project, a change is necessary, but this undoubtedly increases the repetitive effort of the verification engineer. Thus, the variety of via types presents a significant number of problems and challenges to the verification engineer. In the face of many different nocs, the effort of the verification engineer is definitely enormous if each should build a verification environment separately and develop test cases for verification.
In summary, how to find the universality of nocs, and how to get the verification work to be universal, and how to quickly complete the verification of multiple nocs are technical problems to be solved in the field.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, apparatus, device, and storage medium for path verification of a network on chip, which can find versatility in nocs, and which can quickly complete verification of a plurality of nocs by making verification work common. The specific scheme is as follows:
in a first aspect, the present application discloses a method for path verification of a network on chip, including:
extracting architecture information of a network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information;
selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter;
and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip.
Optionally, before extracting the architecture information of the network on chip to be verified, the method further includes:
and filling in an information file of the network-on-chip to be verified, wherein the information file comprises the number, the name, the interface protocol and the access parameters of the interface units which are in butt joint with the host and the interface units which are in butt joint with the slave.
Optionally, the extracting architecture information of the network on chip to be verified, generating a corresponding verification environment based on the architecture information, includes:
extracting architecture information of a network-on-chip to be verified to generate configuration information for configuring a verification environment;
and generating a corresponding verification environment based on the configuration information.
Optionally, the generating a corresponding verification environment based on the architecture information includes:
simulating the transmission behaviors of a host computer and a slave computer connected with the network on chip to be verified by using the verification IP core, and generating a corresponding passage to generate a corresponding verification environment; the access is used for the data transmission of the host and the slave through the network-on-chip to be verified, the access protocol and the access parameters.
Optionally, the selecting a target path from the verification environment and determining a target path parameter through a graphical user interface includes:
selecting a preset number of target paths from the verification environment through a graphical user interface, and designating corresponding path parameters and/or default random path parameters for the target paths;
the path parameters and/or the default random path parameters are determined as target path parameters.
Optionally, after the corresponding test case is operated based on the target path, the target path parameters and the service scenario, and the corresponding operation result is obtained, the method further includes:
and generating a simulation report containing the waveform file, the log file, the use case regression result and the coverage rate file according to the operation result.
Optionally, after generating the simulation report including the waveform file, the log file, the use case regression result and the coverage rate file according to the operation result, the method further includes:
judging whether the simulation result of the simulation report meets a preset simulation target, if not, executing the steps of selecting a target passage from the verification environment through a graphical user interface and determining a target passage parameter.
In a second aspect, the present application discloses a path verification apparatus of a network on chip, including:
the environment generation module is used for extracting architecture information of the network on chip to be verified and generating a corresponding verification environment based on the architecture information;
a parameter determination module for selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter;
and the path verification module is used for running the corresponding test cases based on the target path, the target path parameters and the service scene, acquiring corresponding running results and completing path verification of the network on chip.
In a third aspect, the present application discloses an electronic device comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the previously disclosed network-on-chip path verification method.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the steps of the previously disclosed network-on-chip path verification method.
It can be seen that the present application discloses a path verification method for a network on chip, comprising: extracting architecture information of a network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information; selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter; and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip. Therefore, corresponding verification environments can be generated only by filling different architecture information files in the face of different network-on-chip, verification is performed without generating the verification environments independently for each network-on-chip, and repeated workload and verification period of a verification engineer are reduced; the visual graphical user interface is provided, so that a verification engineer can randomly select a verification passage and passage parameters, the operation is convenient, and the passage verification diversity is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of path verification for a network on chip disclosed in the present application;
FIG. 2 is an exemplary diagram of a verification environment for a network on chip disclosed herein;
FIG. 3 is a flowchart of a method of path verification for a specific network-on-chip disclosed herein;
FIG. 4 is a flowchart of another specific network-on-chip path verification method disclosed herein;
FIG. 5 is a flow chart of functional modules of a network on chip disclosed in the present application;
FIG. 6 is a schematic diagram of a path verification device of a network on chip disclosed in the present application;
fig. 7 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
With the development of integrated circuits, soC is increasingly moving toward large scale, high integration, high complexity, high performance, and low power consumption. In order to efficiently implement task processing, numerous IPs on the SoC propose high performance indexes such as high bandwidth, low latency, etc. for the processed data. At this time, on-chip interconnection tends to be a key to the breakthrough of the performance of the whole SoC. Nocs act as a bus interconnect architecture for connecting multiple masters and slaves to achieve high performance communication throughout the system. The method is highly configurable and structured, and a high-efficiency, high-flexibility and extensible solution is provided for the system by referencing some concepts of the general network. Network-on-chip solutions are now the main direction of development for SoC interconnects.
In order to meet the performance requirements of socs, networks on chip are increasingly being used. The network on chip provided by each manufacturer is used as a mature general IP, has huge self-functions and has been fully verified. Therefore, in SoC, the most important of the network-on-chip verification work is how to quickly implement the full-path verification work. The challenges faced by the path verification of the network on chip in the current SoC are: the variety of path types, where a path refers to the path that a master sees to a slave through a NoC. The variety of path types requires that the verification engineer perform different tests based on the path characteristics of each master-slave at the time of verification. Nocs exist in a wide variety of variations, from 3 points: there are multiple different nocs in one SoC; different versions of one SoC make NoC possible to vary; nocs in different projects; with the increase of the number of hosts and slaves and the increase of the protocol types, how to ensure the completeness of the verification of each path is a problem that needs to be considered by a verification engineer. In addition, if a certain host or the characteristics of the host are changed, all the path verification related to the host needs to be changed. In the early stages of the project, a change is necessary, but this undoubtedly increases the repetitive effort of the verification engineer. The diversity of the via types is therefore very problematic and presents significant challenges to the verification engineer. In the face of many different nocs, the effort of the verification engineer is definitely enormous if each should build a verification environment separately and develop test cases for verification.
Therefore, the application discloses a network-on-chip access verification scheme, which can find the universality of NoCs, and the verification work is also changed into universal, so that the verification of a plurality of NoCs is rapidly completed, and the technical problem to be solved in the field is solved.
Referring to fig. 1, the embodiment of the invention discloses a path verification method of a network on chip, which comprises the following steps:
step S11: and extracting architecture information of the network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information.
In this embodiment, architecture information of a network on chip to be verified is extracted to generate configuration information for configuring a verification environment; and generating a corresponding verification environment based on the configuration information. Specifically, the transmission behaviors of a host computer and a slave computer connected with the network on chip to be verified are simulated by using the verification IP core, and corresponding paths are generated to generate corresponding verification environments; the access is used for the data transmission of the host and the slave through the network-on-chip to be verified, the access protocol and the access parameters. The verification environment of the NoC is generated based on the extracted architecture information, and fig. 2 is an exemplary diagram of a verification environment. The authentication environment integrates VIP (authentication IP) into it to simulate the behavior of masters and Slave, while also generating base sequences for each path. The base sequence of each path randomly transmits n transmissions in a random range of various parameters according to the Master and Slave protocols and protocol parameters of the path. Wherein various parameters may also be specified by the verification engineer to send a particular transmission.
In this embodiment, before extracting the architecture information of the network on chip to be verified, the method further includes: and filling in an information file of the network-on-chip to be verified, wherein the information file comprises the number, the name, the interface protocol and the access parameters of the interface units which are in butt joint with the host and the interface units which are in butt joint with the slave. It will be appreciated that for a SoC, which is often composed of multiple subsystems, there are correspondingly multiple nocs. Nocs are responsible for the connection and communication of the various IPs on the SoC, and their function and performance is critical to the overall SoC. The description will be given taking NoC IP, which is proposed by artris, an interconnection IP company that is leading worldwide, as an example. Filling in architecture information: the architecture engineer fills out the architecture information of the NoC, including all Initiator NIU (the region defined by the region that interfaces with the host) and Target NIU (the region defined by the region that interfaces with the slave) of the NoC:
1) Number of pieces
2) A name;
3) Interface protocols and protocol parameters, such as address bit width, data bit width, ID bit width, burst type supported, burst size range, burst length range, etc. of AXI (on-chip bus);
4) Address mapping relationship.
Due to the diversity of host protocols, nocs support a variety of protocols, such as AXI of the ARM AMBA (advanced microcontroller bus architecture) family, AHB (advanced high-performance bus), APB (peripheral bus), and the like. A NoC may connect multiple hosts, each of which may employ a different interface protocol, and each of which may involve a variety of parameters, and thus may issue a variety of accesses. For example, a host using AHB as the interface protocol may only issue address-aligned accesses, while a host using AXI as the interface protocol may issue address-non-aligned accesses. One interface protocol is an AXI host, which can send out FIXED, INCR, WRAP types of bursts, and the burst length, address and other parameters are different for different burst types. Even with the same protocol, the parameters differ and their access differs. For example, for a host with both interface protocols being AXI, the data bit width of host 1 is 64 bits, the data bit width of host 2 is 32 bits, and the burst sizes sent by host 1 and host 2 are different. Diversity of slave protocols: likewise, a NoC may connect to multiple slaves, each of which may employ a different interface protocol, and each of which may involve a variety of parameters, and thus may receive a variety of accesses. For example, a slave with an interface protocol of AHB may only receive address-aligned accesses, while a slave with an interface protocol of AXI may receive address-non-aligned accesses. Then, based on the above architecture information, a corresponding verification environment is generated, and in the generated verification environment, a part of protocols supported by the NoC need to be supported, where the protocols specifically may include, but are not limited to: AXI protocol, AHB protocol, NSP (Arteris NoC Socket) protocol, etc. In this way, by filling in the architecture information of all the master-slave protocols and related parameters in advance, corresponding verification environments can be generated only by filling in different architecture information files for different nocs, verification is not required to be performed by generating the verification environments for each NoC independently, and repeated workload and verification period of a verification engineer are reduced.
In this embodiment, since the verification environment is automatically generated based on the extracted architecture information, the update operation of the verification environment is also performed based on the extracted new architecture information, that is, when the filled architecture information changes, the verification environment is automatically updated based on the extracted changed architecture information.
Step S12: a target pathway is selected from the verification environment and target pathway parameters are determined through a graphical user interface.
In this embodiment, a target path is selected through a base sequence of each path of the verification environment shown in a GUI (graphical user interface) interface, and corresponding target path parameters and a customized test case are determined to verify the target path parameters.
Step S13: and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip.
In this embodiment, according to the determined target path, the target path parameters and the service scenario, the corresponding test case is operated, where the service scenario also belongs to one of the path types, and the type of the generated test case may be that the AHB Master supports sending out the access of the INCR type. In a system, the scene is different and the access may be different. For example, a CPU with an AXI interface protocol is used as a host to access a slave with three AXI interface protocols, the slave 1 is a device based on FIFO storage, the slave 2 is a device based on a piece of static storage unit, and the slave 3 is a device based on a piece of continuous static storage unit. The master will typically access the slave 1 in a burst transfer of burst type FIXED, data bit width size FIFO data bit width. If the Cache is turned off when the host accesses the slave 2, the slave 2 is typically accessed in bursts of burst type INCR and size RAM data bit width; if the system opens the Cache when the host accesses the slave 3, when the access occurs that needs to perform the Cache replacement operation, the slave 3 may be accessed by burst transmission with burst type WRAP and burst length of one Cache line size. Therefore, in selecting the test case verification target path, attention is also required to a specific service scenario, for example: the performance when the host 1 and the host 2 access the slave 1 simultaneously, the host accesses the slave with a certain specific protocol parameter, and the like. By extracting the architecture information filled by the architecture engineer, the automation of NoC access verification is realized, namely, a verification environment is automatically generated according to the architecture information, and the specific scenes can be verified conveniently and intuitively by the verification engineer by displaying the access and the parameters through a GUI interface.
It can be seen that the present application discloses a path verification method for a network on chip, comprising: extracting architecture information of a network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information; selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter; and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip. Therefore, corresponding verification environments can be generated only by filling different architecture information files in the face of different network-on-chip, verification is performed without generating the verification environments independently for each network-on-chip, and repeated workload and verification period of a verification engineer are reduced; the visual graphical user interface is provided, so that a verification engineer can randomly select a verification passage and passage parameters, the operation is convenient, and the passage verification diversity is realized.
Referring to fig. 3, an embodiment of the present invention discloses a specific method for verifying a path of a network on chip, and compared with the previous embodiment, the present embodiment further describes and optimizes a technical solution. Specific:
step S21: and extracting architecture information of the network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information.
Step S22: selecting a preset number of target paths from the verification environment through a graphical user interface, and designating corresponding path parameters and/or default random path parameters for the target paths; the path parameters and/or the default random path parameters are determined as target path parameters.
In this embodiment, according to the base sequence of each path generated by the verification environment, each path and parameter are displayed to the verification engineer through the GUI interface, so that the verification engineer needs to select a target path or input related parameters from the displayed paths and parameters item by item, and it should be noted that the verification engineer may directly input a corresponding instruction to perform a selection operation or an input operation through the man-machine interaction interface, or may assist in selecting or inputting through an external device such as a mouse or a keyboard, and the specific related selected or input parameters include:
1) Selecting one or more paths to be verified;
2) Designating parameters for the selected path, if the parameters are not designated, automatically selecting the parameters randomly within a reasonable range of the supported parameters by default, and verifying the designated parameters;
3) Customizing a case name for the current test case, and customizing operation options such as coverage rate and the like;
step S23: and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip.
Therefore, the visual GUI interface is convenient for a verification engineer to randomly select a verification passage and passage parameters, the operation is convenient, the configurability of the passage test case is realized, and the passage verification diversity is further realized.
Referring to fig. 4, an embodiment of the present invention discloses a specific method for verifying a path of a network on chip, and compared with the previous embodiment, the present embodiment further describes and optimizes a technical solution. Specific:
step S31: and extracting architecture information of the network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information.
Step S32: a target pathway is selected from the verification environment and target pathway parameters are determined through a graphical user interface.
Step S33: and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip.
The more detailed processing procedures in steps S31, S32, and S33 refer to the above disclosed embodiments, and are not described herein.
Step S34: and generating a simulation report comprising a waveform file, a log file, a use case regression result and a coverage rate file according to the operation result.
In this embodiment, various simulation report files are generated according to the operation result, such as waveform file, log file, regression result file, and HTML report file; then displaying the simulation report, specifically displaying the simulation waveform file of the test case to a verification engineer in a waveform mode through view; view log realizes the function of displaying log files; view regression summary realizes the function of displaying regression result files; the view HTML report realizes the function of displaying the HTML report file, and the HTML report file of the test case is displayed to the verification engineer in the form of HTML.
Step S35: judging whether the simulation result of the simulation report meets a preset simulation target, if not, executing the steps of selecting a target passage from the verification environment through a graphical user interface and determining a target passage parameter.
In this embodiment, when the simulation result in the simulation report does not meet the preset simulation target issued by the verification engineer, or when the verification engineer wants to verify other paths, the paths can be reselected, and the corresponding test cases are automatically run again and the simulation report is generated until the verification engineer completes the set target. For different NoCs, only a framework engineer is required to provide corresponding framework information, and a verification engineer can quickly obtain verification environments of the different NoCs and quickly realize verification of the channel. The invention has the advantages of simple use, high reusability and visual simulation result, and avoids the repeated verification work of different NoCs faced by a verification engineer.
Referring to fig. 5, the path verification includes 4 functional modules: cfg_gen, env_gen, tc_run, report_gen.
The cfg_gen configuration information generating module is responsible for filling in architecture information, extracting the architecture information and generating a verification environment, and specifically comprises 3 parts: arc_info, extract info, cfg class. Wherein rc_info is the architecture information file of the NoC filled by the architecture engineer; the extract info realizes the function of extracting rc_info; cfg class is the finally generated configuration class file used to generate the verification environment.
The env_gen verification environment generation module is responsible for generating or updating a UVM (universal verification methodology) verification environment according to configuration information, and comprises only 1 sub-module: UVM env gen, the function of generating a UVM verification environment is implemented according to the generated cfg class.
The tc_run test case operation module is responsible for automatically operating the corresponding test case according to the path and the scene selected by the verification engineer in a GUI form, and specifically comprises 3 sub-modules: tc select, comp/run arg modification, run tcs. The tc select realizes the function of generating corresponding test cases according to the data paths selected by the verification engineer through the GUI; comp/run arg modification implements functions that modify the compiled or simulated commands according to the compiling or simulated options selected by the validation engineer via the GUI, such as: adding coverage rate, adjusting GUI interface to simulate, modifying TCL file, etc.; run tcs realizes the function of test case automation simulation.
The report_gen simulation report generating module is responsible for generating corresponding waveform files, log files, use case regression results and coverage rate files according to the running results of the test cases, and can select to report in various forms, and specifically comprises 5 sub-modules: post process, view waveform, view log, view regression summary, view html report. The post process is a post processing module, and achieves the function of generating various simulation report files, such as a waveform file, a log file, a regression result file and an HTML report file; the view realizes the function of displaying the waveform file, and the simulation waveform file of the test case is displayed to a verification engineer in a waveform mode; view log realizes the function of displaying log files; view regression summary realizes the function of displaying regression result files; the view HTML report realizes the function of displaying the HTML report file, and the HTML report file of the test case is displayed to the verification engineer in the form of HTML.
Therefore, various simulation reports are automatically generated, the display is clear and visual, and the verification engineer can conveniently conduct subsequent debugging and analysis. Through the three points, an automatic and rapid path verification process aiming at the NoC can be realized, and the whole method has high automation degree and strong reusability.
Referring to fig. 6, an embodiment of the present invention discloses a path verification apparatus for a network on chip, including:
the environment generation module 11 is used for extracting architecture information of the network on chip to be verified and generating a corresponding verification environment based on the architecture information;
a parameter determination module 12 for selecting a target pathway from the verification environment and determining a target pathway parameter via a graphical user interface;
and the path verification module 13 is used for running the corresponding test cases based on the target path, the target path parameters and the service scene, acquiring corresponding running results and completing path verification of the network on chip.
It can be seen that the present application discloses a path verification method for a network on chip, comprising: extracting architecture information of a network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information; selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter; and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip. Therefore, corresponding verification environments can be generated only by filling different architecture information files in the face of different network-on-chip, verification is performed without generating the verification environments independently for each network-on-chip, and repeated workload and verification period of a verification engineer are reduced; the visual graphical user interface is provided, so that a verification engineer can randomly select a verification passage and passage parameters, the operation is convenient, and the passage verification diversity is realized.
In some embodiments, the path verification device of the network on chip may specifically include:
and the information file generating unit is used for filling in an information file of the network-on-chip to be verified, which comprises the number, the name, the interface protocol and the access parameters of the interface unit which is in butt joint with the host and the interface unit which is in butt joint with the slave.
In some embodiments, the environment generating module 11 may specifically include:
the information acquisition unit is used for extracting architecture information of the network on chip to be verified so as to generate configuration information for configuring the verification environment;
and generating a corresponding verification environment based on the configuration information.
In some embodiments, the environment generating module 11 may specifically include:
the environment generation unit is used for simulating the transmission behaviors of a host computer and a slave computer connected with the network on chip to be verified by using the verification IP core, and generating a corresponding passage so as to generate a corresponding verification environment; the access is used for the data transmission of the host and the slave through the network-on-chip to be verified, the access protocol and the access parameters.
In some embodiments, the parameter determining module 12 may specifically include:
a parameter determining unit, configured to select a preset number of target paths from the verification environment through a graphical user interface, and designate corresponding path parameters and/or default random path parameters for the target paths; the path parameters and/or the default random path parameters are determined as target path parameters.
In some embodiments, the path verification device of the network on chip may specifically include:
and the report generating unit is used for generating a simulation report comprising a waveform file, a log file, a use case regression result and a coverage rate file according to the operation result.
In some embodiments, the path verification device of the network on chip may specifically include:
and the result judging unit is used for judging whether the simulation result of the simulation report meets a preset simulation target, and if not, executing the steps of selecting a target passage from the verification environment through a graphical user interface and determining a target passage parameter.
Further, the embodiment of the present application further discloses an electronic device, and fig. 7 is a block diagram of the electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.
Fig. 7 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is configured to store a computer program that is loaded and executed by the processor 21 to implement relevant steps in the network-on-chip path verification method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of DSP (Digital Signal Processing ), FPGA (Field-Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array ). The processor 21 may also comprise a main processor, which is a processor for processing data in an awake state, also called CPU (Central Processing Unit ); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit, image processor) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence ) processor for processing computing operations related to machine learning.
The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, and the like, and the storage may be temporary storage or permanent storage.
The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and the computer program 222, so as to implement the operation and processing of the processor 21 on the mass data 223 in the memory 22, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the network-on-chip path verification method disclosed by any of the foregoing embodiments as being performed by the electronic device 20. The data 223 may include, in addition to data received by the electronic device and transmitted by the external device, data collected by the input/output interface 25 itself, and so on.
Further, the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the previously disclosed path verification method for a network on chip. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above describes in detail a method, apparatus, device and storage medium for path verification of network on chip provided by the present invention, and specific examples are applied to illustrate the principles and embodiments of the present invention, where the above description of the examples is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A method for path verification of a network on chip, comprising:
extracting architecture information of a network-on-chip to be verified, and generating a corresponding verification environment based on the architecture information;
selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter;
and running corresponding test cases based on the target path, the target path parameters and the service scene, and obtaining corresponding running results to complete path verification of the network-on-chip.
2. The method for path verification of a network on chip according to claim 1, wherein before extracting the architecture information of the network on chip to be verified, further comprises:
and filling in an information file of the network-on-chip to be verified, wherein the information file comprises the number, the name, the interface protocol and the access parameters of the interface units which are in butt joint with the host and the interface units which are in butt joint with the slave.
3. The method for path verification of a network on chip according to claim 1, wherein the extracting architecture information of the network on chip to be verified, generating a corresponding verification environment based on the architecture information, comprises:
extracting architecture information of a network-on-chip to be verified to generate configuration information for configuring a verification environment;
and generating a corresponding verification environment based on the configuration information.
4. The method for path verification of a network on chip according to claim 1, wherein the generating a corresponding verification environment based on the architecture information comprises:
simulating the transmission behaviors of a host computer and a slave computer connected with the network on chip to be verified by using the verification IP core, and generating a corresponding passage to generate a corresponding verification environment; the access is used for the data transmission of the host and the slave through the network-on-chip to be verified, the access protocol and the access parameters.
5. The method of path verification of a network on chip of claim 1, wherein the selecting a target path from the verification environment and determining target path parameters via a graphical user interface comprises:
selecting a preset number of target paths from the verification environment through a graphical user interface, and designating corresponding path parameters and/or default random path parameters for the target paths;
the path parameters and/or the default random path parameters are determined as target path parameters.
6. The method for verifying a path of a network on chip according to any one of claims 1 to 5, wherein after the running of the corresponding test case based on the target path, the target path parameters, and the service scenario, and the obtaining of the corresponding running result, further comprises:
and generating a simulation report containing the waveform file, the log file, the use case regression result and the coverage rate file according to the operation result.
7. The method for path verification of a network on chip according to claim 6, wherein after generating a simulation report including a waveform file, a log file, a use case regression result, and a coverage rate file according to the operation result, further comprising:
judging whether the simulation result of the simulation report meets a preset simulation target, if not, executing the steps of selecting a target passage from the verification environment through a graphical user interface and determining a target passage parameter.
8. A network-on-chip path verification apparatus, comprising:
the environment generation module is used for extracting architecture information of the network on chip to be verified and generating a corresponding verification environment based on the architecture information;
a parameter determination module for selecting a target pathway from the verification environment through a graphical user interface and determining a target pathway parameter;
and the path verification module is used for running the corresponding test cases based on the target path, the target path parameters and the service scene, acquiring corresponding running results and completing path verification of the network on chip.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the path verification method of a network on chip as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program; wherein the computer program when executed by a processor implements the steps of the path verification method of a network on chip as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310091520.7A CN116306474A (en) | 2023-02-03 | 2023-02-03 | Method, device, equipment and storage medium for verifying access of network on chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310091520.7A CN116306474A (en) | 2023-02-03 | 2023-02-03 | Method, device, equipment and storage medium for verifying access of network on chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116306474A true CN116306474A (en) | 2023-06-23 |
Family
ID=86819534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310091520.7A Pending CN116306474A (en) | 2023-02-03 | 2023-02-03 | Method, device, equipment and storage medium for verifying access of network on chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116306474A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117194388A (en) * | 2023-11-02 | 2023-12-08 | 摩尔线程智能科技(北京)有限责任公司 | Data management method, device, electronic equipment and storage medium |
| CN118520825A (en) * | 2024-07-24 | 2024-08-20 | 北京开源芯片研究院 | Method, device, equipment and storage medium for constructing network on chip |
-
2023
- 2023-02-03 CN CN202310091520.7A patent/CN116306474A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117194388A (en) * | 2023-11-02 | 2023-12-08 | 摩尔线程智能科技(北京)有限责任公司 | Data management method, device, electronic equipment and storage medium |
| CN117194388B (en) * | 2023-11-02 | 2024-02-06 | 摩尔线程智能科技(北京)有限责任公司 | Data management method, device, electronic equipment and storage medium |
| CN118520825A (en) * | 2024-07-24 | 2024-08-20 | 北京开源芯片研究院 | Method, device, equipment and storage medium for constructing network on chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113312879B (en) | Chip circuit function verification system, method, device and storage medium | |
| CN109039824B (en) | Automatic test system and method for wireless remote communication protocol of vehicle-mounted terminal | |
| US6173438B1 (en) | Embedded graphical programming system | |
| US10592397B2 (en) | Representing a test execution of a software application using extended reality | |
| CN116306474A (en) | Method, device, equipment and storage medium for verifying access of network on chip | |
| US7480609B1 (en) | Applying distributed simulation techniques to hardware emulation | |
| US20140343915A1 (en) | Test environment configuration apparatus and method of operating network simulation apparatus using same | |
| CN109783340B (en) | SoC test code programming method, IP test method and device | |
| CN112286746A (en) | Universal verification platform and method for AXI slave device interface | |
| CN113722020A (en) | Interface calling method, device and computer readable storage medium | |
| CN101551827B (en) | Test method and device capable of switching multi-simulation accuracy | |
| CN111859834A (en) | A UVM-based verification platform development method, system, terminal and storage medium | |
| CN104237699A (en) | USB (universal serial bus) interface communication test system and method | |
| CN114611445B (en) | SoC software and hardware collaborative verification system and method based on FPGA prototype | |
| Levi et al. | BoardScope: A debug tool for reconfigurable systems | |
| CN113657069B (en) | SOC simulation verification method and device, verification server and storage medium | |
| CN104683438A (en) | A Beidou or GPS dual-mode online positioning method | |
| CN106815150B (en) | Server-side interface test system and method | |
| CN113595817A (en) | LIN communication fault injection method, system and storage medium | |
| WO2020000949A1 (en) | Driving system for pcie link and driving debugging system | |
| CN107390548B (en) | A kind of avionics HWIL simulation data path control system | |
| Lee et al. | Collecting big data from automotive ECUs beyond the CAN bandwidth for fault visualization | |
| EP3528126B1 (en) | Representing a test execution of a software application using extended reality | |
| US8046201B1 (en) | Communication system for use with a block diagram environment | |
| WO2005054883A1 (en) | Control device inspection device, pattern signal generation device, and inspection program creation device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |