CN116301969A - JTAG equipment upgrading method and computing equipment - Google Patents

Abstract

The embodiment of the application provides an upgrading method of JTAG equipment and computing equipment, relates to the technical field of computing equipment, and can improve the universality of a JTAG equipment upgrading scheme. The method comprises the following steps: the upper-level JTAG equipment sends JTAG channel switching information and first updating information to the local-level JTAG equipment through the communication bus; the first updating information is used for upgrading the target secondary JTAG equipment; the target secondary JTAG device is one of one or more secondary JTAG devices; the present-stage JTAG device enables a JTAG channel connected through a target JTAG bus between the present-stage JTAG device and a target secondary JTAG device in response to JTAG channel switching information; the present-stage JTAG device sends the first update information to the target secondary JTAG device through the target JTAG bus to upgrade the target secondary JTAG device. The method and the device can be used in the maintenance process of the computing equipment.

Description

JTAG equipment upgrading method and computing equipment

Technical Field

The present disclosure relates to the field of computing devices, and in particular, to an upgrade method for a JTAG device and a computing device.

Background

Typically, a computing device contains multiple components, each with a joint test workgroup (joint test act ion group, JTAG) device (JTAG device may be a logic device) disposed thereon, and multiple JTAG devices in the computing device need to be upgraded periodically. Along with the rapid iteration of the computing device, the computing device starts to develop towards the modularization direction, and components such as different mainboards, backplates and daughter cards are flexibly combined and interconnected, so that the topology of JTAG devices in the computing device is more and more complex, links between JTAG devices are longer and longer, and certain challenges are brought to the upgrading of the JTAG devices.

The design scheme for upgrading JTAG equipment is as follows: all JTAG devices are connected with complex programmable logic devices (complex programmable logic device, CPLD) of the main board, so that all JTAG devices form a daisy chain topology structure through the CPLD of the main board, and based on the topology structure, the CPLD of the main board controls all JTAG devices to upgrade based on logic.

However, in the above-mentioned scheme, it is necessary to reserve a JTAG bus connector on the motherboard for connection with each JTAG device, which leads to an increase in design cost of the motherboard. More importantly, in this solution, if the topology structure formed by the JTAG device changes (for example, when the JTAG device is added or deleted, the topology structure will change), the control logic of the CPLD of the motherboard needs to be modified or upgraded again.

Disclosure of Invention

The embodiment of the application provides an upgrading method of JTAG equipment and computing equipment, which can improve the universality of an upgrading scheme of JTAG equipment.

In a first aspect, an embodiment of the present application provides an upgrade method of a JTAG device, which is applied to a computing device, where the computing device includes a present-stage JTAG device, an upper-stage JTAG device, and one or more secondary JTAG devices; the upper-level JTAG equipment is connected with the local-level JTAG equipment through a communication bus and a JTAG bus; the present-stage JTAG device is connected with each secondary JTAG device in the one or more secondary JTAG devices through a communication bus and a JTAG bus respectively; the method comprises the following steps: the upper-level JTAG equipment sends JTAG channel switching information and first updating information to the present-level JTAG equipment through a communication bus; the first update information is used for upgrading the target secondary JTAG equipment; the target secondary JTAG device is one of the one or more secondary JTAG devices; enabling a JTAG channel connected through a target JTAG bus between the current-stage JTAG device and the target secondary JTAG device in response to the JTAG channel switching information; and the local JTAG equipment sends the first updating information to the target secondary JTAG equipment through the target JTAG bus so as to upgrade the target secondary JTAG equipment.

According to the upgrading method of the JTAG equipment, when a certain JTAG equipment (for example, target secondary JTAG equipment) needs to be upgraded, the upper-stage JTAG equipment of the computing equipment can send JTAG channel switching information to the local-stage JTAG equipment, so that a JTAG channel connected between the local-stage JTAG equipment and the target secondary JTAG equipment through a target JTAG bus is enabled, and further the local-stage JTAG equipment upgrades the target secondary JTAG equipment through the target JTAG bus. According to the JTAG device, the middle JTAG device is in a multi-level master-slave structure, each JTAG device is connected with the JTAG device of the upper stage, compared with the existing calculation, the mainboard is not required to provide more connectors to be connected with each JTAG device, the design cost of the mainboard is reduced, and the universality of the JTAG device upgrading scheme is guaranteed. In addition, the multi-level master-slave structure has clear topological relation, the updating of the topological relation is easy, only the topological relation on the changed branch is required to be modified, other branches are not affected, the universality of the upgrading scheme of the JTAG equipment can be further improved, and the upgrading difficulty of the JTAG equipment is reduced.

In a possible implementation manner, the present-stage JTAG device is provided with a register, where the register includes: JTAG switching bits; the present-stage JTAG device, responsive to the JTAG channel switch information, enables a JTAG channel connected through a target JTAG bus with the target secondary JTAG device, comprising: based on the JTAG channel switch information, the native JTAG device modifies the JTAG switch bit to enable a JTAG channel connected through a target JTAG bus with the target secondary JTAG device.

In another possible implementation manner, a register is provided on the upper-level JTAG device, where the register includes: a communication channel switching bit; before the upper-level JTAG device sends JTAG channel switching information and first update information to the present-level JTAG device via a communication bus, the method further comprises: the upper JTAG equipment acquires communication channel switching information; based on the communication channel switching information, the upper-level JTAG device modifies the communication bus switching bit to enable a communication channel connected between the upper-level JTAG device and the present-level JTAG device through a communication bus. The definition mode of the register can effectively display the position information (the level and the channel) of one JTAG device in the JTAG topological graph, and is convenient for positioning in the upgrading process. In addition, the register also comprises an indication bit for channel switching, and the computing device can realize point-to-point upgrade of the JTAG device by matching with the position information of the JTAG device in the JTAG topological graph, so that the accuracy and the stability of a JTAG upgrade scheme are ensured.

In yet another possible implementation manner, the register further includes: channel indicator bits, hierarchy indicator bits, and underhung device indicator bits; the channel indication bit is used for indicating a channel between one JTAG device and a last stage JTAG device of the JTAG device; the channels include a communication channel and/or a JTAG channel; the hierarchy indicating bit is used for indicating the hierarchy of one JTAG device in the JTAG topological graph; the JTAG topology map is used for indicating the connection relation among the upper-stage JTAG equipment, the present-stage JTAG equipment and the one or more secondary JTAG equipment; the underhung device indication bit is used to indicate the number of next-level JTAG devices of one JTAG device.

In yet another possible implementation, the computing device further includes: a main control unit; when the upper-level JTAG equipment is at a first level in the JTAG topological graph, the main control unit is connected with the upper-level JTAG equipment through a communication bus and a JTAG bus; the method further comprises the steps of: the main control unit sends the communication channel switching information to the upper-level JTAG equipment through a communication bus based on the JTAG topological graph; and transmitting the JTAG channel switching information and the first update information to the upper-level JTAG device through a communication bus.

In yet another possible implementation, the method further includes: and under the condition that JTAG equipment in the computing equipment is changed, the main control unit updates the JTAG topological graph according to channel indicating bits, hierarchy indicating bits and underhung equipment indicating bits in a register of JTAG equipment in the computing equipment. It can be understood that, in an actual scenario, the JTAG link may be changed, for example, a JTAG device is added or deleted, so that in order to ensure normal operation and upgrade of the JTAG link, the embodiment of the present application may implement autonomous update of the JTAG topology map, without excessive manual participation.

In yet another possible implementation, the method further includes: the main control unit sends second update information to the upper-level JTAG equipment through a JTAG bus; the second update information is used for upgrading the upper-level JTAG device.

In yet another possible implementation, the master unit is a central processing unit (central process ing unit, CPU) or a baseboard management controller (baseboard management control ler, BMC).

In yet another possible implementation, the communication bus is an I2C bus.

In a second aspect, embodiments of the present application provide a computing device comprising: a processor and a memory; the memory stores instructions executable by the processor; the processor is configured to execute the instructions to cause the computing device to implement the method of the first aspect described above.

In a third aspect, embodiments of the present application provide a computer-readable storage medium comprising: computer software instructions; the computer software instructions, when executed in a computing device, cause the computing device to implement the method of the first aspect described above.

In a fourth aspect, embodiments of the present application provide a computer program product which, when run on a computer, causes the computer to perform the steps of the related method described in the first aspect above, to implement the method of the first aspect above.

The advantages of the second aspect to the fourth aspect may refer to corresponding descriptions of the first aspect, and are not repeated.

Drawings

FIG. 1 is a schematic diagram of a computing device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of the components provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of the composition of another computing device provided in an embodiment of the present application;

fig. 4 is a flowchart of an upgrade method of a JTAG device provided in an embodiment of the present application;

fig. 5 is a flowchart of another method for upgrading a JTAG device according to an embodiment of the present application;

FIG. 6 is a flowchart illustrating another method for upgrading JTAG devices according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

It should be noted that, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms "first", "second", and the like are used to distinguish the same item or similar items having substantially the same function and effect, and those skilled in the art will understand that the terms "first", "second", and the like are not limited in number and execution order.

First, some of the backgrounds involved in the embodiments of the present application will be described.

JTAG is an international standard test protocol, and a device provided with a JTAG interface in a computing device and capable of connecting with a JTAG bus through the JTAG interface can be called a JTAG device. JTAG link refers to the use of JTAG bus to connect different JTAG devices (e.g., motherboard CPLD, backplane CPLD, etc.) in a computing device, facilitating testing of JTAG devices and their peripheral circuits through JTAG link, thereby improving the controllability and observability of devices in the computing device. Along with the rapid iteration of the computing device products, the computing device starts to develop towards the direction of modularization, and components such as different mainboards, backplates, daughter cards and the like are flexibly combined and interconnected, so that the topology of JTAG links in the computing device is more and more complex, the links are longer and longer, and how to upgrade the firmware of a plurality of JTAG devices and ensuring the stability of the upgrade are very challenging.

There is currently a scheme for daisy-chaining JTAG devices to upgrade JTAG devices using discrete switching devices. Specifically, JTAG devices of the same type are combined into a set, and then different types of sets are chained into a daisy chain by using a discrete switching device and summarized to a main control device. The main control equipment controls the switching state of the discrete switching device so that the discrete switching device is switched to different JTAG equipment, thereby connecting the main control equipment with the different JTAG equipment to upgrade the different JTAG equipment. This solution has the following drawbacks: when JTAG equipment is more, more link branches exist between the main control equipment and the JTAG equipment, so that the problem of overlong links is caused, the transmission quality of signals is affected, and the stability of upgrading cannot be ensured. And, more discrete switching devices are used, which is costly. In addition, because of the need of additionally arranging a discrete switching device, the design requirement on a circuit board where JTAG equipment is located is high, so that the scheme has poor universality.

In order to reduce the cost of using discrete switching devices, there is currently also a solution to replace discrete switching devices by CPLDs. Specifically, all JTAG devices are summarized to the mainboard CPLD through a JTAG bus, so that all JTAG devices form a daisy chain topology structure through the mainboard CPLD, and based on the topology structure, the mainboard CPLD controls all JTAG devices to upgrade based on logic. Although this approach may reduce the use of discrete switching devices, the following disadvantages still exist: all JTAG devices are connected to the motherboard CPLD via the JTAG bus, meaning that the motherboard needs to be provided with more connectors for connecting the JTAG devices, which results in higher motherboard layout requirements and increased motherboard design costs. In addition, in the scheme, different JTAG devices are strung into a daisy chain through the logic implementation of the main board CPLD, so that information such as the quantity type, topology and the like of the JTAG devices needs to be extracted and written into the main board CPLD. If the JTAG link changes, such as adding or deleting the JTAG device, the logic of the upgrade motherboard CPLD needs to be modified again, so that the universality is poor, and the upgrade of the JTAG device is complicated.

In view of the foregoing, there is a need for an upgrade scheme for JTAG devices with high versatility.

In this background, an embodiment of the present application provides a method for upgrading a JTAG device, where a computing device to which the method is applied includes a present-level JTAG device, an upper-level JTAG device, and one or more secondary JTAG devices; the upper-level JTAG equipment is connected with the local-level JTAG equipment through a communication bus and a JTAG bus; the present-stage JTAG device is connected to each of the one or more secondary JTAG devices through a communication bus and a JTAG bus, respectively. When a certain JTAG device (such as a target secondary JTAG device) needs to be upgraded, the upper-level JTAG device sends JTAG channel switching information and first updating information to the local-level JTAG device through a communication bus; the first updating information is used for upgrading the target secondary JTAG equipment; the target secondary JTAG device is one of one or more secondary JTAG devices; the present-stage JTAG device enables a JTAG channel connected through a target JTAG bus between the present-stage JTAG device and a target secondary JTAG device in response to JTAG channel switching information; the present-stage JTAG device sends the first update information to the target secondary JTAG device through the target JTAG bus to upgrade the target secondary JTAG device.

The upper stage, the present stage, and the secondary stage are relative concepts. Standing on the perspective of any one of the JTAG devices in the computing device, this JTAG device may be referred to as a local JTAG device. In connection, a JTAG device directly connected to the side of the present JTAG device near the controller is called an upper JTAG device. Any one of the one or more JTAG devices directly connected to the side of the present-stage JTAG device remote from the controller may be referred to as a secondary JTAG device. It should be appreciated that in some cases, depending on the JTAG device referenced, one JTAG device may be referred to as an upper level JTAG device, or may be referred to as a present level JTAG device or a secondary JTAG device. The controller may be a BMC or a CPU.

Compared with the scheme using the discrete switching device, the method provided by the embodiment of the application does not need to use the discrete switching device, and realizes channel switching by issuing JTAG channel switching information to the present-stage JTAG equipment so as to communicate different secondary JTAG equipment to perform point-to-point upgrading, thereby improving the universality of JTAG upgrading scheme. Compared with the scheme that the CPLD of the main board is used for replacing a discrete device, the JTAG device in the embodiment of the application presents a multi-stage tree topology structure, each JTAG device is connected with the JTAG device of the upper stage, the main board is not required to provide more connectors to connect each JTAG device, and the design cost of the main board is reduced. In addition, the updating and modification of the topological relation in the tree topology are easy to realize, only the corresponding branch is required to be modified, other branches are not influenced, the universality of the upgrading scheme of the JTAG equipment can be further improved, and the upgrading difficulty of the JTAG equipment is reduced.

The upgrading method of the JTAG equipment provided by the embodiment of the application can be applied to the computing equipment. The computing device includes a plurality of JTAG devices. Specifically, as shown in fig. 1, the computing device includes a present-level JTAG device, an upper-level JTAG device, and one or more secondary JTAG devices (3 secondary JTAG devices are shown as an example in the figure, wherein one secondary JTAG device is a target secondary JTAG device to be upgraded). The first-stage JTAG device is connected with the upper-stage JTAG device through a bus, and the first-stage JTAG device is connected with one or more secondary JTAG devices through buses respectively. Wherein the buses include a communication bus and a JTAG bus. The embodiment of the application is described by taking the communication bus as an I2C bus as an example.

The JTAG device in the computing device may be a complex programmable logic device (complex programmable logic device, CPLD) or a field programmable gate array (field programmable gate array, FPGA) disposed on the component, or other JTAG devices with data processing capabilities, which are exemplified as CPLD in the embodiment of the present application. The component may be a motherboard, a back plate, a fan plate, or the like in a computing device.

Fig. 2 is a schematic diagram of a component provided in an embodiment of the present application, where, as shown in fig. 2, a JTAG device is disposed on the component. Wherein, one end of the JTAG device in FIG. 2 leads out a communication bus and a JTAG bus for connecting with the JTAG device of the upper stage. The other end is also led out of the communication bus and the JTAG bus for connecting with the JTAG equipment of the next stage. It should be noted that, there may be multiple sets of communication buses and JTAG buses for connecting the next-stage JTAG device, and only 1 set is shown in fig. 2 as an example.

The main functions of the JTAG device are as follows: 1. as the JTAG device to be upgraded, it is upgraded by the JTAG device of the previous stage. 2. And upgrading the JTAG equipment of the next stage connected with the JTAG equipment. 3. And the JTAG device at the upper stage reports the information (topology information) of the register. 4. Topology information of a next-stage JTAG device connected with the JTAG device is recorded.

As can be seen in conjunction with fig. 1 and 2, each JTAG device in fig. 1 corresponds to a set of communication buses and JTAG buses, and in this embodiment of the present application, the JTAG buses are used for loading or upgrading the JTAG devices, and the communication buses are used for transmitting out-of-band management signals and upgrade packets of the JTAG devices.

Fig. 3 is a schematic diagram of another computing device according to an embodiment of the present application, where, as shown in fig. 3, the computing device includes 5 JTAG devices, which are JTAG devices 1-5, respectively. JTAG device 1 is arranged on a main board of the computing device, JTAG devices 2-4 are respectively arranged on backboard 1-3, and JTAG device 5 is arranged on a fan board. Wherein JTAG device 1 is connected to three next-stage JTAG devices, namely JTAG devices 2-4, respectively. JTAG device 2 is connected to 1 next-stage JTAG device, which is JTAG device 5. It can be seen that the JTAG device in fig. 3 presents a tree topology, and when the JTAG device 2 is the present-stage JTAG device, the upper-stage JTAG device is JTAG device 1, and the secondary JTAG device is JTAG device 5.

In some embodiments, a set of registers is defined within each JTAG device in the computing device that enable channel switching between JTAG devices, as well as recording of topology information for JTAG devices.

Wherein the register includes: the communication channel switch bit and the JTAG switch bit. Wherein the communication channel switching bit is used for enabling a communication channel connected through a communication bus between one JTAG device and a next stage JTAG device of the JTAG device, and the JTAG switching bit is used for enabling a JTAG channel connected through a JTAG bus between one JTAG device and a next stage JTAG device of the JTAG device. For example, for JTAG device 1 in FIG. 3, the communication channel switch bit in the register may be used to enable a communication channel corresponding to the I2C2 bus, the I2C3 bus, or the I2C4 bus, and the JTAG switch bit may be used to enable a JTAG channel corresponding to JTAG2, JTAG3, or JTAG 4. It can be seen that the communication channel switching bit and the JTAG switching bit can enable the JTAG equipment to be oriented to upgrade one next-stage JTAG equipment, and normal use of other next-stage JTAG equipment is not affected.

In addition, the register further includes: channel indicator bits, hierarchy indicator bits, and underhung device indicator bits.

Wherein the channel indication bit is used for indicating a channel between one JTAG device and a last stage JTAG device of the JTAG device, and the channel comprises a communication channel and/or a JTAG channel. For example, the channel indication bit on the register of JTAG device 2 in FIG. 3 indicates that JTAG device 2 is located on a first set of channels of JTAG device 1, the first set of channels corresponding to I2C2 and/or JTAG2. The channel indication bit on the register of JTAG device 3 indicates that JTAG device 3 is located on a second set of channels of JTAG device 1, the second set of channels corresponding to I2C3 and/or JTAG3.

The hierarchy indication bit is used for indicating the hierarchy of one JTAG device in a JTAG topology map, and the JTAG topology map is used for indicating the connection relation among the upper-level JTAG device, the present-level JTAG device and one or more secondary JTAG devices. It can be seen that the JTAG topology map in FIG. 3 presents a tree topology. If JTAG device 1 is the root node of the tree topology, then the hierarchy indication bits on the registers of JTAG device 1 indicate that JTAG device 1 is at the first level of the JTAG topology map. JTAG device 2, JTAG device 3, and JTAG device 4 are next to JTAG device 1, and the hierarchy indication bits on the registers of JTAG device 2, JTAG device 3, and JTAG device 4 indicate that they are at the second stage of the JTAG topology map. JTAG device 5 is the next to JTAG device 2 of the second stage, and the hierarchy indication bit of the register of JTAG device 5 indicates that it is at the third stage of the JTAG topology map.

The underhung device indication bit is used to indicate the number of next-level JTAG devices of one JTAG device, and the number of bit signals of the next-level JTAG devices, which can be acquired by the JTAG device, of the numerical value of the underhung device indication bit is determined. For example, in fig. 3, JTAG device 1 hangs down JTAG device 2, JTAG device 3, and JTAG device 4, and then the hang device indication bit on the register of JTAG device 1 indicates that the number of hang devices of JTAG device 1 is 3.

In some embodiments, the above register further includes: the bit itself indicates a bit. The self bit indicating bit is used for indicating whether the JTAG device is in place or not, and is determined by the JTAG device at the upper stage. For example, for JTAG device 2 in FIG. 3, after its previous stage JTAG device (i.e., JTAG device 1) has acquired the bit signal, it may determine that JTAG device 2 is in bit, and instruct JTAG device 2 to modify its own bit indicator bit on its own register to indicate that JTAG device 2 is powered up in bit.

The definition format of a register provided in the embodiment of the present application is shown in the following table 1:

TABLE 1

As shown in table 1, this register is exemplified by 16 bits (bit) bits. Wherein bit [15:13] represents JTAG channel to be switched, if the corresponding value is 000, the default state is represented, and the default channel (preset channel) is used. bit12 indicates itself in place, read by the previous stage, in position 1, if it is always 0, indicating that the device is the first stage. bit [11:9] represents an I2C channel to be switched, and if the corresponding value is 000, a default state is represented, and a default channel (a preset channel) is used. bit [8:6] represents the level of the JTAG topology map where the component is located, bit [5:3] indicates the JTAG channel between the component and the upper level component, and bit [2:0] represents the number of secondary devices.

It can be understood that, in table 1, the number of the down-hanging devices of one JTAG device is 7 at the maximum if the down-hanging device indication bits occupy 3 bits, and if more devices need to be down-hung by the JTAG device in an actual scenario, the number of bits of the register may be increased.

The definition mode of the register can effectively display the position information (the level and the channel) of one JTAG device in the JTAG topological graph, and is convenient for positioning in the upgrading process. In addition, the register also comprises an indication bit for channel switching, and the computing device can realize point-to-point upgrade of the JTAG device by matching with the position information of the JTAG device in the JTAG topological graph, so that the accuracy and the stability of a JTAG upgrade scheme are ensured.

Fig. 4 is a flowchart of an upgrade method of a JTAG device according to an embodiment of the present application. The method for upgrading the JTAG device provided by the embodiment of the application can be applied to the computing device shown in FIG. 1.

S401, the upper-level JTAG device sends JTAG channel switching information and first update information to the local-level JTAG device through the communication bus.

The first update information is used for upgrading a target secondary JTAG device, and the target secondary JTAG device is one of one or more secondary JTAG devices.

In some embodiments, when one of the computing devices (the target secondary JTAG device) needs to be upgraded, the upper-level JTAG device may send JTAG channel switching information and first update information to the present-level JTAG device through a communication bus connected to the present-level JTAG device. The JTAG channel switching information can enable the JTAG channel connected between the current-stage JTAG device switch and the target secondary JTAG through the target JTAG bus.

S402, enabling a JTAG channel connected through a target JTAG bus between the present-stage JTAG device and the target secondary JTAG device in response to the JTAG channel switching information.

In some embodiments, after receiving the JTAG channel switching information of the upper-level JTAG device, the present-level JTAG device can enable the JTAG channel connected with the target secondary JTAG device through the target JTAG bus based on the JTAG channel switching information, so as to realize the directional switching of the JTAG channel between the present-level JTAG device and the secondary JTAG device, and realize the point-to-point upgrade.

Specifically, the registers of the present-stage JTAG device include JTAG switch bits. After receiving the JTAG channel switching information, the present-stage JTAG device may modify the JTAG switching bit to enable a JTAG channel connected through the target JTAG bus with the target secondary JTAG device based on the JTAG channel switching information.

For example, described in connection with fig. 3. Taking this level of JTAG device as JTAG device 2 in FIG. 3 as an example, the upper level JTAG device is JTAG device 1 in FIG. 3, and the target secondary JTAG device is JTAG device 5 in FIG. 3. With JTAG device 5 being located on a first set of channels of JTAG device 2. Accordingly, JTAG device 2, upon receiving the channel switch information of JTAG device 1, modifies bits [15:13] in its own register from a value of 000 to 001, enabling JTAG channels between JTAG device 2 and JTAG device 5 that are connected through a JTAG5 bus.

S403, the present-stage JTAG device sends the first update information to the target secondary JTAG device through the target JTAG bus so as to upgrade the target secondary JTAG device.

In some embodiments, the present stage JTAG device may receive the first update information sent by the upper stage JTAG device, send the first update information to the target secondary JTAG device via the enabled target JTAG bus, and implement a directed upgrade to the target secondary JTAG device.

Illustratively, as previously described, the communication bus may be used to transmit the upgrade package of the JTAG device. Continuing to refer to fig. 3, after receiving the upgrade packet transmitted by the JTAG device 1 through the I2C2 bus, the JTAG device 2 may parse the upgrade packet to obtain first update information, and further send the first update information to the JTAG device 5 through the JTAG5 bus (target JTAG bus) to perform directional upgrade on the JTAG device 5.

In some embodiments, as shown in fig. 5, before S401, the upgrading method of the JTAG device provided in the embodiment of the present application further includes the following S400a and S400b.

S400a, the upper-level JTAG equipment acquires the communication channel switching information.

The communication channel switching information is used for indicating the upper-stage JTAG equipment to switch the communication channel connected with the present-stage JTAG equipment through the communication bus.

S400b, based on the communication channel switching information, the upper-stage JTAG device modifies the communication bus switching bit to enable the communication channel connected between the upper-stage JTAG device and the present-stage JTAG device through the communication bus.

The description will be continued with reference to fig. 3. Taking the above-mentioned JTAG device as JTAG device 1 as an example, three JTAG devices are hung under JTAG device 1. Wherein JTAG device 2 is located on a first set of channels of JTAG device 1. If JTAG device 2 wants to send the first update information and JTAG channel switch information to JTAG device 2, it is necessary to enable a communication channel between JTAG device 1 and JTAG device 2 connected through the I2C2 bus. Therefore, JTAG device 1, after obtaining the communication channel switching information, modifies the value of bit [11:9] in its own register from 000 to 001, enabling the I2C2 bus between JTAG device 1 and JTAG device 2.

In some embodiments, a master control unit is also included in the computing device. The main control unit can be a logic device with data processing capability such as a CPU or BMC. When the upper-level JTAG device is at the first level in the JTAG topological graph, the main control unit is connected with the upper-level JTAG device through a communication bus and a JTAG bus. For example, in fig. 3, the main control unit is disposed on the motherboard and is connected to the JTAG device 1 through the I2C1 bus and the JTAG1 bus.

In this embodiment of the present application, the main functions of the main control unit are: 1. and acquiring register information of the JTAG equipment through the communication bus, and generating a topological relation of the JTAG equipment based on the analysis of the register information. 2. And upgrading the JTAG equipment. 3. The JTAG topology map of the JTAG devices in the computing device is shown to the user.

In one possible implementation manner, if the main control unit is a CPU, the main control unit needs to further report the analysis result of the register information to the BMC, and the analysis result is displayed to the user by the BMC through the BMC management system.

In another possible implementation manner, if the master control unit is a BMC, the master control unit may directly display the analysis result to the user through the BMC management system.

In the embodiment of the application, the main control unit is used for modifying and configuring the values of the registers of the JTAG device. The process of configuring registers of the JTAG device is described in detail with reference to FIG. 3 and Table 1 above. After the computing devices are powered up, the master unit polls each of the JTAG devices in the computing devices and rewrites the register information of the JTAG devices to indicate topology information of the JTAG devices in the JTAG topology map.

For JTAG device 5, register bit [2:0] =3' b000, since the next stage has no devices. After all JTAG devices are polled, the main control unit determines that JTAG device 5 is in place and sets its register bit12 to 1. The master unit passes level 3 (JTAG device 1-JTAG device 2-JTAG device 5) when it polls JTAG device 5, so the master unit rewrites the register bit [8:6] =3' b011. The I2C5 bus and the JTAG5 bus between JTAG device 2 and JTAG device 5 are the first set of channels of JTAG device 2, so the master unit rewrites the register bit [5:3] =3' b001. In summary, after the main control unit finishes the power-on polling, the register 5 of the JTAG device may be represented as [15:0] = 16'b0001 0000 11001000, which indicates that the second secondary JTAG device is in the third level of the JTAG topology, and the first channel position is a leaf node of the tree topology without the down-hanging device.

For JTAG device 3, since the next stage has no device, register bit [2:0] = 3' b000. After all JTAG devices are polled, the main control unit determines that JTAG device 3 is in place and sets its register bit12 to 1. The main control unit polls JTAG equipment 3 to transfer 2 stages, so that the main control unit rewrites the register bit [8:6] =3' b010; the I2C3 bus and the JTAG3 bus are the second set of channels of JTAG device 1, so the master unit rewrites the register bit [5:3] =3' b010. After the master unit finishes the power-on polling, the value of the register of the JTAG device 3 may be represented as [15:0] = 16'b0001 0000 10010000, which indicates that the JTAG device 3 is at the second level of the JTAG topology, and the second channel position is a leaf node of the tree topology without an underhung device.

Similarly, the value of the register of JTAG device 4 in fig. 3 may be represented as [15:0] = 16'b0001 0000 1010 0000, indicating that JTAG device 4 is at the second level of the JTAG topology, the third path location, and no down-hanging device, is a leaf node of the tree topology.

The value of the register of JTAG device 2 in FIG. 3 may be represented as [15:0] = 16'b0001 0000 0100 1001, indicating JTAG device 1 is at the second level of the JTAG topology, the first lane position, underhanging 1 device, being an intermediate node of the tree topology. The value of the register of JTAG device 1 in fig. 3 may be denoted as [15:0] = 16'b0001 0000 0100 1011, indicating that JTAG device 1 is at the first level of the JTAG topology, the first channel position, underhanging three devices, being the root node of the tree topology.

It can be seen that the definition mode of the register shows inheritance and relevance among JTAG devices, so that the main control unit is convenient to adaptively manage out-of-band, and stability and universality of JTAG links are improved.

Fig. 6 is a flowchart of another method for upgrading a JTAG device according to an embodiment of the present application.

S601, a main control unit sends communication channel switching information to upper-level JTAG equipment through a communication bus based on JTAG topological graph; and transmitting the JTAG channel switching information and the first update information to the upper-level JTAG device through the communication bus.

Referring to fig. 3, it can be seen that the target secondary JTAG device (JTAG device 5) is the next stage of JTAG device 2, and that JTAG device 2 is the next stage of JTAG device 1. Therefore, when the JTAG device 5 needs to be upgraded, the main control unit sends the communication channel switching information to the JTAG device 1 through the I2C0 bus based on the JTAG topology map, so that the JTAG device 1 modifies the communication channel switching bit of its own register based on the communication channel switching information, and enables the I2C1 bus, so that the JTAG device 1 can transmit data to the JTAG device 2 through the I2C1 bus. In addition, the main control unit also sends JTAG channel switching information and first updating information to the JTAG device 1 through the I2C0 bus, so that the JTAG device 1 can further send the JTAG channel switching information and the first updating information to the JTAG device 2, and the directional upgrading of the JTAG device 2 to the JTAG device 5 is realized.

It can be seen that the above embodiments are for upgrading the secondary JTAG device, and in other embodiments, the main control unit may also upgrade the primary JTAG device. Referring to fig. 4, as shown in fig. 6, the method for upgrading the JTAG device further includes S602.

S602, the main control unit sends second update information to the upper-level JTAG equipment through the JTAG bus.

The second update information is used for upgrading the upper-level JTAG equipment.

It can be seen that, in fig. 3, the main control unit is directly connected with the upper-level JTAG device (JTAG device 1) through the JTAG bus (JTAG 0 bus), so that the main control unit can parse the second update information obtained by the upgrade packet, and send the second update information to the main JTAG device through the JTAG0 bus to upgrade the main JTAG device.

In some scenarios, the JTAG link may change, such as adding JTAG devices or deleting JTAG devices. In order to ensure normal operation and upgrading of the JTAG link, the upgrading method of the JTAG device provided by the embodiment of the application can also update the topology relation of the JTAG link in time. As shown in fig. 6, the following S603 is also included.

S603, under the condition that JTAG equipment in the computing equipment is changed, the main control unit updates the JTAG topological graph according to channel indicating bits, hierarchy indicating bits and underhung equipment indicating bits in a register of the JTAG equipment in the computing equipment.

As previously described, the registers defined in JTAG devices include channel indicator bits, hierarchy indicator bits, and underhung device indicator bits. These register information may reflect topology information of any one of the JTAG devices and related information of the secondary devices of the JTAG device. For example, the main control unit may periodically poll each JTAG device to obtain its register information, parse to obtain the latest JTAG link condition, and update the topology map. Alternatively, each JTAG device in the JTAG link may automatically report its own register information, so that the master unit updates the topology map. For example, in fig. 3, the JTAG device 3 is newly added with a next-stage JTAG device 6. Then the hang device indication bit in the register of JTAG device 3 indicates that JTAG device 3 has an hang device. In addition, based on the registers of JTAG device 6, the master unit determines that JTAG device 6 is at a third level, on the first set of channels of JTAG device 3. Therefore, the main control unit can update the JTAG topological graph, and a third-level node is added under the JTAG device 3 of the second level.

It can be understood that, in the subsequent process of upgrading the JTAG device, the main control unit upgrades according to the updated new JTAG topology.

In addition, the execution sequence of S601 to S603 in fig. 6 is not limited in the embodiment of the present application, and is only an example in the figure, and is not particularly limited.

It should be noted that, in the foregoing embodiments, the main control unit is connected to one first-stage JTAG device, and in other embodiments, the main control unit may be connected to a plurality of first-stage JTAG devices, that is, one main control unit may correspondingly manage a plurality of JTAG links, where one first-stage JTAG device is a root node of a tree topology of one JTAG link. The master control unit can implement management upgrade on different JTAG links through switching between the communication bus and the JTAG bus, and specifically, reference may be made to the description of the foregoing embodiments, and no repeated description is given here.

According to the technical scheme provided by the embodiment, at least the following beneficial effects are brought, when a certain JTAG device (for example, a target secondary JTAG device) needs to be upgraded, the upper-level JTAG device of the computing device can send JTAG channel switching information to the local-level JTAG device, so that the JTAG channel connected between the local-level JTAG device and the target secondary JTAG device through the target JTAG bus is enabled, and the target secondary JTAG device is further upgraded through the target JTAG bus by the local-level JTAG device. According to the JTAG device, the middle JTAG device is in a multi-level master-slave structure, each JTAG device is connected with the JTAG device of the upper stage, compared with the existing calculation, the mainboard is not required to provide more connectors to be connected with each JTAG device, the design cost of the mainboard is reduced, and the universality of the JTAG device upgrading scheme is guaranteed. In addition, the multi-level master-slave structure has clear topological relation, the updating of the topological relation is easy, only the topological relation on the changed branch is required to be modified, other branches are not affected, the universality of the upgrading scheme of the JTAG equipment can be further improved, and the upgrading difficulty of the JTAG equipment is reduced.

Furthermore, the method provided by the embodiment of the application does not need to use a discrete switching device, realizes channel switching by issuing JTAG channel switching information to JTAG equipment so as to communicate different JTAG equipment to perform point-to-point upgrading, improves the universality of JTAG upgrading schemes and reduces the cost.

In addition, the embodiment of the application also provides a new register definition scheme, so that flexible switching of channels among JTAG devices can be realized, and the accuracy of point-to-point upgrading is ensured. In addition, the register definition scheme can also realize the self-adaptive identification of the topology structure of the JTAG link of the computing device, excessive manual participation is not needed, the flexibility and the universality of JTAG link design are further ensured while the manpower resource cost is reduced, and the register definition scheme can be widely applied to most scenes.

It can be seen that the foregoing description of the solution provided by the embodiments of the present application has been presented mainly from a method perspective. To achieve the above-mentioned functions, embodiments of the present application provide corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Embodiments of the present application provide a structural schematic diagram of a computing device. As shown in fig. 7, the computing device 700 includes: a processor 702, a communication interface 703, and a bus 704. Optionally, the computing device may also include a memory 701.

The processor 702 may be any means for implementing or executing the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor 702 may be a central processor, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor 702 may also be a combination of computing functions, e.g., including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

A communication interface 703 for connecting with other devices via a communication network. The communication network may be an ethernet, a radio access network, a wireless local area network (wireless local area networks, WLAN), etc.

The memory 701 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (electrical ly erasable programmable read-only memory, EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

As a possible implementation, the memory 701 may exist separately from the processor 702, and the memory 701 may be connected to the processor 702 through the bus 704 for storing instructions or program codes. When the processor 702 calls and executes the instructions or the program codes stored in the memory 701, the upgrading method of the JTAG device provided in the embodiment of the present application can be implemented.

In another possible implementation, the memory 701 may also be integrated with the processor 702.

Bus 704, which may be an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like. The bus 704 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in fig. 7, but not only one bus or one type of bus.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the computing device is divided into different functional modules to perform all or part of the functions described above.

Embodiments of the present application also provide a computer-readable storage medium. All or part of the flow in the above method embodiments may be implemented by computer instructions to instruct related hardware, and the program may be stored in the above computer readable storage medium, and the program may include the flow in the above method embodiments when executed. The computer readable storage medium may be any of the foregoing embodiments or memory. The computer readable storage medium may also be an external storage device of the computing device, such as a plug-in hard disk provided on the computing device, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash card, or the like. Further, the computer-readable storage medium may also include both an internal storage unit and an external storage device of the computing device. The computer readable storage medium is used to store the computer program and other programs and data required by the computing device. The above-described computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

Embodiments of the present application also provide a computer program product, which contains a computer program, which when run on a computer causes the computer to perform the upgrade method of any one of the JTAG devices provided in the above embodiments.

Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. The upgrading method of the joint test workgroup JTAG equipment is characterized by being applied to computing equipment, wherein the computing equipment comprises a present-stage JTAG equipment, an upper-stage JTAG equipment and one or more secondary JTAG equipment; the upper-level JTAG equipment is connected with the local-level JTAG equipment through a communication bus and a JTAG bus; the present-stage JTAG device is connected with each secondary JTAG device in the one or more secondary JTAG devices through a communication bus and a JTAG bus respectively; the method comprises the following steps:

the upper-level JTAG equipment sends JTAG channel switching information and first updating information to the present-level JTAG equipment through a communication bus; the first update information is used for upgrading the target secondary JTAG equipment; the target secondary JTAG device is one of the one or more secondary JTAG devices;

enabling a JTAG channel connected through a target JTAG bus between the current-stage JTAG device and the target secondary JTAG device in response to the JTAG channel switching information;

And the local JTAG equipment sends the first updating information to the target secondary JTAG equipment through the target JTAG bus so as to upgrade the target secondary JTAG equipment.

2. The method of claim 1, wherein the present-stage JTAG device is provided with a register, the register comprising: JTAG switching bits;

the present-stage JTAG device, responsive to the JTAG channel switch information, enables a JTAG channel connected through a target JTAG bus with the target secondary JTAG device, comprising:

based on the JTAG channel switch information, the native JTAG device modifies the JTAG switch bit to enable a JTAG channel connected through a target JTAG bus with the target secondary JTAG device.

3. The method according to claim 1 or 2, wherein a register is provided on the upper-level JTAG device, the register comprising: a communication channel switching bit;

before the upper-level JTAG device sends JTAG channel switching information and first update information to the present-level JTAG device via a communication bus, the method further comprises:

the upper JTAG equipment acquires communication channel switching information;

based on the communication channel switching information, the upper-level JTAG device modifies the communication bus switching bit to enable a communication channel connected between the upper-level JTAG device and the present-level JTAG device through a communication bus.

4. A method according to claim 3, wherein the register further comprises: channel indicator bits, hierarchy indicator bits, and underhung device indicator bits;

the channel indication bit is used for indicating a channel between one JTAG device and a last stage JTAG device of the JTAG device; the channels include a communication channel and/or a JTAG channel;

the hierarchy indicating bit is used for indicating the hierarchy of one JTAG device in the JTAG topological graph; the JTAG topology map is used for indicating the connection relation among the upper-stage JTAG equipment, the present-stage JTAG equipment and the one or more secondary JTAG equipment;

the underhung device indication bit is used to indicate the number of next-level JTAG devices of one JTAG device.

5. The method of claim 4, wherein the computing device further comprises: a main control unit; when the upper-level JTAG equipment is at a first level in the JTAG topological graph, the main control unit is connected with the upper-level JTAG equipment through a communication bus and a JTAG bus; the method further comprises the steps of:

the main control unit sends the communication channel switching information to the upper-level JTAG equipment through a communication bus based on the JTAG topological graph; and transmitting the JTAG channel switching information and the first update information to the upper-level JTAG device through a communication bus.

6. The method of claim 5, wherein the method further comprises:

and under the condition that JTAG equipment in the computing equipment is changed, the main control unit updates the JTAG topological graph according to channel indicating bits, hierarchy indicating bits and underhung equipment indicating bits in a register of JTAG equipment in the computing equipment.

7. The method according to claim 5 or 6, characterized in that the method further comprises:

the main control unit sends second update information to the upper-level JTAG equipment through a JTAG bus; the second update information is used for upgrading the upper-level JTAG device.

8. The method according to any one of claims 5 to 7, wherein,

the main control unit is a Central Processing Unit (CPU) or a Baseboard Management Controller (BMC).

9. The method of any of claims 1-8, wherein the communication bus is an I2C bus.

10. A computing device, the computing device comprising a processor and a memory; the processor is coupled with the memory; the memory is used to store computer instructions that are loaded and executed by the processor to cause a computing device to implement the method of upgrading a JTAG device according to any of claims 1 to 9.

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