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CN116301142A - Circuit for controlling static power consumption of high-voltage LDO in voltage drop state - Google Patents

Circuit for controlling static power consumption of high-voltage LDO in voltage drop state Download PDF

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Publication number
CN116301142A
CN116301142A CN202211604453.6A CN202211604453A CN116301142A CN 116301142 A CN116301142 A CN 116301142A CN 202211604453 A CN202211604453 A CN 202211604453A CN 116301142 A CN116301142 A CN 116301142A
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voltage
type mos
mos tube
circuit
electrode
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丁敏
徐剑
李胜男
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NANJING MICRO ONE ELECTRONICS Inc
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NANJING MICRO ONE ELECTRONICS Inc
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The invention provides a circuit for controlling the static power consumption of the voltage drop state of a high-voltage LDO, which is applied to the technical field of the high-voltage LDO and comprises a feedback loop and a comparator circuit, wherein the feedback loop comprises a circuit for generating an output signal V by regulating the voltage OUT And will output signal V OUT Conventional high-voltage LDO circuit input to comparator circuit and comparison signal V for current controlling conventional high-voltage LDO circuit and receiving output of comparator circuit OCP Is provided; the comparator circuit comprises a mirror current unit for providing proper current to each part of the circuit and a comparator circuit for comparing the external high voltage power supply V IN And the output signal V of the feedback loop OUT And isolating the voltage of the circuit element according to the comparison result to output a comparison signal V OCP2 And an isolation comparison unit to the current limiting circuit. The circuit can reduce the static power consumption of the high-voltage LDO in a voltage drop state.

Description

Circuit for controlling static power consumption of high-voltage LDO in voltage drop state
Technical Field
The invention belongs to the technical field of high-voltage LDOs, and particularly relates to a circuit for controlling static power consumption in a voltage drop state of a high-voltage LDO.
Background
The invention patent CN113253792B is a circuit for controlling the static power consumption in the low-voltage LDO voltage drop state, and the problem that the static power consumption in the voltage drop state is large in the same high-voltage LDO is solved.
In the conventional high-voltage LDO structure (FIG. 1), when V IN ＜V OUT(NOM) +V DROP When, i.e. pressure drop state, V OUT ＜V OUT(NOM) Wherein V is OUT(NOM) For the normal output voltage of LDO, V DROP V under a certain load condition OuT Source-drain voltage necessary for high-voltage P-type Power tube Power during normal output, feedback voltage V generated by feedback resistor FB ＜V REF The output of the operational amplifier EA is positive, the grid potential of the low-voltage N-type MOS tube N1 is raised, the current of the second stage of the operational amplifier EA (common source amplification formed by the low-voltage N-type MOS tube N1) is very large, which causes the static current of the high-voltage LDO in a voltage drop state to be very large, and FIG. 3 is the voltage supply V with external high voltage based on the static power consumption of the high-voltage LDO of the circuit of FIG. 1 IN The waveform diagram of the voltage change obviously shows that the static power consumption of the high-voltage LDO in the voltage drop state is higher than the static power consumption I in the normal operation Q(NOM) Much higher, possibly up to I Q(NOM) Several hundred times of (a).
In order to solve the problem, the invention provides a circuit for controlling the static power consumption of the high-voltage LDO in the voltage drop state.
Disclosure of Invention
In view of the above problems in the prior art, an objective of the present invention is to provide a circuit for controlling the static power consumption of the high-voltage LDO in the voltage drop state, which can reduce the static power consumption of the high-voltage LDO in the voltage drop state.
A circuit for controlling the static power consumption of a high-voltage LDO in a voltage drop state, comprising a feedback loop and a comparator circuit electrically connected to each other, the feedback loop comprising:
a conventional high-voltage LDO circuit is used for adjusting the voltage to generate an output signal V OUT And will output signal V OUT Input to a comparator circuit;
the current limiting circuit is electrically connected with the traditional high-voltage LDO circuit and is used for controlling the current of the traditional high-voltage LDO circuit and receiving a comparison signal V output by the comparator circuit OCP2 ；
The comparator circuit includes:
a mirror current unit for providing appropriate current to each part of the circuit;
the isolation comparison unit is electrically connected with the mirror current unit and is used for comparing the external high-voltage power supply V IN Feedback loopOutput signal V of (2) OUT And isolating the voltage of the circuit element according to the comparison result to output a comparison signal V OCP2 To the current limiting circuit.
In a preferred embodiment of the present invention, the mirror current unit includes a power supply V DD Connected bias current source I B The bias current source I B The negative electrode of the low-voltage N-type MOS tube is connected with the drain electrode and the grid electrode of the low-voltage N-type MOS tube three N3, the source electrode of the low-voltage N-type MOS tube four N4, the source electrode of the low-voltage N-type MOS tube five N5 and the source electrode of the low-voltage N-type MOS tube six N6 are all grounded, and the drain electrode and the grid electrode of the low-voltage N-type MOS tube three N3 are respectively connected with the grid electrode of the low-voltage N-type MOS tube four N4, the low-voltage N-type MOS tube five N5 and the source electrode of the low-voltage N-type MOS tube six N6.
The invention relates to a preferred implementation mode, wherein the isolation comparison unit comprises a high-voltage N-type MOS tube two HN2, a high-voltage N-type MOS tube three HN3 and a high-voltage N-type MOS tube four HN4, and grid electrodes of the high-voltage N-type MOS tube two HN2, the high-voltage N-type MOS tube three HN3 and the high-voltage N-type MOS tube four HN4 are all connected with a power supply V DD The source electrode is connected with the drain electrodes of the low-voltage N-type MOS tube four N4, the low-voltage N-type MOS tube five N5 and the low-voltage N-type MOS tube six N6 respectively;
the isolation comparison unit further comprises a high-voltage P-type MOS tube two HP2, a high-voltage P-type MOS tube three HP3, a high-voltage P-type MOS tube four HP4, a zener tube one Z1 and a zener tube two Z2, wherein the drain electrode of the high-voltage N-type MOS tube two HN2 is connected with the positive electrode of the zener tube one Z1 and the grid electrode of the high-voltage P-type MOS tube four HP4, and the negative electrode of the zener tube one Z1 is connected with an external high-voltage power supply V IN Connecting;
the drain electrode of the high-voltage N-type MOS tube tri HN3 is connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube two HP2 and the drain electrode of the high-voltage P-type MOS tube tetra HP4, and the source electrode of the high-voltage P-type MOS tube two HP2 is input with an output signal V OUT ；
The drain electrode of the high-voltage N-type MOS tube four HN4 is connected with the drain electrode of the high-voltage P-type MOS tube three HP3, the grid electrode of the high-voltage P-type MOS tube three HP3 is connected with the source electrode of the high-voltage P-type MOS tube four HP4 and the positive electrode of the zener diode two Z2, and the source electrode of the high-voltage P-type MOS tube three HP3 and the negative electrode of the zener diode two Z2 are both connected with the external high-voltage power supply V IN Connecting;
the saidThe circuit between the source electrode of the high-voltage N-type MOS tube four HN4 and the drain electrode of the low-voltage N-type MOS tube six N6 outputs a comparison signal V OCP2 。
In a preferred embodiment of the present invention, the conventional high-voltage LDO circuit includes an operational amplifier EA having a non-inverting input terminal connected to a reference voltage V REF The inverting input is connected with the feedback signal V FB The output end is connected with the grid electrode of a low-voltage N-type MOS tube N1, the source electrode of the low-voltage N-type MOS tube N1 is connected with a current limiting circuit, the current limiting circuit is connected with a comparator circuit, the drain electrode of the low-voltage N-type MOS tube N1 is connected with the source electrode of a high-voltage N-type MOS tube HN1, and the grid electrode of the high-voltage N-type MOS tube HN1 is connected with a power supply V DD The drain electrode is connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube HP1, the source electrode of the high-voltage P-type MOS tube HP1 is connected with a resistor tri-R3, and the other end of the resistor tri-R3 is respectively connected with an external high-voltage power supply V IN The source electrode of the resistor four R4 and the high-voltage P-type Power tube Power are connected, the other end of the resistor four R4 is respectively connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube HP1 and the grid electrode of the high-voltage P-type Power tube Power, the drain electrode of the high-voltage P-type Power tube Power is connected with the resistor one R1 and the resistor two R2 which are connected in series, the other end of the resistor two R2 is grounded, and an output signal V is output by a circuit between the resistor one R1 and the drain electrode of the high-voltage P-type Power tube Power OUT 。
A preferred embodiment of the invention, the circuit between the resistor one R1 and the resistor two R2 outputs a feedback signal V FB 。
In a preferred embodiment of the present invention, the current limiting circuit 211 includes a low-voltage N-type MOS transistor two N2, the source electrode of the low-voltage N-type MOS transistor two N2 is grounded, and a comparison signal V is input to the gate electrode OCP2 Drain and capacitor C C The source electrode of the low-voltage N-type MOS tube N1 is connected with the capacitor C C Is connected with a resistor R at the other end C The resistance R C The other end of the first transistor is connected with the grid electrode of the second N2 of the low-voltage N-type MOS tube.
In a preferred embodiment of the invention, the width-to-length ratio of the two high-voltage P-type MOS tubes (HP 2) and the three high-voltage P-type MOS tubes (HP 3) is the same, the number ratio is N:1, and when V IN ＜V OUT When +DeltaV, the comparator circuit outputs a comparison signal V OCP2 Is reduced in voltage; wherein N is greater than 1, Δv= |v TH(HP3) |-|V TH(HP2) |，V TH(HP2) 、V TH(HP3) The threshold voltages of the two high-voltage P-type MOS transistors HP2 and the three high-voltage P-type MOS transistors HP3 are respectively.
In a preferred embodiment of the invention, when V IN ＞V OUT +V z When the high-voltage P-type MOS tube four HP4 isolates the grid voltage of the two HP2 and the grid voltage of the three HP3 of the high-voltage P-type MOS tube, so that the grid source voltage of the three HP3 of the high-voltage P-type MOS tube does not exceed V z Wherein V is z Is the reverse breakdown voltage of zener diode two Z2.
In a preferred embodiment of the present invention, the bias current source I B On the nA level.
The beneficial effects of the invention are as follows: the circuit for controlling the static power consumption of the high-voltage LDO in the voltage drop state is characterized in that when in use, when V IN -|V TH(HP3) |≥V OUT -|V TH(HP2) I, i.e. V IN ≥V OUT -|V TH(HP2) |+|V TH(HP3) I, note Δv= |v TH(HP3) |-|V TH(HP2) I, then V IN ≥V OUT +DeltaV, comparison signal V OCP2 ＝V DD -V TH(HN4) The low-voltage N-type MOS tube II N2 works in a linear region and can be regarded as a switch tube in a conducting state to output a signal V OUT Normally outputting;
V IN gradually decrease when V IN ＜V OUT In +AV, the comparison signal V OCP2 Gradually reducing the current of a branch where the low-voltage N type MOS tube II N2 is located, and operating in a subthreshold region, so that the static power consumption of the LDO in a voltage drop state is controlled;
wherein V is TH(HP2) 、V TH(HP3) 、V TH(HN4) Threshold voltages of the high-voltage P-type MOS tube two HP2, the high-voltage P-type MOS tube three HP3 and the high-voltage P-type MOS tube four HP4 are respectively obtained.
The method can control the static power consumption of the voltage drop region to the static power consumption I when the high-voltage LDO works normally Q(NOM) The following solves the problem of high-voltage LDO voltageAnd the problem of high static power consumption in the reduced state is solved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a circuit diagram of a conventional high-voltage LDO;
FIG. 2 is a circuit diagram of the present invention;
FIG. 3 is a waveform diagram of the static power consumption of a conventional high voltage LDO as a function of input voltage;
fig. 4 is a waveform diagram of static power consumption as a function of input voltage for the present invention.
Marked in the figure as: 210. a feedback loop; 211. a current limiting circuit; 220. a comparator circuit.
Detailed Description
Example 1
As shown in fig. 2, a circuit for controlling the static power consumption of the high-voltage LDO in the voltage drop state includes a feedback loop 210 and a comparator circuit 220 electrically connected to each other.
Wherein the feedback loop 210 includes a conventional high-voltage LDO circuit and a current limiting circuit 211.
Specifically, as shown in fig. 1 and 2, the conventional high-voltage LDO circuit is used for adjusting the voltage to generate an output signal V OUT And will output signal V OUT Is input to the comparator circuit 220. The conventional high-voltage LDO circuit comprises an operational amplifier EA with a non-inverting input terminal connected to a reference voltage V REF The inverting input is connected with the feedback signal V FB The output end is connected with the grid electrode of the low-voltage N-type MOS tube N1, wherein a circuit between the resistor R1 and the resistor R2 outputs a feedback signal V FB 。
The source electrode of the low-voltage N-type MOS tube N1 is connected with the current limiting circuit 211, the current limiting circuit 211 is connected with the comparator circuit 220, the drain electrode of the low-voltage N-type MOS tube N1 is connected with the source electrode of the high-voltage N-type MOS tube HN1, and the grid electrode of the high-voltage N-type MOS tube HN1 is connected with the power supply V DD The drain electrode is connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube HP1, and the source electrode of the high-voltage P-type MOS tube HPlThe pole is connected with a resistor three R3, and the other end of the resistor three R3 is respectively connected with an external high-voltage power supply V IN The resistor four R4 and the source electrode of the high-voltage P-type Power tube Power are connected, the other end of the resistor four R4 is respectively connected with the grid electrode and the drain electrode of the first HPl high-voltage P-type MOS tube and the grid electrode of the high-voltage P-type Power tube Power, the drain electrode of the high-voltage P-type Power tube Power is connected with the resistor one R1 and the resistor two R2 which are connected in series, the other end of the resistor two R2 is grounded, and an output signal V is output by a circuit between the resistor one R1 and the drain electrode of the high-voltage P-type Power tube Power OUT 。
Reference voltage V by operational amplifier EA REF And feedback signal V FB Comparing, the output of the operational amplifier EA controls the grid voltage of a low-voltage N-type MOS tube N1, and the signal is transmitted to the grid of a high-voltage P-type Power tube Power through a high-voltage P-type MOS tube HP1 to regulate the output signal V OUT Make output signal V OUT And (3) stability.
As shown in fig. 2, the current limiting circuit 211 is used for current control of the conventional high-voltage LDO circuit and receiving the comparison signal V output by the comparator circuit 220 OCP2 The current limiting circuit 211 comprises a low-voltage N-type MOS tube N2, wherein the source electrode of the low-voltage N-type MOS tube N2 is grounded, and a comparison signal V is input into the gate electrode OCP2 Drain and capacitor C C The source electrode of the low-voltage N-type MOS tube N1 is connected with the capacitor C C Is connected with a resistor R at the other end C Resistance R C The other end of the first transistor is connected with the grid electrode of the second N2 of the low-voltage N-type MOS tube.
The comparator circuit 220 includes a mirror current unit and an isolated comparison unit.
As shown in fig. 2, in particular, the mirror current unit is used for providing appropriate current for each part of the circuit, and the mirror current unit includes a power supply V DD Connected bias current source I B Bias current source I B For nA level, bias current source I B The negative electrode of the low-voltage N-type MOS transistor is connected with the drain electrode and the grid electrode of the low-voltage N-type MOS transistor tri-N3, the source electrode of the low-voltage N-type MOS transistor tetra-N4, the source electrode of the low-voltage N-type MOS transistor penta-N5 and the source electrode of the low-voltage N-type MOS transistor hexa-N6 are all grounded, and the drain electrode and the grid electrode of the low-voltage N-type MOS transistor tri-N3 are respectively connected with the low-voltage N-type MOS transistor tetra-N4, the low-voltage N-type MOS transistor penta-N5 and the low-voltage N-type MOThe grid electrode of the S tube is connected with the grid electrode of the six N6.
Further, the width-to-length ratio of the five N5 low-voltage N-type MOS tubes and the six N6 low-voltage N-type MOS tubes are the same, the number of the same mirror currents are the same, and the currents of the branches where the five N5 low-voltage N-type MOS tubes and the six N6 low-voltage N-type MOS tubes are located are equal to I B 。
As shown in fig. 2, in particular, the isolation comparison unit is used for comparing the external high voltage power supply V IN And the output signal V of the feedback loop 210 OUT And isolating the voltage of the circuit element according to the comparison result to output a comparison signal V OCP2 To the current limiting circuit 211. The name of the isolation comparison unit is named because the unit has the functions of isolation and comparison, and has no special meaning.
The isolation comparison unit comprises a high-voltage N-type MOS tube two HN2, a high-voltage N-type MOS tube three HN3 and a high-voltage N-type MOS tube four HN4, and the grid electrodes of the high-voltage N-type MOS tube two HN2, the high-voltage N-type MOS tube three HN3 and the high-voltage N-type MOS tube four HN4 are all connected with a power supply V DD The source electrode is connected with the drain electrodes of the low-voltage N-type MOS tube four N4, the low-voltage N-type MOS tube five N5 and the low-voltage N-type MOS tube six N6 respectively; the isolation comparison unit further comprises a high-voltage P-type MOS tube two HP2, a high-voltage P-type MOS tube three HP3, a high-voltage P-type MOS tube four HP4, a zener tube one Z1 and a zener tube two Z2, wherein the drain electrode of the high-voltage N-type MOS tube two HN2 is connected with the positive electrode of the zener tube one Z1 and the grid electrode of the high-voltage P-type MOS tube four HP4, and the negative electrode of the zener tube one Z1 is connected with an external high-voltage power supply V IN And (5) connection.
The drain electrode of the high-voltage N-type MOS tube three HN3 is connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube two HP2 and the drain electrode of the high-voltage P-type MOS tube four HP4, and the source electrode of the high-voltage P-type MOS tube two HP2 is input with an output signal V OUT The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the high-voltage N-type MOS tube four HN4 is connected with the drain electrode of the high-voltage P-type MOS tube three HP3, the grid electrode of the high-voltage P-type MOS tube three HP3 is connected with the source electrode of the high-voltage P-type MOS tube four HP4 and the positive electrode of the zener diode two Z2, and the source electrode of the high-voltage P-type MOS tube three HP3 and the negative electrode of the zener diode two Z2 are both connected with the external high-voltage power supply V IN Connecting; the circuit between the source electrode of the high-voltage N-type MOS tube four HN4 and the drain electrode of the low-voltage N-type MOS tube six N6 outputs a comparison signal V OCP2 。
Further, when V IN ＞V OUT +V z During the process, the four HP4 of the high-voltage P-type MOS tube can isolate the grid voltage of the two HP2 of the high-voltage P-type MOS tube from the grid voltage of the three HP3 of the high-voltage P-type MOS tube, so that the grid source voltage of the three HP3 of the high-voltage P-type MOS tube does not exceed V z Wherein V is z Is the reverse breakdown voltage of zener diode two Z2.
When in use, the two HP2 of the high-voltage P-type MOS tube and the three HP3 of the high-voltage P-type MOS tube are arranged to have the same width-to-length ratio, the number ratio is N:1, and V is defined TH(HP2) 、V TH(HP3) 、V TH(HN4) Threshold voltages of the high-voltage P-type MOS tube two HP2, the high-voltage P-type MOS tube three HP3 and the high-voltage P-type MOS tube four HP4 are respectively obtained.
When V is IN -|V TH(HP3) |≥V OUT -|V TH(HP2) I, i.e. V IN ≥V OUT -|V TH(HP2) |+|V TH(HP3) I, let Δv= |v TH(HP3) |-|V TH(HP2) I, then VI N ≥V OUT +ΔV, comparison signal V output from comparator circuit 220 OCP2 At the highest, V OCP2 ＝V DD -V TH(HN4) The low-voltage N-type MOS transistor two N2 works in a linear region, the low-voltage N-type MOS transistor two N2 can be regarded as a switch tube in a conducting state, and the output signal V output by the feedback loop 210 OUT The feedback signal V is generated by dividing the voltage of the resistor I R1 and the resistor II R2 FB And will feed back the signal V FB Into the inverting input of the operational amplifier EA to enable the feedback signal V FB With reference voltage V input at non-inverting input REF Comparing, the output of the operational amplifier EA controls the grid voltage of a low-voltage N-type MOS tube N1, and transmits signals to the grid of a high-voltage P-type Power tube Power through a high-voltage P-type MOS tube HP1 so as to adjust the output signal V OUT The feedback loop 210 is not affected by the two N2 of the low-voltage N-type MOS tube, and outputs a signal V OUT The output is stabilized, at this time,
Figure BDA0003996878970000071
when V is IN ＜V OUT At +ΔV, the comparator circuit 220 outputs a comparison signal V OCP2 Is low and the voltage is lowThe second N2 of the N-type MOS tube works in a subthreshold region, the current of the branch where the second N2 of the low-voltage N-type MOS tube is positioned is limited to be reduced, the grid voltage of the Power of the high-voltage P-type Power tube is increased, and a signal V is output OUT Decrease, compare signal V OCP2 And the negative feedback is formed by increasing, so that balance is realized. Thus, when V IN ＜V OUT When +DeltaV, the signal V is compared OCP2 And the current is not 0, but the current of the branch where the low-voltage N type MOS transistor II N2 is located is reduced when the low-voltage N type MOS transistor II N2 enters a subthreshold region.
As shown in FIG. 4, the circuit controls the static power consumption of the voltage drop region to the static power consumption I when the high voltage LD0 is in normal operation Q(NOM) The problem of high static power consumption in the high-voltage LDO voltage drop state is solved.
The foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A circuit for controlling the quiescent power consumption of a high-voltage LDO in a voltage drop state, comprising a feedback loop (210) and a comparator circuit (220) electrically connected to each other, the feedback loop (210) comprising:
a conventional high-voltage LDO circuit is used for adjusting the voltage to generate an output signal V OUT And will output signal V oUT Input to a comparator circuit (220);
the current limiting circuit (211) is electrically connected with the traditional high-voltage LDO circuit and is used for controlling the current of the traditional high-voltage LDO circuit and receiving the comparison signal V output by the comparator circuit (220) OCO2 ；
The comparator circuit (220) comprises:
a mirror current unit for providing appropriate current to each part of the circuit;
isolation ofThe comparison unit is electrically connected with the mirror current unit and is used for comparing the external high-voltage power supply V IN And the output signal V of the feedback loop (210) OUT And isolating the voltage of the circuit element according to the comparison result to output a comparison signal V OCP2 To a current limiting circuit (211).
2. The circuit for controlling static power consumption in a high-voltage LDO drop state according to claim 1, wherein the mirror current unit comprises a power supply V DD Connected bias current source I B The bias current source I B The negative electrode of the low-voltage N-type MOS tube is connected with the drain electrode and the grid electrode of the low-voltage N-type MOS tube three N3, the source electrode of the low-voltage N-type MOS tube four N4, the source electrode of the low-voltage N-type MOS tube five N5 and the source electrode of the low-voltage N-type MOS tube six N6 are all grounded, and the drain electrode and the grid electrode of the low-voltage N-type MOS tube three N3 are respectively connected with the grid electrode of the low-voltage N-type MOS tube four N4, the low-voltage N-type MOS tube five N5 and the source electrode of the low-voltage N-type MOS tube six N6.
3. The circuit for controlling static power consumption in a high-voltage LDO drop state according to claim 1, wherein the isolation comparison unit comprises a high-voltage N-type MOS tube two HN2, a high-voltage N-type MOS tube three HN3 and a high-voltage N-type MOS tube four HN4, wherein the grid electrodes of the high-voltage N-type MOS tube two HN2, the high-voltage N-type MOS tube three HN3 and the high-voltage N-type MOS tube four HN4 are all connected with a power supply V DD The source electrode is connected with the drain electrodes of the low-voltage N-type MOS tube four N4, the low-voltage N-type MOS tube five N5 and the low-voltage N-type MOS tube six N6 respectively;
the isolation comparison unit further comprises a high-voltage P-type MOS tube two HP2, a high-voltage P-type MOS tube three HP3, a high-voltage P-type MOS tube four HP4, a zener tube one Z1 and a zener tube two Z2, wherein the drain electrode of the high-voltage N-type MOS tube two HN2 is connected with the positive electrode of the zener tube one Z1 and the grid electrode of the high-voltage P-type MOS tube four HP4, and the negative electrode of the zener tube one Z1 is connected with an external high-voltage power supply V IN Connecting;
the drain electrode of the high-voltage N-type MOS tube tri HN3 is connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube two HP2 and the drain electrode of the high-voltage P-type MOS tube tetra HP4, and the source electrode of the high-voltage P-type MOS tube two HP2 is input with an output signal V OUT ；
The drain electrode of the high-voltage N-type MOS tube four HN4 is connected with the drain electrode of the high-voltage P-type MOS tube three HP3, the grid electrode of the high-voltage P-type MOS tube three HP3 is connected with the source electrode of the high-voltage P-type MOS tube four HP4 and the positive electrode of the zener diode two Z2, and the source electrode of the high-voltage P-type MOS tube three HP3 and the negative electrode of the zener diode two Z2 are both connected with the external high-voltage power supply V IN Connecting;
the circuit between the source electrode of the high-voltage N-type MOS tube four HN4 and the drain electrode of the low-voltage N-type MOS tube six N6 outputs a comparison signal V OCP2 。
4. The circuit for controlling static power consumption in a high-voltage LDO drop state according to claim 1, wherein said conventional high-voltage LDO circuit comprises an operational amplifier EA having a non-inverting input terminal connected to a reference voltage V REF The inverting input is connected with the feedback signal V FB The output end is connected with the grid electrode of a low-voltage N-type MOS tube N1, the source electrode of the low-voltage N-type MOS tube N1 is connected with a current limiting circuit (211), the current limiting circuit (211) is connected with a comparator circuit (220), the drain electrode of the low-voltage N-type MOS tube N1 is connected with the source electrode of a high-voltage N-type MOS tube HN1, and the grid electrode of the high-voltage N-type MOS tube HN1 is connected with a power supply V DD The drain electrode is connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube HP1, the source electrode of the high-voltage P-type MOS tube HP1 is connected with a resistor tri-R3, and the other end of the resistor tri-R3 is respectively connected with an external high-voltage power supply V IN The source electrode of the resistor four R4 and the high-voltage P-type Power tube Power are connected, the other end of the resistor four R4 is respectively connected with the grid electrode and the drain electrode of the high-voltage P-type MOS tube HP1 and the grid electrode of the high-voltage P-type Power tube Power, the drain electrode of the high-voltage P-type Power tube Power is connected with the resistor one R1 and the resistor two R2 which are connected in series, the other end of the resistor two R2 is grounded, and an output signal V is output by a circuit between the resistor one R1 and the drain electrode of the high-voltage P-type Power tube Power OUT 。
5. The circuit for controlling static power consumption in a high-voltage LDO drop state according to claim 4, wherein the circuit between resistor one R1 and resistor two R2 outputs a feedback signal V FB 。
6. The circuit for controlling static power consumption in a high-voltage LDO drop state according to claim 4, wherein the current limiting circuit (211) comprises a low-voltage N-type MOS transistor N2, the source electrode of the low-voltage N-type MOS transistor N2 is grounded, and a comparison signal V is input to the gate electrode OCP2 Drain and capacitor C C The source electrode of the low-voltage N-type MOS tube N1 is connected with the capacitor C C Is connected with a resistor R at the other end C The resistance R C The other end of the first transistor is connected with the grid electrode of the second N2 of the low-voltage N-type MOS tube.
7. The circuit for controlling the static power consumption in the high-voltage LDO voltage drop state according to claim 1, wherein the width-to-length ratio of the two high-voltage P-type MOS transistors two HP2 and the three high-voltage P-type MOS transistors three HP3 is the same, and the number ratio is N:1, when V IN <V OUT At +DeltaV, the comparator circuit (220) outputs a comparison signal V OCP2 Is reduced in voltage; wherein N is greater than 1, Δv= |v TH() |-V TH() |，V TH() 、V TH() The threshold voltages of the two high-voltage P-type MOS transistors HP2 and the three high-voltage P-type MOS transistors HP3 are respectively.
8. The circuit for controlling static power consumption in a high-voltage LDO drop state of claim 1, wherein when V IN >V OUT +V z When the high-voltage P-type MOS tube four HP4 isolates the grid voltage of the two HP2 and the grid voltage of the three HP3 of the high-voltage P-type MOS tube, so that the grid source voltage of the three HP3 of the high-voltage P-type MOS tube does not exceed V z Wherein V is z Is the reverse breakdown voltage of zener diode two Z2.
9. The circuit for controlling the quiescent power consumption of a high-voltage LDO drop state of claim 2, wherein the bias current source I B On the nA level.
CN202211604453.6A 2022-12-13 2022-12-13 Circuit for controlling static power consumption of high-voltage LDO in voltage drop state Pending CN116301142A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118169436A (en) * 2024-05-14 2024-06-11 南京星问科技有限公司 Method and device for low noise test of equipment to be tested based on LDO test circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118169436A (en) * 2024-05-14 2024-06-11 南京星问科技有限公司 Method and device for low noise test of equipment to be tested based on LDO test circuit

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