CN116300378A - Frequency self-adaptive time-digital conversion circuit - Google Patents

Abstract

The frequency self-adaptive time digital conversion circuit comprises a phase discriminator, a digital-to-analog converter, an oscillator, 8 counters, 8 AND gates and digital logic, wherein the output end of each AND gate is connected with the input end of one counter, the output ends of all the counters are connected with the digital logic, the counters are divided into 4 groups, the oscillator outputs 4 signals, two AND gates of the same group of counters are respectively input, the phase discriminator has 2 input ends, input signals of the circuit are respectively received, the phase discriminator outputs 2 signals, two AND gates of the same group of counters are respectively input, the digital logic outputs 6 signals, 5 signals serve as output signals of the circuit, 1 signal is input into the digital-to-analog converter, the digital-to-analog converter outputs current to the oscillator, and the frequency of the output signals of the oscillator is controlled.

Description

Frequency self-adaptive time-digital conversion circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a design technology of a time-to-digital conversion circuit.

Background

Whether the sundial is used for ancient times or the resonator is used for precisely defining seconds nowadays, the sundial can be regarded as a part of timing technology. Throughout the history of scientific development, the layered timing technology has played an important role in various fields. The field of electronics is no exception: the digital circuit needs stable clock, each module of the circuit system cooperates and divides work and needs strict time sequence control, and various interface protocols also use the requirement of time sequence as the key part.

The TDC is used for detecting the delay difference between two clocks with the same frequency and different phases in an integrated circuit, and the working principle is as shown in figure 1, clk1 and clk2 are two clock signals with the same frequency and have T _D Time delay difference of (2), TDC detection T _D A digital code Dout is generated in proportion thereto. In many TDC documents, the clock signal clk1 with a leading phase is referred to as a start signal, and the clock signal clk2 with a lagging phase is referred to as a stop signal, so as to represent the phase relationship between the two signals.

Several metrics should be of interest in TDC applications: what interval range the input clock frequency of the TDC is? What is the minimum resolution LSB of the TDC? Whether or not the LSB of the TDC varies with process corner, supply voltage, temperature (collectively PVT)?

The conventional TDC is designed to have a focus on reducing LSB so as to obtain higher quantization accuracy. As is common for interpolation TDCs, vernier TDCs, which can reduce the LSB to within one inverter delay, they have in common that the internal oscillator always oscillates at the highest frequency, which is not adjustable. Since the oscillation frequency of the oscillator varies greatly with PVT, the LSB of the conventional TDC also varies with PVT. The same input signal has different output values measured by a conventional TDC under different PVT conditions.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a frequency self-adaptive time-to-digital conversion circuit for measuring the time interval between two working steps of other circuits, and in order to achieve the purposes, the invention adopts the following technical scheme.

The circuit comprises a phase discriminator, a digital-to-analog converter, an oscillator, 8 counters, 8 AND gates and digital logic, wherein the output end of each AND gate is connected with the input end of one counter, the output ends of all the counters are connected with the digital logic, the counters are divided into 4 groups, the oscillator outputs 4 signals, the two AND gates of the same group of counters are respectively input, the phase discriminator has 2 input ends, the input signals of the circuit are respectively received, the phase discriminator outputs 2 signals, the two AND gates of the same group of counters are respectively input, the digital logic outputs 6 signals, 5 signals are used as the output signals of the circuit, 1 signal is input into the digital-to-analog converter, the digital-to-analog converter outputs current to the oscillator, and the frequency of the output signals of the oscillator is controlled.

The high-frequency oscillation signal generated by the oscillator is used as a time reference, and the counter is used for measuring how many times the oscillation occurs in the oscillator within a given delay difference, so that the accurate value of the delay difference is obtained.

The digital logic and the digital-analog converter form a loop, 8 measured values are operated, a control signal is output, the frequency of the oscillator is regulated in an internal closed loop, the self-adaptive change of the time-digital converter is realized in a certain range, the LSB is automatically regulated to an optimal working state, the regulation by people is not needed, and the PVT stability of the measured result of the circuit is ensured.

The number of the digital logic output signals is 5, and the digital logic output signals are respectively a period measurement value, a delay difference measurement value, a locking state indication, an oscillator frequency too high indication and an oscillator frequency too low indication, so that more information is output, and the circuit fault detection method is beneficial to the fault detection when the circuit is abnormal in working state.

The two signals to be measured are input into the phase discriminator to generate the delay difference and the period length of the two input signals, the delay difference is measured, the clock period is also measured, the counters are paired, the accuracy of circuit measurement is guaranteed, and under the condition that the period of the input signals is known, the accurate value of the delay difference can be obtained through a proportional method.

The 8 counters and AND gates form 4 identical modules, work in parallel at the same time, cooperate with multiphase signals generated by the oscillator, average for 4 times of measurement, reduce errors, and reduce the measurement errors of TDC from the system level.

Drawings

Fig. 1 is a TDC operation principle, fig. 2 is a circuit configuration principle, fig. 3 is an adaptive processing flow, fig. 4 is a test flow, and fig. 5 is an input-output waveform.

Description of the embodiments

The technical scheme of the invention is specifically described below with reference to the accompanying drawings.

The circuit is constructed in a manner such that the input signals start and stop are input to the phase detector, clk_ref and clk_det are output, and osc0, osc1, osc2, osc3 are output from the oscillator, as shown in fig. 2. osc0 corresponds to the first group of counters 0r and 0d, osc1 corresponds to the second group of counters 1r and 1d, osc2 corresponds to the third group of counters 2r and 2d, osc3 corresponds to the fourth group of counters 3r and 3d, clk_ref corresponds to the counters 0r, 1r, 2r, 3r, clk_det corresponds to the counters 0d, 1d, 2d, 3d,4 groups of counters are driven by oscillation signals osc0, osc1, osc2, osc3, osc0, and high level times of clk_ref and clk_det are measured, and 4 groups of measured values ref_cnt0< N:0> and det_cnt0< N:0>, ref_cnt1< N:0> and det_cnt2< N:0> and det_cnt0< N > are output, respectively.

The digital logic calculates a period measurement value start_period < M:0>, a measurement value start2stop < M:0>, an internal signal dac_code < X:0>, of the start from 4 sets of measurement values, and displays a locked state tdc_lock, an oscillator frequency too high, and an oscillator frequency too low.

The process flow of the digital logic is shown in FIG. 3, when the start_period < M:0> reaches the upper limit, the dac_code < X:0> is subtracted by 1, when the start_period < M:0> reaches the lower limit, the dac_code < X:0> is added by 1, the start_period < M:0> is other values, the tdc_lock is set to 1, when the dac_code reaches the lower limit, the over_high is set to 1, when the dac_code reaches the upper limit, the over_low is set to 1, the dac output current Ibias is controlled by the dac_code < X:0>, and the frequencies of the oscillation signals osc0, osc1, osc2 and osc3 are adjusted.

As shown in fig. 4, if tdd_lock is not 1, it is determined that over_high, if 1, if 0, it is determined that over_low is manually turned down, if 1, it is manually turned up, if 0, it is waited for circuit adaptive adjustment, if tdd_lock is 1, it is possible to read start_period < M:0> and start2stop < M:0>, calculate the rising edge time difference between start and stop by start signal period x (start 2stop < M:0 >)/(start_period < M:0 >), observe waveform diagrams corresponding to input and output signals, and verify the above procedure, as shown in fig. 5.

The foregoing is illustrative of the present invention and is not to be construed as limiting thereof, but rather as being included within the spirit and scope of the present invention.

Claims (5)

1. A frequency adaptive time-to-digital conversion circuit, comprising: the circuit comprises a phase discriminator, a digital-to-analog converter, an oscillator, 8 counters, 8 AND gates and digital logic, wherein the output end of each AND gate is connected with the input end of one counter, the output ends of all the counters are connected with the digital logic, the counters are divided into 4 groups, the oscillator outputs 4 signals, the two AND gates of the same group of counters are respectively input, the phase discriminator has 2 input ends, the input signals of the circuit are respectively received, the phase discriminator outputs 2 signals, the two AND gates of the same group of counters are respectively input, the digital logic outputs 6 signals, 5 signals are used as the output signals of the circuit, 1 signal is input into the digital-to-analog converter, the digital-to-analog converter outputs current to the oscillator, and the frequency of the output signals of the oscillator is controlled.

2. The frequency adaptive time-to-digital conversion circuit of claim 1, further comprising: the input signals start and stop are input to the phase detector, the clk_ref and clk_det are output, the oscillator outputs osc0, osc1, osc2, osc3, osc0 corresponds to the first group of counters 0r and 0d, osc1 corresponds to the second group of counters 1r and 1d, osc2 corresponds to the third group of counters 2r and 2d, osc3 corresponds to the fourth group of counters 3r and 3d, clk_ref corresponds to the counter 0r, counter 1r, counter 2r, counter 3r, clk_det corresponds to the counter 0d, counter 1d, counter 2d, and 4 groups of counters are driven by the oscillation signals osc0, osc1, osc2, osc3, and 4 groups of counters output 4 groups of measured values_c0N:0 and det_c0:0:1:1:N_c0:1:2:2:4:2:4:4:4:1:2:1:1:2:0:0:3:0:0:0:3:0:0:0 respectively.

3. The frequency adaptive time to digital conversion circuit according to claim 2, wherein the digital logic calculates a period measurement value of start_period < M:0>, a measurement value of start-to-stop delay difference, start2stop < M:0>, an internal signal dac_code < X:0>, and indicates a lock state tdc_lock, an oscillator frequency too high, and an oscillator frequency too low from 4 sets of measurement values.

4. The frequency adaptive time to digital conversion circuit of claim 3, further comprising: when the start_period < M:0> reaches the upper limit, the dac_code < X:0> is subtracted by 1, when the start_period < M:0> reaches the lower limit, the dac_code < X:0> is added by 1, and the start_period < M:0> is other values, the tdc_lock is set 1, when the dac_code reaches the lower limit, the over_high is set 1, when the dac_code reaches the upper limit, the over_low is set 1, the dac output current Ibias is controlled by the dac_code < X:0>, and the frequencies of the oscillation signals osc0, osc1, osc2, osc3 and osc0 are adjusted.

5. The frequency adaptive time-to-digital conversion circuit of claim 4, further comprising: if the tdc_lock is not 1, it is determined that over_high, if 1, ibias is manually turned down, if 0, it is determined that over_low, if 1, ibias is manually turned up, if 0, it is waited for circuit self-adaptation adjustment, if tdc_lock is 1, start_period < M:0> and start2stop < M:0> are read, and the rising edge time difference between start and stop is calculated by start signal period x (start 2stop < M:0 >)/(start_period < M:0 >).

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