CN116260454B - Jitter separation device and clock recovery instrument - Google Patents

Abstract

The invention provides a jitter separation device and a clock recovery instrument, and relates to the technical field of electronics. The jitter separation apparatus includes: the device comprises a phase discriminator, a jitter separation module, a voltage-controlled oscillator and a data processing module; the input end of the phase discriminator is used for receiving an input signal, and the output end of the phase discriminator is connected with the input end of the jitter separation module; the jitter separation module is used for extracting a clock signal corresponding to an output signal of the phase discriminator, and performing jitter separation on the clock signal to obtain a first jitter component and a second jitter component corresponding to an input signal; the data processing module is used for carrying out jitter analysis on the first jitter component and the second jitter component, and determining frequency characteristics corresponding to the first jitter component and frequency characteristics corresponding to the second jitter component. The jitter separation device and the clock recovery instrument provided by the invention can be used for performing jitter separation on the clock signal extracted from the output signal of the phase discriminator, and can be used for effectively performing jitter analysis on the obtained jitter component, so that the accuracy of the jitter analysis is improved.

Description

Jitter Separator and Clock Recovery Instrument

technical field

The invention relates to the field of electronic technology, in particular to a jitter separation device and a clock recovery instrument.

Background technique

The traditional jitter separation needs to rely on the jitter analysis function of the oscilloscope, and the analysis accuracy is low, and when the jitter separation of the input high-speed signal is performed through the oscilloscope, special measuring instruments and corresponding options are required, which are expensive and inconvenient to use. Because high-speed oscilloscopes often require the support of ultra-high-speed analog-to-digital converters (Analog to Digital Converter, ADC), the number of effective quantization bits is low, and small jitter cannot be resolved, and the amplitude resolution of large jitter is insufficient.

Contents of the invention

The invention provides a jitter separation device and a clock recovery instrument, which are used to solve the technical problem of low jitter separation accuracy in the prior art.

The invention provides a shaking separation device, comprising:

Phase detector, jitter separation module, voltage controlled oscillator and data processing module;

The input end of the phase detector is used to receive an input signal, and the output end of the phase detector is connected to the input end of the jitter separation module;

The first output end of the jitter separation module is connected to the data processing module, and the second output end of the jitter separation module is connected to the input end of the voltage-controlled oscillator;

The jitter separation module is used to extract a clock signal corresponding to the output signal of the phase detector, and perform jitter separation on the clock signal to obtain a first jitter component and a second jitter component corresponding to the clock signal;

The data processing module is configured to perform jitter analysis on the first jitter component and the second jitter component, and determine a frequency feature corresponding to the first jitter component and a frequency feature corresponding to the second jitter component.

In some embodiments, the jitter separation module includes a first submodule and a second submodule; the first submodule is used to obtain the first jitter component based on a fixed loop bandwidth; the second submodule The module is used to obtain the second jitter component based on the variable loop bandwidth;

The input end of the first submodule is connected to the output end of the phase detector, the first output end of the first submodule is connected to the data processing module, and the second output end of the first submodule connected to the input end of the second submodule;

The first output terminal of the second submodule is connected to the data processing module, and the second output terminal of the second submodule is connected to the input terminal of the voltage-controlled oscillator.

In some embodiments, the first submodule includes a first loop filter and a first emitter follower;

The input end of the first loop filter is connected to the output end of the phase detector, the first output end of the first loop filter is connected to the input end of the first emitter follower, and the The output end of the first emitter follower is connected to the data processing module, and the second output end of the first loop filter is connected to the input end of the second sub-module;

Wherein, the first loop filter has the fixed loop bandwidth.

In some embodiments, the second submodule includes a second loop filter and a second emitter follower;

The input end of the second loop filter is connected to the second output end of the first sub-module, the first output end of the second loop filter is connected to the input end of the second emitter follower connected, the output end of the second emitter follower is connected to the data processing module, and the second output end of the second loop filter is connected to the voltage controlled oscillator;

Wherein, the second loop filter has the variable loop bandwidth.

In some embodiments, the first loop filter includes: a first integral filter, a first capacitor and a fixed value resistor;

The input end of the first integration filter is respectively connected to the output end of the phase detector and the first end of the fixed value resistor, and the second end of the fixed value resistor is connected to the first end of the first capacitor. The second end of the first capacitor is connected to the output end of the first integration filter and the input end of the first emitter follower respectively, and the output end of the first integration filter is connected to the input end of the first emitter follower. The input terminal of the second sub-module is connected.

In some embodiments, the second loop filter includes: a second integral filter, a second capacitor, and an adjustable resistor;

The input terminal of the second integrating filter is respectively connected to the second output terminal of the first sub-module and the first terminal of the adjustable resistor, and the second terminal of the adjustable resistor is connected to the second capacitor connected to the first terminal of the second capacitor, the second terminal of the second capacitor is respectively connected to the output terminal of the second integration filter and the input terminal of the second emitter follower, and the output of the second integration filter The terminal is connected with the input terminal of the voltage controlled oscillator.

In some embodiments, the data processing module includes a first analog-to-digital converter, a second analog-to-digital converter, FPGA and MCU;

The first output end of the first sub-module is connected to the input end of the first analog-to-digital converter, the output end of the first analog-to-digital converter is connected to the FPGA, and the output end of the FPGA is connected to the The input terminal connection of the MCU;

The first output end of the second sub-module is connected to the input end of the second analog-to-digital converter, the output end of the second analog-to-digital converter is connected to the FPGA, and the output end of the FPGA is connected to the The input terminals of the MCU are connected.

The present invention also provides a clock recovery instrument, including: the above-mentioned jitter separation device.

The jitter separation device and the clock recovery instrument provided by the present invention obtain the first jitter component and the second jitter component corresponding to the clock signal by extracting the clock signal corresponding to the output signal of the phase detector and performing jitter separation on the clock signal, and Effective jitter analysis can be performed on the collected first jitter component and the second jitter component, thereby improving the accuracy of jitter analysis.

Description of drawings

In order to more clearly illustrate the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are the present invention. For some embodiments of the invention, those skilled in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is one of structural representations of the jitter separation device provided by the present invention;

Fig. 2 is the second structural diagram of the jitter separation device provided by the present invention;

Fig. 3 is a schematic structural diagram of the clock recovery instrument provided by the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

The jitter separation device and the clock recovery instrument of the present invention will be described below with reference to FIGS. 1-3 .

Fig. 1 is one of the structural schematic diagrams of the jitter separation device provided by the present invention. Referring to FIG. 1 , the jitter separation device provided by the present invention includes: a phase detector 110 , a jitter separation module 120 , a voltage-controlled oscillator 130 and a data processing module 140 .

The input end of the phase detector 110 is used to receive the input signal, and the output end of the phase detector 110 is connected to the input end of the jitter separation module 120;

The first output end of the jitter separation module 120 is connected to the data processing module 140, and the second output end of the jitter separation module 120 is connected to the input end of the voltage-controlled oscillator 130;

The jitter separation module 120 is configured to extract a clock signal corresponding to the output signal of the phase detector 110, and perform jitter separation on the clock signal to obtain a first jitter component and a second jitter component corresponding to the clock signal;

The data processing module 140 is configured to perform jitter analysis on the first jitter component and the second jitter component, and determine a frequency feature corresponding to the first jitter component and a frequency feature corresponding to the second jitter component.

In actual implementation, the input signal received by the input terminal of the phase detector 110 includes a pseudo-random data signal and a signal output by a voltage controlled oscillator 130 (Voltage Controlled Oscillator, VCO). The phase detector 110 is used to compare the phases of the two signals, determine the phase difference between the two signals, and convert the phase difference into a corresponding voltage control signal. The voltage control signal is the output signal of the phase detector 110 .

The voltage-controlled oscillator 130 is an oscillator circuit whose output frequency corresponds to an input control voltage, that is, the output frequency of the voltage-controlled oscillator 130 is controlled by the input voltage.

After the output terminal of the phase detector 110 outputs the voltage control signal, the voltage control signal is input to the jitter separation module 120 .

The output of the jitter separation module 120 is divided into two channels, one is input to the data processing module 140 for jitter analysis, and the other is input to the voltage-controlled oscillator 130 for locking with the input high-speed data.

The jitter separation module 120 may perform jitter separation on the periodic clock signal corresponding to the voltage control signal based on different loop bandwidths, and then obtain the first jitter component and the second jitter component corresponding to the clock signal.

The data processing module 140 can perform jitter analysis on the first jitter component and the second jitter component, calculate the frequency feature corresponding to the first jitter component and the frequency feature corresponding to the second jitter component, and can also calculate the relative power.

In actual implementation, the data processing module 140 may include an Analog to Digital Converter (Analog to Digital Converter, ADC), a Field Programmable Gate Array (Field Programmable Gate Array, FPGA) and a Microcontroller Unit (Microcontroller Unit, MCU).

The first output end of the jitter separation module 120 is connected to the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is connected to the FPGA, and the output end of the FPGA is connected to the input end of the MCU.

The ADC is used to collect the analog signal output by the jitter separation module 120, and convert the collected analog signal into a discrete digital signal, that is, convert the first jitter component and the second jitter component into corresponding digital signals.

After the FPGA obtains the digital signal corresponding to the first jitter component and the digital signal corresponding to the second jitter component, it performs Fourier decomposition on the above digital signals respectively, and converts the time domain signal into a frequency domain signal.

The MCU analyzes the frequency domain signal corresponding to the first jitter component and the frequency domain signal corresponding to the second jitter component, and can obtain the frequency characteristics and relative power corresponding to the first jitter component, and the frequency characteristics and relative power corresponding to the second jitter component .

The jitter separation device provided by the present invention obtains the first jitter component and the second jitter component corresponding to the clock signal by extracting the clock signal corresponding to the output signal of the phase detector and performing jitter separation on the clock signal, and can analyze the collected Effective jitter analysis is performed on the first jitter component and the second jitter component, improving the accuracy of jitter analysis.

Fig. 2 is the second structural schematic diagram of the jitter separation device provided by the present invention. Referring to Figure 2,

In some embodiments, the jitter separation module 120 includes a first submodule 210 and a second submodule 220 .

The first submodule 210 is used to acquire the first jitter component based on the fixed loop bandwidth; the second submodule 220 is used to acquire the second jitter component based on the variable loop bandwidth;

The input end of the first submodule 210 is connected with the output end of the phase detector 110, the first output end of the first submodule 210 is connected with the data processing module 140, the second output end of the first submodule 210 is connected with the second submodule 220 input connection;

The first output terminal of the second sub-module 220 is connected to the data processing module 140 , and the second output terminal of the second sub-module 220 is connected to the input terminal of the voltage-controlled oscillator 130 .

In actual implementation, the first sub-module 210 has a fixed loop bandwidth and is used to analyze the original jitter component of the input signal, that is, the first jitter component.

The second sub-module 220 has a variable loop bandwidth. Since loop bandwidths of different devices under test (Device Under Test, DUT) are different, the second sub-module 220 sets a variable loop bandwidth to simulate the loop bandwidth of the device under test.

The second sub-module 220 is used to analyze the real jitter component after the output signal of the phase detector passes through the fixed-bandwidth loop and the device under test, that is, the second jitter component. Wherein, the loop bandwidth of the second sub-module 220 can be set according to actual detection requirements, and is not specifically limited here.

The jitter separation device provided by the present invention, by collecting the jitter components separated by the first sub-module and the second sub-module, compared with directly collecting the input high-speed signal, greatly reduces the burden on the sampler Analog bandwidth requirements and requirements for signal processing capabilities.

As shown in FIG. 2, in some embodiments, the first submodule 210 includes a first loop filter 2100 and a first emitter follower 2101;

The input end of the first loop filter 2100 is connected with the output end of the phase detector 110, the first output end of the first loop filter 2100 is connected with the input end of the first emitter follower 2101, and the first emitter follower The output end of the filter 2101 is connected to the data processing module 140, and the second output end of the first loop filter 2100 is connected to the input end of the second sub-module 220;

Wherein, the first loop filter 2100 has a fixed loop bandwidth.

In actual implementation, the first loop filter 2100 is a fixed loop filter, that is, the loop bandwidth does not change. The first loop filter 2100 can filter out the high-frequency components including the frequency of the input signal in the output signal of the phase detector 110, so as to improve the anti-interference capability of the loop.

The first emitter follower 2101 is a common-collector amplifying circuit, and its main function is to amplify the alternating current to improve the load carrying capacity of the entire amplifying circuit. In actual circuits, it is generally used as an output stage or an isolation stage. It is characterized by high input impedance and low output impedance, so the current required from the signal source is small and the load capacity is strong.

In the present invention, the first emitter follower 2101 is used to connect the first loop filter 2100 and the analog-to-digital converter in the data processing module 140, so as to reduce the influence caused by the direct connection between circuits and play a buffering role.

As shown in FIG. 2, in some embodiments, the second submodule 220 includes a second loop filter 2200 and a second emitter follower 2201;

The input end of the second loop filter 2200 is connected to the second output end of the first sub-module 210, the first output end of the second loop filter 2200 is connected to the input end of the second emitter follower 2201, and the second The output end of the emitter follower 2201 is connected to the data processing module 140, and the second output end of the second loop filter 2200 is connected to the voltage controlled oscillator 130;

Wherein, the second loop filter 2200 has a variable loop bandwidth.

In actual implementation, the second loop filter 2200 is a variable loop filter, that is, the loop bandwidth can be changed. According to user detection requirements, the loop bandwidth of the second loop filter 2200 can be changed to obtain the required loop bandwidth and gain, so as to meet the needs of various applications.

The second emitter follower 2201 is a common-collector amplifying circuit, and its main function is to amplify the AC current to improve the load carrying capacity of the entire amplifying circuit. In actual circuits, it is generally used as an output stage or an isolation stage. It is characterized by high input impedance and low output impedance, so the current required from the signal source is small and the load capacity is strong.

In the present invention, the second emitter follower 2201 is used to connect the second loop filter 2200 and the analog-to-digital converter in the data processing module 140, so as to reduce the influence caused by the direct connection between circuits and play a buffering role.

As shown in FIG. 2 , in some embodiments, the first loop filter 2100 includes: a first integrating filter 2102, a first capacitor C ₁ and a fixed value resistor R ₁ ;

The input end of the first integrating filter 2102 is respectively connected with the output end of the phase detector 110 and the first end of the fixed value resistor _R1 , and the second end of the fixed value resistor _R1 is connected with the first end of the first capacitor _C1 , the second end of the first capacitor _C1 is respectively connected to the output end of the first integral filter 2102 and the input end of the first emitter follower 2101, and the output end of the first integral filter 2102 is connected to the second sub-module 220 input connection.

In actual implementation, the first integral filter 2102 has the characteristics of a low-pass filter, and at the same time, the phase-frequency characteristics also have the function of leading correction. The first integral filter 2102 may be an active proportional integral filter.

The capacitance value of the first capacitor C ₁ is a fixed value, and the capacitance value of the first capacitor C ₁ and the resistance value of the fixed-value resistor R ₁ can be set according to actual detection requirements, which are not specifically limited here.

The first loop filter 2100 does not change the loop bandwidth, and can be used to analyze the original jitter component of the input signal.

As shown in FIG. 2 , in some embodiments, the second loop filter 2200 includes: a second integrating filter 2202, a second capacitor C ₂ and an adjustable resistor R ₂ ;

The input end of the second integrating filter 2202 is respectively connected to the second output end of the first sub-module 210 and the first end of the adjustable resistor _R2 , and the second end of the adjustable resistor _R2 is connected to the second end of the second capacitor _C2 . Connected at one end, the second end of the second capacitor _C2 is respectively connected to the output end of the second integral filter 2202 and the input end of the second emitter follower 2201, and the output end of the second integral filter 2202 is connected to the voltage-controlled oscillation connected to the input of device 130.

In actual implementation, the second integral filter 2202 has the characteristics of a low-pass filter, and at the same time, the phase-frequency characteristics also have the function of leading correction. The second integral filter 2202 may be an active proportional integral filter.

In the second loop filter 2200, by adjusting the resistance value of the adjustable resistor _R2 , the loop gain can be changed, and thus the loop bandwidth of the second loop filter 2200 can be changed. Changing the loop bandwidth can simulate the loop bandwidth of the device under test, and then analyze the real jitter component of the output signal of the phase detector 110 after passing through the fixed loop filter and the device under test.

The capacitance value of the second capacitor _C2 is a fixed value, and the capacitance value of the second capacitor _C2 can be set according to actual detection requirements, which is not specifically limited here.

As shown in Figure 2, in some embodiments, the data processing module 140 includes a first analog-to-digital converter 1401, a second analog-to-digital converter 1402, FPGA1403 and MCU1404;

The first output end of the first sub-module 210 is connected to the input end of the first analog-to-digital converter 1401, the output end of the first analog-to-digital converter 1401 is connected to the FPGA1403, and the output end of the FPGA1403 is connected to the input end of the MCU1404;

The first output end of the second sub-module 220 is connected to the input end of the second analog-to-digital converter 1402 , the output end of the second analog-to-digital converter 1402 is connected to the FPGA 1403 , and the output end of the FPGA 1403 is connected to the input end of the MCU 1404 .

The first analog-to-digital converter 1401 is used to convert the collected analog signal into a discrete digital signal, that is, to collect the first jitter component output by the first sub-module 210, and convert the first jitter component into a corresponding digital signal .

The second analog-to-digital converter 1402 is used to convert the collected analog signal into a discrete digital signal, that is, to collect the first jitter component output by the second sub-module 220, and convert the second jitter component into a corresponding digital signal .

After the FPGA1403 obtains the digital signal corresponding to the first jitter component and the digital signal corresponding to the second jitter component, it performs Fourier decomposition on the digital signals respectively, and converts the time-domain signal into a frequency-domain signal. FPGA1403 sends the frequency domain signal to MCU1404 through the advanced extensible interface protocol (Advanced eXtensible Interface, AXI) bus interface.

MCU1404 analyzes the frequency domain signal corresponding to the first jitter component and the frequency domain signal sum corresponding to the second jitter component, and can obtain the frequency characteristics and relative power corresponding to the first jitter component, and the frequency characteristics and relative power corresponding to the second jitter component. power.

In conjunction with Fig. 2, the working principle of the jitter separation device provided by the present invention is described as a whole below:

The output signal of the phase detector 110 first passes through the fixed loop filter, and the output of this stage is divided into two paths, one of which is buffered by the first emitter follower 2101 and then sent to the first analog-to-digital converter 1401 to collect data, and the FPGA1403 obtains the data Afterwards, Fourier decomposition is performed to convert the time-domain signal into a frequency-domain signal. The other signal is sent to the variable loop filter, and the output of the variable loop filter is divided into two paths. One path is buffered by the second emitter follower 2201 and then sent to the second analog-to-digital converter 1402 to collect data. FPGA1403 obtains the data Perform Fourier decomposition to convert the time-domain signal into a frequency-domain signal; the other channel is given to the voltage-controlled oscillator 130 for locking with the input high-speed data.

The jitter separation device provided by the present invention, by collecting the jitter components on the fixed loop filter and the variable loop filter, compared with directly collecting the input high-speed signal, it greatly reduces the sampling frequency. The analog bandwidth requirements of the device and the requirements for signal processing capabilities. Therefore, a relatively low-speed analog-to-digital converter can be used for acquisition. Compared with an analog-to-digital converter with dozens of G samples, the effective number of bits of a low-speed analog-to-digital converter can be extended from 6 bits to 14 bits or even higher. The resolution ability is greatly enhanced.

Fig. 3 is a schematic structural diagram of the clock recovery instrument provided by the present invention. Referring to FIG. 3 , the clock recovery instrument 300 includes the jitter separation device 310 in the above-mentioned embodiment. For example, the jitter separation device shown in FIG. 1 to FIG. 2 may be included.

The jitter separation device shown in FIG. 1 to FIG. 2 has been described in the above embodiments, and will not be repeated here.

In the related art, the existing clock recovery instrument cannot analyze the jitter of the input signal, and the source of the jitter cannot be effectively judged after the clock recovered signal is sent to the sampling oscilloscope.

The clock recovery instrument provided by the present invention extracts the periodic clock signal from the complex pseudo-random data signal, and separates the clock signal by jitter, so that the frequency and relative power after the jitter separation can be calculated more accurately, so as to realize the analysis of the input signal jitter analysis.

The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.

Through the above description of the implementations, those skilled in the art can clearly understand that each implementation can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic Disks, CDs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (8)

1. A shaking separation device, characterized in that, comprising: Phase detector, jitter separation module, voltage controlled oscillator and data processing module; The input end of the phase detector is used to receive an input signal, and the output end of the phase detector is connected to the input end of the jitter separation module; The first output end of the jitter separation module is connected to the data processing module, and the second output end of the jitter separation module is connected to the input end of the voltage-controlled oscillator; The jitter separation module is used to extract the clock signal corresponding to the output signal of the phase detector based on different loop bandwidths, and perform jitter separation on the clock signal to obtain the first jitter component corresponding to the clock signal and the second dither component; The data processing module is configured to perform jitter analysis on the first jitter component and the second jitter component, and determine a frequency characteristic corresponding to the first jitter component and a frequency characteristic corresponding to the second jitter component; The jitter separation module includes a first submodule and a second submodule; the first submodule is used to obtain the first jitter component based on a fixed loop bandwidth; the second submodule is used to obtain the first jitter component based on a variable A loop bandwidth of , obtaining the second jitter component; The first submodule includes a first loop filter and a first emitter follower; wherein, the first loop filter has the fixed loop bandwidth; The second sub-module includes a second loop filter and a second emitter follower; wherein, the second loop filter has the variable loop bandwidth. 2. The jitter separation device according to claim 1, wherein the input terminal of the first submodule is connected to the output terminal of the phase detector, and the first output terminal of the first submodule is connected to the The data processing module is connected, and the second output terminal of the first submodule is connected with the input terminal of the second submodule; The first output terminal of the second submodule is connected to the data processing module, and the second output terminal of the second submodule is connected to the input terminal of the voltage-controlled oscillator. 3. The jitter separation device according to claim 2, wherein the input end of the first loop filter is connected to the output end of the phase detector, and the first loop filter of the first loop filter The output end is connected to the input end of the first emitter follower, the output end of the first emitter follower is connected to the data processing module, and the second output end of the first loop filter is connected to the The input terminal of the second sub-module is connected. 4. The jitter separation device according to claim 2, wherein the input end of the second loop filter is connected to the second output end of the first sub-module, and the second loop filter The first output end of the second emitter follower is connected to the input end of the second emitter follower, the output end of the second emitter follower is connected to the data processing module, and the second output of the second loop filter The terminal is connected with the voltage controlled oscillator. 5. The jitter separation device according to claim 3, wherein the first loop filter comprises: a first integral filter, a first capacitor and a fixed value resistor; The input end of the first integration filter is respectively connected to the output end of the phase detector and the first end of the fixed value resistor, and the second end of the fixed value resistor is connected to the first end of the first capacitor. The second end of the first capacitor is connected to the output end of the first integration filter and the input end of the first emitter follower respectively, and the output end of the first integration filter is connected to the input end of the first emitter follower. The input terminal of the second sub-module is connected. 6. The jitter separation device according to claim 4, wherein the second loop filter comprises: a second integral filter, a second capacitor and an adjustable resistor; The input terminal of the second integrating filter is respectively connected to the second output terminal of the first sub-module and the first terminal of the adjustable resistor, and the second terminal of the adjustable resistor is connected to the second capacitor connected to the first terminal of the second capacitor, the second terminal of the second capacitor is respectively connected to the output terminal of the second integration filter and the input terminal of the second emitter follower, and the output of the second integration filter The terminal is connected with the input terminal of the voltage controlled oscillator. 7. The jitter separation device according to any one of claims 2-6, wherein the data processing module comprises a first analog-to-digital converter, a second analog-to-digital converter, an FPGA, and an MCU; The first output end of the first sub-module is connected to the input end of the first analog-to-digital converter, the output end of the first analog-to-digital converter is connected to the FPGA, and the output end of the FPGA is connected to the The input terminal connection of the MCU; The first output end of the second sub-module is connected to the input end of the second analog-to-digital converter, the output end of the second analog-to-digital converter is connected to the FPGA, and the output end of the FPGA is connected to the The input terminals of the MCU are connected. 8. A clock recovery instrument, characterized by comprising: the jitter separation device according to any one of claims 1-7.