CN116247078A - Mixed channel compound semiconductor device - Google Patents

Abstract

The present invention discloses a mixed channel compound semiconductor device, wherein a groove-shaped gate electrode of the device realizes a normally-off compound semiconductor device by controlling a vertical electron channel and a transverse electron channel. The device avoids the risk of high-voltage short circuit caused by using the normally-open compound semiconductor transistor in the power module, and can safely and fully exert the advantages of high efficiency and high voltage resistance of the compound semiconductor transistor in power electronics.

Description

A mixed channel compound semiconductor device

This application is a divisional application of an invention with a filing date of June 20, 2018, an application number of "201810631911.2", and an invention title of "a hybrid channel compound semiconductor device".

technical field

The invention relates to the technical field of semiconductors, in particular to a mixed channel compound high voltage device.

Background technique

Power electronic switch modules are widely used in power electronics and power supplies, and are the basic functional modules in current DC/DC and AC/DC conversions.

Traditional solid-state power electronic switching modules are implemented using silicon materials. Due to the constraints of the basic properties of silicon materials, its performance has approached the limit of improvement in terms of module efficiency, heat dissipation, and speed.

The use of compound semiconductor materials, such as gallium nitride, to construct power electronic switching modules has become a development trend in the power electronics industry. This is because compound semiconductor materials have the characteristics of high withstand voltage, low resistance, and low capacitance, and have the potential to improve performance by hundreds or thousands of times compared to silicon.

Compound semiconductor power electronic modules face a challenge that is not present in silicon material modules - that is, normally-off compound semiconductor power transistors are difficult to obtain. Most compound semiconductor transistors are normally-on devices. The disadvantage of building a power module using only normally-on compound semiconductor devices is that the safety of the module is not guaranteed.

Specifically, for a normally open device, it is necessary to provide a negative voltage to the control terminal to ensure that the device is turned off. In the natural state when the system is not powered on, the normally open device is turned on. As a result, in the case of failure of the negative voltage control module, there is a normally open device that cannot block the high voltage and provides a path from the high voltage to the ground, which may cause dangerous situations such as system short circuit and burnout.

One solution to this problem is to manufacture normally-off compound semiconductor transistors. Compound semiconductor device companies are trying their best to try this way. For example, US patent US8193562B2 describes a structure that uses P-type gate technology to achieve a normally-off compound semiconductor power transistor.

Contents of the invention

Based on this, it is necessary to provide an enhanced compound high-voltage device that can effectively solve the problem of having a positive threshold voltage.

A mixed channel compound field effect transistor, comprising a substrate and a buffer layer, a first channel layer, a first potential barrier layer, a second channel layer, and a second potential barrier layer sequentially stacked on the substrate ; from the upper surface of the second barrier layer, a groove-shaped gate deposition region penetrating to the lower surface of the second barrier layer but not exceeding the lower surface of the first barrier layer is provided, And on both sides of the gate deposition area, there are respectively provided source deposition areas that penetrate to no more than the lower surface of the second barrier layer, and penetrate from the upper surface of the second barrier layer to more than The lower surface of the second barrier layer but not exceeding the drain deposition region on the lower surface of the first barrier layer; the mixed channel compound field effect transistor also includes a gate dielectric layer, a gate layer, and a source layer and a drain layer, wherein the gate dielectric layer covers the bottom and side surfaces of the gate deposition region and extends to both sides to above the second barrier layer; the gate layer extends from the gate above the gate dielectric layer on one side of the electrode deposition region, and extend along the gate dielectric layer to above the gate dielectric layer on the other side; the source layer and the drain layer are separated from the source The bottom of the electrode deposition region and the bottom of the drain deposition region extend to above the barrier layer along the corresponding sides; wherein, through the second channel layer and the gate deposition region, the The path of electron flow in the vertical direction of the second channel layer, thereby introducing a vertical channel; at the same time, realizing a horizontal two-dimensional electron gas in the first channel layer and the second channel layer respectively, thereby introducing a lateral channel channel; wherein, the gate layer can control the magnitude of current in the lateral channel and the vertical channel in the second channel layer through the electric field through the gate dielectric layer.

In one embodiment, on one side of the source deposition region, more than one groove-shaped gate deposition region and source deposition region are arranged.

In one embodiment, the source deposition regions form a two-dimensional array, and the two-dimensional arrays are separated by groove-shaped gate deposition regions.

In one of the embodiments, the source deposition region and the surrounding semiconductor are separated by the groove-shaped gate deposition region to form a two-dimensional array whose unit horizontal cross-section is but not limited to circular, square, and hexagonal .

In one embodiment, the thickness of the first barrier layer is 2 nm to 100 nm.

In one embodiment, the first barrier layer comprises _{AlxGa1 -xN} material, where X is between 0 and 1, including 0 and 1 itself.

In one of the embodiments, the first channel layer includes GaN material.

In one embodiment, the material of the first channel layer contains impurity doping.

In one embodiment, the second channel layer includes GaN material.

In one embodiment, the thickness of the second channel layer is 2 nanometers to 10 micrometers.

In one embodiment, the material of the second channel layer contains impurity doping.

In one embodiment, the thickness of the second barrier layer is 2 nanometers to 100 nanometers.

In one embodiment, the second barrier layer comprises _{AlxGa1 -xN} material, where X is between 0 and 1, including 0 and 1 itself.

In one embodiment, the gate dielectric is but not limited to one or a combination of SiO ₂ , SiN, Al ₂ O ₃ , AlN, HfO ₂ , and Ga ₂ O ₃ , with a thickness of 0.5 nanometers to 100 nanometers.

Due to the implementation of the above technical solutions, the present invention has the following advantages compared with the prior art: the compound device in the present invention has two kinds of vertical and lateral channel combinations, and the total threshold voltage can be achieved by controlling the threshold voltage of these two channels positive effect. Specifically, by introducing the second channel layer and the groove-shaped gate deposition region, a path for electrons flowing in the vertical direction through the second channel layer is introduced, thereby introducing a vertical channel; at the same time, in the first barrier layer and the second Below the second barrier layer, due to the piezoelectric effect, a horizontal two-dimensional electron gas is respectively realized in the first channel layer and the second channel layer, thereby introducing a lateral channel. The threshold voltages of the two channels are controlled by the different crystal orientations and surface states of the channel surface.

Description of drawings

Fig. 1 is a cross-sectional structure diagram of a mixed channel compound device.

Figure 2 is a cross-sectional view of a mixed channel compound device with repeating groove-shaped gate deposition regions.

Figure 3 is a top view of a mixed channel compound device with repeating groove-shaped gate deposition regions.

Figure 4 is a top view of a mixed channel compound device with repeating groove-shaped gate deposition regions.

Wherein the shape of the drain electrode (8) is hexagonal.

Figure 5 is a top view of a mixed channel compound device with repeating groove-shaped gate deposition regions.

Wherein the shape of the drain electrode (8) is circular.

Detailed ways

In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

It should be noted that when an element is referred to as being “disposed on” another element, it may be directly on the other element or there may also be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in FIG. 1 , a mixed channel compound field effect transistor according to one embodiment includes a substrate 1 and a buffer layer 2 , a first channel layer 3 , a first barrier layer 4 , and a first barrier layer 4 sequentially stacked on the substrate 1 . The second channel layer 5 and the second barrier layer 6 .

In this embodiment, the mixed channel compound device is provided with a groove-shaped gate deposition region 102 penetrating from the upper surface of the second barrier layer 6 to the lower surface of the first barrier layer 4, and Both sides of the gate deposition region 102 are respectively provided with a source deposition region (103) formed to penetrate to the lower surface of the second barrier layer 6, and to penetrate from the upper surface of the second barrier layer 6 to not exceed the second barrier layer 6. A drain deposition region 104 on the lower surface 4 of the barrier layer.

The hybrid channel compound field effect transistor further includes a drain layer 7 , a source layer 8 , a gate dielectric layer 9 and a gate layer 10 . Wherein, the gate dielectric layer 9 covers the bottom surface and two sides of the gate deposition region 102 and extends to both sides to the top of the second barrier layer 6 .

The gate layer 10 extends from above the gate dielectric layer 9 on one side of the gate deposition region 102 along the gate dielectric layer 9 to above the gate dielectric layer 9 on the other side.

In a specific embodiment, more than one groove-shaped gate deposition region 102 and source deposition region 103 are arranged on one side of the source deposition region 103 .

In a specific embodiment, the source deposition regions 103 form a two-dimensional array, and the two-dimensional arrays are separated by groove-shaped gate deposition regions 102 .

In a specific embodiment, the source deposition region 103 and surrounding semiconductors are separated by the gate deposition region 102 into a two-dimensional array of unit horizontal cross-sections including but not limited to circles, squares, and hexagons.

In a specific embodiment, the thickness of the first barrier layer 4 is 2 nm to 100 nm.

In a specific embodiment, the first barrier layer 4 comprises _{AlxGa1 -xN} material, where X is between 0 and 1, including 0 and 1 itself.

In a specific embodiment, the first channel layer 3 includes GaN material.

In a specific embodiment, the material of the first channel layer 3 contains impurity doping.

In a specific embodiment, the second channel layer 5 includes GaN material.

In a specific embodiment, the thickness of the second channel layer 5 is 2 nanometers to 10 micrometers.

In a specific embodiment, the material of the second channel layer 5 contains impurity doping.

In a specific embodiment, the thickness of the second barrier layer 6 is 2 nanometers to 100 nanometers.

In a specific embodiment, the second barrier layer 6 comprises _{AlxGa1 -xN} material, where X is between 0 and 1, including 0 and 1 itself.

In a specific embodiment, the gate dielectric 9 is but not limited to one or a combination of SiO ₂ , SiN, Al ₂ O ₃ , AlN, HfO ₂ , and Ga ₂ O ₃ , with a thickness of 0.5 nm to 100 nm. Nano.

Compared with the traditional technology, the compound device in the present invention has a combination of vertical and lateral channels, and the total threshold voltage can be positive by controlling the threshold voltages of these two channels. Specifically, by introducing the second channel layer and the groove-shaped gate deposition region, a path for electrons flowing in the vertical direction through the second channel layer is introduced, thereby introducing a vertical channel; at the same time, in the first barrier layer and the second Below the second barrier layer, due to the piezoelectric effect, a horizontal two-dimensional electron gas is respectively realized in the first channel layer and the second channel layer, thereby introducing a lateral channel. The threshold voltages of the two channels are controlled by the different crystal orientations and surface states of the channel surface.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (14)

1. A mixed channel compound field effect transistor, comprising a substrate and a buffer layer, a first channel layer, a first potential barrier layer, a second channel layer, and a second potential layer stacked successively on the substrate layer; A groove-shaped gate deposition region is provided from the upper surface of the second barrier layer to penetrate beyond the lower surface of the second barrier layer but not beyond the lower surface of the first barrier layer, and On both sides of the gate deposition region, there are respectively provided source deposition regions that penetrate to no more than the lower surface of the second barrier layer, and penetrate from the upper surface of the second barrier layer to exceed the the lower surface of the second barrier layer but not beyond the drain deposition region on the lower surface of the first barrier layer; The hybrid channel compound field effect transistor also includes a gate dielectric layer, a gate layer, a source layer, and a drain layer, wherein the gate dielectric layer covers the bottom and side surfaces of the gate deposition region, and the outer side extends above the second barrier layer; The gate layer extends from above the gate dielectric layer on one side of the gate deposition region along the gate dielectric layer to above the gate dielectric layer on the other side; The source layer and the drain layer respectively extend from the bottom of the source deposition region and the bottom of the drain deposition region along the corresponding sides to above the second barrier layer; Wherein, through the second channel layer and the gate deposition region, a path for electrons flowing in the vertical direction through the second channel layer is introduced, thereby introducing a vertical channel; at the same time, respectively in the first channel A horizontal two-dimensional electron gas is realized in the layer and the second channel layer, thereby introducing a lateral channel; Wherein, the gate layer can control the current in the lateral channel and the vertical channel in the second channel layer through the electric field through the gate dielectric layer. 2. The hybrid channel compound field effect transistor according to claim 1, characterized in that it has more than one groove-shaped gate deposition region and source deposition region. 3 . The hybrid channel compound field effect transistor according to claim 1 , wherein the source deposition regions are separated into a two-dimensional array by the gate deposition regions. 4 . 4 . The hybrid channel compound field effect transistor according to claim 3 , wherein the horizontal cross-section of the array unit of the two-dimensional array comprises a circle, a square, and a hexagon. 5. The hybrid channel compound field effect transistor according to claim 1, wherein the thickness of the first barrier layer is 2 nm to 100 nm. 6. The hybrid channel compound field effect transistor according to claim 1, wherein the first barrier layer comprises _{AlxGa1 -} xN material, wherein X is between 0 and 1, including 0 and 1 itself. 7. The hybrid channel compound field effect transistor of claim 1, wherein the first channel layer comprises GaN material. 8. The hybrid channel compound field effect transistor according to claim 1, wherein the material of the first channel layer contains impurity doping. 9. The hybrid channel compound field effect transistor of claim 1, wherein the second channel layer comprises GaN material. 10. The hybrid channel compound field effect transistor according to claim 1, wherein the thickness of the second channel layer is 2 nanometers to 10 micrometers. 11. The hybrid channel compound field effect transistor according to claim 1, wherein the material of the second channel layer contains impurity doping. 12. The hybrid channel compound field effect transistor according to claim 1, wherein the thickness of the second barrier layer is 2 nm to 100 nm. 13. The hybrid channel compound field effect transistor according to claim 1, wherein the second barrier layer comprises _{AlxGa1 -} xN material, wherein X is between 0 and 1, including 0 and 1 itself. 14. The hybrid channel compound field effect transistor according to claim 1, wherein the gate dielectric comprises one of SiO ₂ , SiN, Al ₂ O ₃ , AlN, HfO ₂ , and Ga ₂ O ₃ Or a combination of several, with a thickness of 0.5 nanometers to 100 nanometers.

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