CN116243844B

CN116243844B - Method for accessing system memory and processing circuit arranged on network card

Info

Publication number: CN116243844B
Application number: CN202111484555.4A
Authority: CN
Inventors: 林嘉宏
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-12-07
Filing date: 2021-12-07
Publication date: 2025-09-16
Anticipated expiration: 2041-12-07
Also published as: CN116243844A

Abstract

The present invention discloses a method for accessing a system memory, which includes the following steps: reading a description unit from the system memory, wherein the description unit includes a buffer start address field and a buffer size field, wherein the buffer start address field includes the start address of the buffer in the system memory, and the buffer size field includes the size of the buffer; receiving a plurality of data packets, and writing the plurality of data packets into the buffer; modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit only includes information of a portion of the plurality of data packets or does not include information of any of the plurality of data packets; and writing the modified description unit into the system memory.

Description

Method for accessing system memory and processing circuit arranged on network card

Technical Field

The invention relates to a method for accessing a system memory.

Background

When the electronic device receives the network data packet from the outside, the network data packet and the related analysis information are temporarily stored in the system memory for subsequent processing. In storing the parsing information, one of the following two ways is mainly to configure a complete continuous memory space in the system memory, and use the parsing information of each data packet as the header of the data packet to store in the memory space. However, since each packet must be stored in the memory space continuously, and the number of packet processes increases due to the rapid increase in network connection speed, it is difficult to find a complete continuous and large memory space in the system memory. In order to solve the problem of the first way, the second way is to use a plurality of description units (descriptors) to describe a plurality of data packets respectively, and each data packet can be stored in a different address in the system memory, and the processor can know the address of the data packet in the system memory through the pointer of the corresponding description unit. However, although the second method may not require a complete continuous memory space in the system memory, if a large number of small data packets are received, the number of times of reading and writing of the description unit is too frequent, which results in waste of bandwidth and insufficient bandwidth, and thus the data packets cannot be efficiently transmitted.

Disclosure of Invention

It is therefore an object of the present invention to provide a method for accessing a system memory, which can effectively reduce the number of times of reading and writing using a description unit without configuring a complete continuous memory space in the system memory, so as to solve the problems described in the prior art.

In one embodiment of the invention, a method for accessing a system memory is disclosed, comprising the steps of reading a description unit from the system memory, wherein the description unit comprises a buffer start address field and a buffer size field, wherein the buffer start address field comprises a start address of a buffer in the system memory and the buffer size field comprises a size of the buffer, receiving a plurality of data packets and writing the plurality of data packets into the buffer, modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit comprises information of only a portion of the plurality of data packets or information of no data packet in the plurality of data packets, and writing the modified description unit into the system memory.

In one embodiment of the invention, a processing circuit disposed on a network card is disclosed for reading a description unit from a system memory external to the network card, wherein the description unit comprises a buffer start address field and a buffer size field, wherein the buffer start address field comprises a start address of a buffer in the system memory, and the buffer size field comprises a size of the buffer, receiving a plurality of data packets and writing the plurality of data packets into the buffer, modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit comprises information of only a part of the plurality of data packets or information of no data packet in the plurality of data packets, and writing the modified description unit into the system memory.

Drawings

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a description unit prepared by a central processing unit and a modified description unit generated by a processing circuit.

FIG. 3 is a diagram illustrating a modified description unit and a corresponding buffer according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a modified description unit and a corresponding buffer according to another embodiment of the invention.

FIG. 5 is a method of accessing system memory according to one embodiment of the invention.

Detailed Description

Fig. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the invention. As shown in fig. 1, the electronic device 100 includes a network card 110, a system memory 120, a central processing unit 130 and a storage unit 140, wherein the network card 110 includes a processing circuit 112 and a network connector 114, the network connector 114 is used for connecting to the network cable 102, the system memory 120 can be implemented by using a static random access memory (Static Random Access Memory, SRAM) or a dynamic random access memory (Dynamic Random Access Memory, DRAM), the system memory 120 includes a plurality of areas, one area is used for storing a plurality of description units 122_1 to 122_n, each of the description units 122_1 to 122_n is respectively used for pointing to a plurality of buffers 124_1 to 124_n, and the storage unit 140 includes at least one driver 142, wherein the driver 142 is used for executing operations related to the network card 110. In the present embodiment, the electronic device 100 may be any electronic device that needs to use network functions, such as a desktop computer, a notebook computer, etc., and the network card 110 may be built into or externally connected to the electronic device 100.

In the present embodiment, each of the description units 122_1 to 122_n has a fixed size, for example, 16 bytes or 32 bytes, and in one embodiment, the description units 122_1 to 122_n are located at fixed addresses in the system memory 120, and the description units 122_1 to 122_n are consecutive in memory addresses, but the invention is not limited thereto. In another embodiment, the description units 122_1 to 122_n do not have to have a fixed address in the system memory 120, and the description units 122_1 to 122_n do not have to be consecutive in memory addresses, as long as the description unit can indicate the memory address of the next description unit, for example, the description unit 122_1 contains information pointing to the starting memory address of the description unit 122_2. In addition, the addresses of the plurality of buffers 124_1-124_N in the system memory 120 are not fixed, and the buffers 124_1-124_N may be discontinuous with each other in memory addresses.

In the operation of the electronic device 100, the cpu 130 reads the driver 142 from the storage unit 140, and executes the driver 142 to start the operation related to the network card 110, i.e. to receive the data packet received from the network card 110 via the network cable 102, or to transmit the data to other electronic devices via the network card 110. In addition, the system memory 120 is used to temporarily store network data packets from outside, data that needs to be transmitted to other electronic devices through the network card 110, or other system data. Since the present invention focuses on providing a method for storing data packets and related information, the following embodiments are described only with respect to the content of the electronic device 100 that receives network data packets from outside and stores the network data packets in the system memory 120.

First, the CPU 130 prepares the contents of the description units 122_1 to 122_N in the system memory 120, wherein the description units 122_1 to 122_N are used for describing the information of the corresponding buffers 124_1 to 124_N, respectively. For example, referring to the schematic diagram of the description unit 122_1 shown in fig. 2, the description unit 122_1 includes at least three fields, namely an own bit field, a buffer start address field and a buffer size field, wherein the control bit field is used to indicate whether the description unit 122_1 is currently available for the network card 110, for example, the cpu 130 sets the control bit to "0" to indicate that the network card 110 can currently use the description unit 122_1 and the corresponding buffer 124_1, the buffer start address field is used to indicate the start address of the buffer 124_1 in the system memory 120, and the buffer size field is used to indicate the capacity of the buffer 124_1. Similarly, each of the remaining description units 122_2-122_n may have the same structure, e.g., the description unit 122_2 includes a control bit corresponding to the buffer 124_2, a buffer start address, and a buffer size, and so on.

In one embodiment, the buffers 124_1-124_N do not have a fixed address, for example, the buffer 124_1 may have a different address when the CPU 130 prepares the contents of the description unit 122_1 next time, and the start address of the buffer in the description unit 122_1 is different accordingly. In one embodiment, the size of each buffer 124_1-124_n is greater than or equal to the maximum data size of one ethernet packet, for example, 1.5 Kilobytes (KB), but the invention is not limited thereto. In other embodiments, the size of each buffer 124_1-124_n may be smaller than the maximum data size of one ethernet packet.

Then, when the processing circuit 112 of the network card 110 receives one or more data packets from the outside, the processing circuit 112 sequentially reads the description units 122_1 to 122_n to determine which description unit is available for the processing circuit 112, for example, the processing circuit 112 sequentially reads the control bits in the description units 122_1 to 122_n, and selects the description unit with the control bit of "0" to perform subsequent operations. For convenience of description, the following embodiment is illustrated with the processing circuit 112 selecting the description unit 122_1.

After reading the description unit 122_1, the processing circuit 112 determines how many currently received data packets can be stored in the buffer 124_1 according to the buffer size of the buffer 124_1 recorded in the description unit 122_1. Taking fig. 3 as an example for illustration, assuming that the data packets #0 to #2 are currently received and the total data amount of the data packets #0 to #2 is smaller than the size of the buffer 124_1 after adding the relevant header #0 to #2, the processing circuit 112 may establish a corresponding header according to each data packet to record the information of the data packet and write the header together with the data Bao Yi into the buffer 124_1. Specifically, the processing circuit 112 may establish a header #0 of the packet #0, wherein the header #0 records a size and related information of the packet #0, such as an error check code like a checksum (checksum), and sequentially and continuously write the header #0 and the packet #0 to the buffer 124_1, then the processing circuit 112 establishes a header #1 of the packet #1, wherein the header #1 records a size and related information of the packet #1, and sequentially and continuously writes the header #1 and the packet #1 to the buffer 124_1, wherein the header #1 immediately follows the packet #0, then the processing circuit 112 establishes a header #2 of the packet #2, wherein the header #2 records a size and related information of the packet #2, and sequentially and continuously writes the header #2 and the packet #2 to the buffer 124_1, wherein the header #2 immediately follows the packet # 1.

In the present embodiment, since the size of the next data packet received by the processing circuit 112 is larger than the remaining space of the buffer 124_1, the processing circuit 112 does not continue to store the next data packet in the buffer 124_1, and the remaining space of the buffer 124_1 can remain blank without storing any data or store invalid data.

After the data packets #0 to #2 are written into the buffer 124_1, the processing circuit 112 modifies the content of the read description unit 122_1 so that the modified description unit 112_1_a includes at least four fields, which are a control bit field, a first packet information field, a multi-packet tag field, and a total data amount/total data packet number field, respectively. In this embodiment, the control bit may have a bit "1" to indicate that the corresponding buffer 124_1 has stored a data packet, and may also be used to inform the cpu 130 that the buffer 124_1 has only stored a data packet, the first data packet information field may include the start address of the header #0 of the data packet #0, that is, the start address of the buffer 124_1, the multi-data packet tag field may be used to indicate whether the buffer 124_1 stores a plurality of data packets, for example, the multi-data packet tag may be represented by a single bit, and the multi-data packet tag of "1" indicates that the buffer 124_1 currently stores two or more data packets, and the multi-data packet tag of "0" indicates that the buffer 124_1 currently stores only one data packet, and the total data/total data packet number field records the data amount of all data currently stored in the buffer 124_1, or the number of data packets stored in the buffer 124_1, for example, three data packets stored in the buffer 124_1 shown in fig. 3.

After the processing circuit 112 modifies the description unit 122_1, the processing circuit 112 stores the modified description unit 112_1_a back to the original address of the description unit 122_1 in the system memory 120, i.e., the processing circuit 112 uses the modified description unit 112_1_a to overwrite the description unit 122_1.

Next, the cpu 130 reads and analyzes the control bits in the description units 122_1 to 122_n, and reads the description unit with the control bit "1". In the present embodiment, the cpu 130 reads the modified description unit 112_1_a, and sequentially reads the header #0, the data packet #0, the header #1, the data packet #1, the header #2, and the data packet #2 in the buffer 124_1 according to the information in the modified description unit 112_1_a for subsequent processing. In the present embodiment, since the modified description unit 112_1_a provides the multi-packet tag field and the total data amount/total data packet number field, the cpu 130 can accurately know how much data or how many data packets need to be read from the buffer 124_1.

After the cpu 130 successfully reads the data in the buffer 124_1, the cpu 130 may additionally re-modify the modified description unit 112_1_a to the description unit 112_1, for example, use the original description unit 112_1 to overwrite the modified description unit 112_1_a for use when the processing circuit 112 of the network card 110 stores the subsequent data packet.

In the above embodiment, since the buffer area pointed by the single description unit can allow storing a plurality of data packets, the cpu 130 does not need to prepare too many description units 122_1 to 122_n in the system memory 120 for receiving a large number of small data packets, so that the space configured in the system memory 120 for storing the description units 122_1 to 122_n can be greatly reduced. In addition, although one buffer may allow a plurality of data packets to be stored, since related information (i.e., a header) of the data packets is also stored in the buffer, the description unit may not need to describe related information of each data packet in the buffer, so that the size of the description unit may be effectively reduced to avoid occupying excessive space in the system memory 120.

In the embodiment of fig. 2 and 3, the buffer 124_1 sequentially stores the header #0, the packet #0, the header #1, the packet #1, the header #2, and the packet #2, and the start address of the header #0 is pointed out by the first packet information in the modified description unit 112_1_a. However, in other embodiments, referring to fig. 4, the first packet information field in the modified describing unit 112_1_a may directly include the related information of the packet #0, such as the size of the packet #0 and the error check code, and the buffer 124_1 itself does not need to store the related information of the packet #0, i.e. the buffer 124_1 stores the packet #0, the header #1, the packet #1, the header #2, and the packet #2 in sequence. Such design variations are intended to fall within the scope of the present invention.

FIG. 5 is a method of accessing system memory according to one embodiment of the present invention, while referring to the description of the above embodiment, the flow of FIG. 5 is as follows.

And 500, starting the flow.

Step 502, the central processing unit configures a plurality of description units and a plurality of corresponding buffers in the system memory.

Step 504, the processing circuit of the network card reads one of the description units.

In step 506, the processing circuit stores one or more data packets and their headers in buffers corresponding to the description units.

The processing circuit modifies 508 the description unit according to the one or more data packets stored in the buffer to generate a modified description unit.

The processing circuitry writes the modified description unit to system memory, step 510.

The foregoing description is only of the preferred embodiments of the present invention, and all the equivalent changes and modifications made by the claims of the present invention fall within the protection scope of the present invention.

Reference numerals illustrate:

100 electronic device

102 Network cable

110 Network card

112 Processing circuitry

114 Network connector

120 System memory

122_1 To 122_N descriptive unit

122_1_A modified description Unit

124_1 To 124_N buffer area

130 Central processing unit

140 Memory cell

142 Driver program

Claims

1. A method for accessing a system memory, comprising:

Reading a description unit from the system memory, wherein the description unit comprises a buffer start address field and a buffer size field, wherein the buffer start address field comprises a start address of a buffer in the system memory, and the buffer size field comprises a size of the buffer;

receiving a plurality of data packets, and writing the plurality of data packets into the buffer;

Modifying the description unit according to the plurality of data packets written into the buffer to generate a modified description unit, wherein the modified description unit only includes information of a portion of the plurality of data packets or does not include information of any of the plurality of data packets; and

The modified description unit is written to the system memory.

2. The method of claim 1 , wherein the step of receiving a plurality of data packets and writing the plurality of data packets into the buffer comprises:

generating headers for the plurality of data packets respectively, wherein the header of each data packet includes information of the data packet; and

The plurality of data packets, together with the corresponding headers, are sequentially written into the buffer.

3. The method of claim 2 , wherein the step of modifying the description unit according to the plurality of data packets written to the buffer to generate the modified description unit comprises:

The description unit is modified according to the multiple data packets written to the buffer to add a first data packet information field and a total data volume/total number of data packets field to generate the modified description unit, wherein the first data packet information field includes the starting address of the buffer in the system memory or the address of the header of the first data packet among the multiple data packets; and the total data volume/total number of data packets field records the total amount of data stored in the buffer or the number of the multiple data packets.

4. The method of claim 3, wherein the modified description unit further comprises a multi-packet tag field, wherein the multi-packet tag field records whether the buffer stores multiple packets or only stores one packet.

The method of claim 2 , wherein the information of the data packet includes the size of the data packet.

6. The method of claim 1 , wherein the plurality of data packets include a first data packet and at least one second data packet, and the step of receiving the plurality of data packets and writing the plurality of data packets into the buffer comprises:

respectively generating a header for each of the at least one second data packet, wherein the header of each of the at least one second data packet comprises information of the second data packet; and

The first data packet, the at least one second data packet and the corresponding headers are sequentially written into the buffer.

7. The method of claim 6 , wherein the step of modifying the description unit according to the plurality of data packets written to the buffer to generate the modified description unit comprises:

The description unit is modified according to the multiple data packets written to the buffer to add a first data packet information field and a total data volume/total data packet number field to generate the modified description unit, wherein the first data packet information field includes information of the first data packet and the address of the first data packet in the system memory; and the total data volume/total data packet number field records the total data volume stored in the buffer or the number of the multiple data packets.

8. The method of claim 7, wherein the information of the first data packet includes a size of the first data packet, and the information of the second data packet includes a size of the second data packet.

9. The method according to claim 3 or 7, wherein the modified description unit further comprises a multi-packet tag field, wherein the multi-packet tag field records whether the buffer stores multiple data packets or only stores one data packet.

10. A processing circuit provided on a network card, configured to perform the following operations:

Reading a description unit from a system memory external to the network card, wherein the description unit includes a buffer start address field and a buffer size field, wherein the buffer start address field includes a start address of a buffer in the system memory, and the buffer size field includes a size of the buffer;

The modified description unit is written to the system memory.