CN116233031B - An implementation method of time-sensitive network switch model - Google Patents

Abstract

The invention discloses a method for realizing a time-sensitive network switch model, wherein the switch model comprises a plurality of inlet ports, a switch structure, an outlet module and a plurality of outlet ports which are connected in sequence; the exit module comprises a queue distributor, a plurality of queues, a plurality of transmission feasibility checking modules, a time-aware integer query module and an exit port transmission control module; after the data frame enters the switch model, the queue distributor distributes the data frame to a proper queue according to the information in the data frame; the queue is used for queuing the data frames; the transmission feasibility checking module is used for judging the trafficability of the data frame in the subsequent link, if the data frame can pass, the data frame is submitted backwards, otherwise, the data frame is temporarily stored in the transmission feasibility checking module; the time-aware integer query module is used for realizing a TAS mechanism specified in the 802.1Qbv protocol; the output port transmission control module is used for realizing strict priority and output port control function. The invention provides a switch model implementation scheme based on software simulation.

Description

An implementation method of time-sensitive network switch model

Technical field

The invention relates to the field of network communication technology, and in particular to a method for implementing a time-sensitive network switch model.

Background technique

Time-sensitive networks have deterministic delay guarantees and multi-service carrying capabilities, which solve the problem of data transmission on the same network in the industrial Internet, and have become a research hotspot in industrial field networks. Most of the current time-sensitive network research time-triggered service flows are periodic. Time-aware shaping technology can perform predefined static configurations for periodic time-triggered service flows, control the timing of transmitted data flows, and change the transmission of data service flows. It is predictable and deterministic, thus ensuring the service quality of end-to-end time-triggered service flow transmission. However, due to the uncertainty in the arrival time of service flows triggered by non-periodic time, switch resources and gating cannot be managed through resource reservation or preconfiguration. Therefore, how to dynamically schedule switch resources and gate control has become the key to triggering deterministic transmission of service flows at non-periodic times.

Time-sensitive networks originated in the audio and video field, mainly to solve the uncertainty of audio and video data transmission. In 2005, the AVB task group was established and some standards were established. On the basis of maintaining full compatibility with the existing Ethernet system, the time-sensitive network The second data is forwarded, integer and other parts are expanded, so that Ethernet has the ability to guarantee bandwidth, limit delay, and precise clock synchronization, and provide high-quality, low-latency, and low-latency audio and video data services under the standard Ethernet architecture. It guarantees time synchronization, is compatible with the transmission of other data services, and provides a multi-service bearer solution. In 2012, the AVB working group was renamed the time-sensitive network working group to further study data transmission in industrial control networks. On the basis of traditional Ethernet, time synchronization, transmission scheduling, path control, resource reservation, and reliable redundancy were added. The mechanism ensures the service quality of mission-critical data and also solves the problem that multiple data services cannot be carried uniformly.

The TAS algorithm specified in the IEEE 802.1Qbv standard is a synchronization time scheduling algorithm that can strictly guarantee the certainty of TT flow delay. Figure 1 shows the typical packet scheduling structure defined by the 802.1Qbv standard. It sets eight FIFO queues with fixed priorities (from the lowest 0 to the highest 7) to cache packets to be scheduled. The IEEE 802.1Q standard specifies how to define the class to which a packet belongs based on the PCP and VLAN ID fields in the packet header. The class determines the priority of the packet and which queue it is sent to for buffering. Generally speaking, the queue with the highest priority is assigned to the TT stream, several queues with the next highest priority are assigned to the AVB stream, and the remaining queues are assigned to the BE stream. For the queue of AVB flow, you can set a CBS gate at the head of the queue: only when the credit value of the queue is positive, the CBS gate is open (that is, packets are allowed to pass). All queues are connected to a TAS gate, and its on/off status is controlled by the gate list GCL. Packet queue Q7 is used to cache TT packets, and during the time period T0 to T1, the TAS gate of queue Q7 is in the open state and the gates of other queues are in the closed state. Therefore, in the time period T0 to T1, only the TAS gate in Q7 TT streams can occupy ports exclusively. Each item in the gating list corresponds to the TAS gating status of each queue during a certain period of time, which is called a time window. By allocating time windows of different lengths to different queues, TAS finally achieves a special kind of time division multiplexing. Finally, the scheduler will select the queue with the highest priority from all queues with TAS gates and CBS gates turned on for scheduling. By planning a reasonable time window for the TT flow offline, TAS can ensure that the TT flow is scheduled and forwarded within a fixed time period of each hop switch, thereby ensuring end-to-end delay certainty.

At the beginning of the TT window, the low-priority flow being transmitted will hinder the transmission of the high-priority flow, thus affecting the on-time scheduling of the TT flow. To solve this problem, the 802.1Qbv standard proposes a guard band mechanism: stopping the work of the scheduler within the transmission time of a maximum Ethernet frame before the start of the next TT window. On this basis, 802.1Qbv proposes an improved guard band mechanism, that is, as long as the scheduling decision packet can be transmitted before the start of the next TT window, scheduling will continue; otherwise, scheduling will stop. Through the guard band mechanism, TAS can provide an exclusive, interference-free time window for TT flows.

The TSN protocol only stipulates the mechanism of TAS but does not provide a solution method for gating. Therefore, many researchers in related fields are currently studying the solution algorithm for gating. When the algorithm is solving the gating process or after the solution is completed, it needs to be verified through certain methods. Generally speaking, it can be verified through software simulation or directly in the physical system. In many cases, simulations are used instead of physical systems to research and verify mechanisms and algorithms. This is because compared to physical systems, simulation systems have the following three advantages:

1. The speed of following up with new standards is more controllable. Each manufacturer will consider many factors when implementing the standard, so there may be certain differences between the products released and the regulations in the standard. In addition, some parts of the agreement may be considered insufficiently important by the manufacturer and will not be implemented for a long time.

2. Lower cost. A physical system that fully runs a time-sensitive network requires at least a few TSN switches and multiple end devices that can support TSN, and the overall cost is relatively high. The simulation system only requires an ordinary computer.

3. Network topology settings are more flexible. Modifying the network topology or adding devices to the system in the simulation system is a task with no additional overhead. However, the above operations in a physical system require considerable manpower and material resources.

There are currently some simulation solutions based on the TAS mechanism specified by 802.1Qbv. Some researchers build a TAS simulation framework based on existing network simulation software such as omnet++ or opnet. However, almost no one provides independent TAS software simulation solutions without existing simulation software.

Contents of the invention

In view of this, the purpose of the present invention is to provide a method for implementing a time-sensitive network switch model, and to provide a feasible solution for the implementation of the most critical switch in independent TAS software simulation.

In order to solve the above technical problems, embodiments of the present invention provide the following solutions:

On the one hand, a method for implementing a time-sensitive network switch model is provided. The switch model includes a plurality of ingress ports, a switching structure, an egress module and a plurality of egress ports connected in sequence; wherein the egress module includes a queue distributor , multiple queues, multiple transmission feasibility check modules, time-aware integer query module and egress port transmission control module;

After the data frame enters the switch model, the queue allocator allocates the data frame to the appropriate queue according to the information in the data frame; the queue is used to queue the data frame; the transmission feasibility check module is used to determine the data frame Passability in subsequent links, if passable, will be submitted backwards, otherwise it will be temporarily stored in this module; the time-aware integer query module is used to implement the TAS mechanism specified in the 802.1Qbv protocol; the egress port transmission control module Used to implement strict priority and egress port control functions.

Preferably, the methods of data interaction between modules in the switch model include the following two: data pipes and events;

The basic rules followed during the implementation of the switch model are: if data is only logically interactive and does not require the flow of time, use the data pipeline method; if data interaction requires or will cause the flow of time, use the event method;

Among them, an event is defined as: a collection of key time points in a process and its corresponding status information.

Preferably, the time-sensitive network where the switch model is located also includes an end node model and an event table; the end node model is divided into a source node model and a destination node model;

The event table contains the data structure and corresponding methods of all events in the time-sensitive network. The events are sorted according to time information and stored in the linked list, and events are triggered sequentially from the head of the linked list. Some events will generate new events after being triggered. Events, new events are also inserted into the appropriate position in the linked list according to time information; events between each model include: data frame sending event, data frame sending completion event, data frame receiving completion event;

The source node model is the location where the data frame is generated and only receives the data frame sending event; when the data frame sending event reaches the source node model, the source node model will generate the data frame according to the information in the data frame sending event and detect it successfully. After link connectivity, register a data frame sending event to the event table and generate a data frame sending completion event through the data frame sending event to remind yourself that the data frame sending is completed in the future;

After receiving the data frame reception completion event, the destination node model will obtain the information of the data frame and perform statistics, including calculation of transmission delay jitter and recording of status information of the data frame during transmission.

The implementation method of the time-sensitive network switch model includes the following steps:

Data frames enter the switch model from the ingress port;

The switching structure switches data frames to the corresponding egress module according to the MAC table and switching rules;

The queue distributor puts the data frames into the corresponding queue according to priority;

The data frame is waiting for inspection in the transmission feasibility check module;

The time-aware integer query module checks whether the data frame passes. If it fails, it gives failure feedback to the transmission feasibility check module. If it passes, it proceeds to subsequent steps;

The egress port transmission control module checks whether the data frame passes. If it fails, it gives failure feedback to the transmission feasibility check module. If it passes, it proceeds to subsequent steps;

Data frames are transmitted from the egress port.

Preferably, the workflow of the queue distributor is as follows:

Initially, the queue allocator is in idle state. When the queue allocator receives a data frame, it will transfer to the queue allocation state and then transfer the data frame to the corresponding data pipeline according to the defined allocation rules. The data pipeline will send the data frame to the corresponding in the queue; then the queue allocator is in the feedback waiting state. When the queue notifies the queue allocator that the allocation is successful through the data pipeline, the queue allocator will enter the idle state again and wait for the arrival of the next data frame;

The workflow of the queue is as follows:

When the queue allocator allocates the data frame to the queue, the queue will be triggered to start working; the queue defines two working conditions, namely: 1. The queue allocator allocates the data frame to the queue; 2. The transmission feasibility check module requests data;

For case 1: When the queue receives the data frame sent by the queue distributor through the data pipe, it will query the status of the transmission feasibility check module through the data pipe. If the transmission feasibility check module is empty, the data frame just allocated will be passed through. The data pipeline is passed to the transmission feasibility check module, otherwise it is stored in the queue; whether it is stored in the queue or passed to the transmission feasibility check module, when the operation is completed, feedback will be given to the queue allocator through the data pipe;

For situation 2: When the transmission feasibility check module sends a data request to the queue, if there are still data frames being queued in the current queue, a data frame will be submitted through the data pipe. If the queue is empty at this time, it will be transmitted through the data pipe. Feasibility check module feedback.

Preferably, the workflow of the transmission feasibility check module is as follows:

The transmission feasibility check module is initially in an idle state. When it receives a data frame, it will query the status of the subsequent time-aware integer query module through the data pipeline;

If the specific implementation of the time-aware integer query module is not considered, if the current data frame wants to pass the time-aware integer query module, there are four possible situations, namely: 1. It can pass successfully and the passing time is known; 2. It can pass successfully, but the passing time is not known; 3. It cannot pass this time, but it is known when it may pass next time; 4. It cannot pass this time, and it knows nothing about the next time; but it can be combined with the requirements of the event table Time must have time information. Case 2 cannot actually be put into the event table as a reasonable time, so it is equivalent to case 4. The final time-aware integer query module check can provide three cases 1, 3, and 4;

If the time-aware integer query module check is successful and the time T_send passed by the time-aware integer query module is known, the transmission feasibility check module registers an event for itself to remind itself that the current data frame is sent; recorded as waiting state (1);

When the time-aware integer query module check fails until the next possible time, the time-aware integer query module registers an event for itself to remind itself to check the time-aware integer query module again at the next possible time point. ;Recorded as waiting state (2);

If the time-aware integer query module check fails and no additional information is known, the subsequent specific working status of the transmission feasibility check module cannot be judged by itself. Other modules are required to register specific events to remind the transmission feasibility check module to follow up. How to work; record as waiting state (3);

The process of waiting state (1) is as follows:

After the transmission feasibility check module enters the waiting state (1), it will wait for the reminder event registered by itself. When the reminder event is received, it means that the sending of the data frame has been completed, and then clears the content in the transmission feasibility check module and sends it to the queue through the data pipeline. Request a new data frame. If the feedback given by the queue is that the queue is empty, it returns to the idle state. Otherwise, the data frame is successfully requested and transferred to stage (4) and the process of receiving a data frame is restarted;

The process of waiting state (2) is as follows:

In the waiting state (2), if it receives its own reminder event, it will re-enter the door control check (5) state;

The process of waiting state (3) is as follows:

In the case of waiting state (3), the transmission feasibility check module cannot register a reminder event for itself and can only rely on other modules, usually the later time-aware integer query module or the egress port transmission control module, to register the event reminder that the transmission is feasible. The sex check module wakes up at the right time and proceeds with the next step;

When the transmission feasibility check module is awakened again, there are two situations: 1. The previously attempted check has a confirmed failure result after a period of time, then the transmission feasibility check module re-enters the gate control check state (5); 2. The check result of the previous attempt is finally determined to be successful, then the transmission feasibility check module enters the cache clear (6) state and continues with the subsequent process.

Preferably, the workflow of the time-aware integer query module is as follows:

The time-aware integer query module is used to implement the TAS mechanism specified in 802.1Qbv and provides a gate control interface for the transmission feasibility check module;

When the time-aware integer query module receives the check request, it will first check whether the data frame can pass the gate check at the current time based on its own gate configuration information. If it cannot pass, it will give feedback to the transmission feasibility check module that it failed and has time. ; If it can pass the gate control check, it is necessary to perform a backward check. The meaning of backward check here is to check the modules after this module; because in fact, the transmission feasibility check module only senses the status of the integer query module at the check time and then Carry out corresponding actions, so when the transmission feasibility check module checks the time-aware integer query module, it needs the time-aware integer query module to replace the transmission feasibility check module to check subsequent modules, so that the transmission feasibility check module can Provide complete results to allow them to make correct judgments;

If there are more modules that need to be checked, backward checks are also performed in sequence and status is provided to the transmission feasibility check module; if the backward check of the time-aware integer query module passes and the time is known, the transmission feasibility check module is successful and Feedback of known time; in other cases, the transmission feasibility check module fails and the feedback of unknown time is given.

Preferably, the workflow of the outbound port transmission control module is as follows:

When the egress port transmission control module is triggered to check, it first determines whether there is a data frame being sent. If so, it will give failure feedback to the transmission feasibility check module and give the time when the current data transmission is completed; if no data is being sent, check Whether to set the self-check, if not set, set and register the self-check event;

The reason for setting up self-check: An egress port has one egress port transmission control module but corresponds to multiple transmission feasibility check modules. At a certain time, T1 may have multiple transmission feasibility check modules all checking the egress port transmission control module, but In principle, from the perspective of the implementation of the event table, even events at the same time are in sequence in the event table. Different sequences will cause the inspection of the egress port transmission control module to show different results, so additional inspections must be carried out. ;

In terms of implementation, self-checking is to register an event with a minimum time order in the future to remind the port transmission control module to determine which data in the transmission feasibility check module can be sent. The minimum time order is 1ns or 1ps; and then determines the data Whether the frame is the highest priority, if so, it can be sent directly, and the time-aware integer query module is given successful feedback, the time is given, and the frame is transferred to the sending state; if it is not the highest priority, it is first put into the buffer to be sent. If it is currently sent If the data in the cache has a lower priority than itself, pass it into the to-be-sent cache and transfer the current data to the sending cache; if there is data with a higher priority than itself, do nothing;

When a self-check event is received, a sending success reminder event is sent to the cache module corresponding to the data frame in the sending cache, and a sending failure reminder event is sent to the cache module corresponding to the data in the cache to be sent.

On the other hand, an electronic device is provided. The electronic device includes a processor and a memory. At least one instruction is stored in the memory. The at least one instruction is loaded and executed by the processor to implement the above time-sensitive network. Implementation method of switch model.

On the other hand, a computer-readable storage medium is provided, in which at least one instruction is stored, and the at least one instruction is loaded and executed by a processor to implement the above implementation method of the time-sensitive network switch model.

The beneficial effects brought by the technical solutions provided by the embodiments of the present invention include at least:

The present invention designs and implements a switch model based on independent TAS software simulation based on the IEEE 802.1Qbv protocol, which is used to verify the feasibility of time-sensitive network system design, provide verification of gated scheduling algorithms, and can provide various Optimization algorithms provide software support for time-sensitive networks.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of a typical packet scheduling structure defined by the 802.1Qbv standard;

Figure 2 is a simplified structural schematic diagram of a network switch model provided by an embodiment of the present invention;

Figure 3 is a schematic structural diagram of an outlet module provided by an embodiment of the present invention;

Figure 4 is a work flow chart of the implementation method of the time-sensitive network switch model provided by the embodiment of the present invention;

Figure 5 is a work flow chart of the queue distributor provided by the embodiment of the present invention;

Figure 6 is a workflow diagram of a queue provided by an embodiment of the present invention;

Figure 7 is a work flow chart of the transmission feasibility check module provided by the embodiment of the present invention;

Figure 8 is a work flow chart of the waiting state (1) provided by the embodiment of the present invention;

Figure 9 is a work flow chart of the waiting state (2) provided by the embodiment of the present invention;

Figure 10 is a work flow chart of the waiting state (3) provided by the embodiment of the present invention;

Figure 11 is a schematic diagram of the overall state machine of the transmission feasibility check module provided by the embodiment of the present invention;

Figure 12 is a work flow chart of the time-aware integer query module provided by the embodiment of the present invention;

Figure 13 is a work flow chart of the egress port transmission control module provided by the embodiment of the present invention.

Figure 14 is a schematic diagram of the position of the flow at the source node's sending time on the timeline provided by the embodiment of the present invention;

Figure 15 is a schematic diagram of the gate control settings provided by the embodiment of the present invention.

As shown in the figures, in order to clearly realize the structure of the embodiments of the present invention, specific structures and devices are marked in the figures, but this is only for illustration and is not intended to limit the present invention to the specific structures, devices and environments. , according to specific needs, those of ordinary skill in the art can adjust or modify these devices and environments, and the adjustments or modifications are still included in the protection scope of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

Switching is a general term for the technology that uses manual or automatic equipment to transmit information to the corresponding route that meets the requirements according to the needs of both ends of the communication. Switches can be divided into WAN switches and LAN switches based on different working locations. A wide area switch is a device that performs information exchange functions in a communication system. It is applied at the data link layer. The switch has multiple ports, each with bridging capabilities, that can connect to a local area network or a high-performance server or workstation. In fact, switches are sometimes called multiport bridges.

A network switch is a device that expands the network and can provide more connection ports in a subnetwork to connect more computers. With the development of the communications industry and the advancement of informatization of the national economy, the network switch market has shown a steady upward trend. It is cost-effective, highly flexible, relatively simple and easy to implement. Ethernet technology has become the most important LAN networking technology today, and network switches have become the most popular switches.

Switch is the English name of a switch. This product is an upgrade from the original hub. In appearance, it is not much different from the hub. Since both ends of the communication need to transmit information, and the information to be transmitted is sent to the corresponding router that meets the required standards through equipment or manually, this technology is switch technology. From a broad perspective, the device that implements the information exchange function in a communication system is a switch.

TSN switches refer to switches that support time-sensitive network-related protocols. The embodiments of the present invention focus on describing how to implement a TSN switch model for simulation through software on an ordinary computer.

During the software simulation process, it is not easy to establish a correspondence between the simulation time and the time in the real world. Therefore, the switch model does not directly use time triggering during actual operation but uses event triggering to establish the connection with time. Here is an example. When an Ethernet data frame is transmitted from switch A to switch B through the Ethernet link, during the software running process, assuming that there is no small probability event that the data frame will cause errors in the link, the entire data frame The transmission process can be described by being a set of two events {transmission start, transmission end}. This converts the entire time from a continuous process to a discrete process, and the intermediate state in this discrete process actually does not have much practical significance. Such events are the basic way the switch model in this article relates to time. An event can be defined as: a collection of key time points in a process and its corresponding status information.

The focus of the present invention lies in the implementation of the time-sensitive network switch model in software. However, in order to describe the entire system more completely, other models in the network are briefly introduced here. In addition to the switch model, the time-sensitive network also includes end node models. The end nodes are divided into source node models (models corresponding to the physical entities where the TSN talker is located) and destination node models (models corresponding to the physical entities where the TSN listener is located). ) and also contains a software module event table that organizes all events.

Wherein, the event table includes the data structure and corresponding methods of all events in the time-sensitive network. According to the above definition of events, each event has corresponding time information. Judging from the actual network system, there is a strict sequence and specific triggering relationship between the operation of these events. Therefore, the event table sorts the events according to time information and stores them in the linked list, and triggers events sequentially from the head of the linked list. Some events will generate new events after being triggered, and new events are also inserted into the linked list according to the time information. suitable location. In this way, the event table ensures that events are triggered reasonably in the correct order. Events between each model include: data frame sending event, data frame sending completion event, and data frame receiving completion event.

The source node model is the location where data frames are generated and only receives data frame sending events. When the data frame sending event reaches the source node model, the source node model will generate a data frame according to the information in the data frame sending event and after successfully detecting link connectivity, register a data frame sending event with the event table and send it through the data frame The event generates a data frame sending completion event to remind itself in the future that the data frame sending is completed.

After receiving the data frame reception completion event, the destination node model will obtain the data frame information and perform statistics, including calculation of transmission delay jitter and recording of status information of the data frame during transmission.

The core content of the present invention is to provide a method for implementing a time-sensitive network switch model. As shown in Figure 2, the switch model includes multiple ingress ports, a switching structure, an egress module and multiple egress ports connected in sequence; wherein, The structure of the egress module is shown in Figure 3, including a queue distributor, multiple queues, multiple transmission feasibility check modules, a time-aware integer query module and an egress port transmission control module;

When the data frame enters the switch model, the queue allocator allocates the data frame to the appropriate queue according to the information in the data frame. Generally speaking, the default rule is to allocate the data frame according to the PCP field in the vlan tag of the data frame; the queue Used for queuing of data frames; the transmission feasibility check module is used to judge the passability of the data frame in subsequent links. If it can pass, it will be submitted backwards, otherwise it will be temporarily stored in this module; the time-aware integer query module It is used to implement the TAS mechanism specified in the 802.1Qbv protocol; the egress port transmission control module is used to implement strict priority and egress port control functions.

In the embodiment of the present invention, the data interaction methods between modules in the switch model include the following two methods: data pipes and events.

The basic rules followed during the implementation of the switch model are: if the data only interacts logically and does not require the flow of time, use the data pipeline method; if the data interaction requires or will cause the flow of time, use the event method.

The implementation method of the time-sensitive network switch model, as shown in Figure 4, includes the following steps:

Data frames enter the switch model from the ingress port;

The switching structure switches data frames to the corresponding egress module according to the MAC table and switching rules;

The queue distributor puts the data frames into the corresponding queue according to priority;

The data frame is waiting for inspection in the transmission feasibility check module;

The time-aware integer query module checks whether the data frame passes. If it fails, it gives failure feedback to the transmission feasibility check module. If it passes, it proceeds to subsequent steps;

The egress port transmission control module checks whether the data frame passes. If it fails, it gives failure feedback to the transmission feasibility check module. If it passes, it proceeds to subsequent steps;

Data frames are transmitted from the egress port.

Further, as shown in Figure 5, the workflow of the queue allocator is as follows:

Initially, the queue allocator is in idle state. When the queue allocator receives a data frame, it will transfer to the queue allocation state and then transfer the data frame to the corresponding data pipeline according to the defined allocation rules. The data pipeline will send the data frame to the corresponding in the queue; after that, the queue allocator is in the feedback waiting state. When the queue notifies the queue allocator that the allocation is successful through the data pipeline, the queue allocator will enter the idle state again and wait for the arrival of the next data frame.

As shown in Figure 6, the workflow of the queue is as follows:

When the queue allocator allocates the data frame to the queue, it will trigger the queue to start working; the queue defines two working situations, namely: 1. The queue allocator allocates the data frame to the queue; 2. The transmission feasibility check module requests data.

For case 1: When the queue receives the data frame sent by the queue distributor through the data pipe, it will query the status of the transmission feasibility check module through the data pipe. If the transmission feasibility check module is empty, the data frame just allocated will be passed through. The data pipeline is passed to the transmission feasibility check module, otherwise it is stored in the queue; whether it is stored in the queue or passed to the transmission feasibility check module, when the operation is completed, it will be fed back to the queue allocator through the data pipeline.

For situation 2: When the transmission feasibility check module sends a data request to the queue, if there are still data frames being queued in the current queue, a data frame will be submitted through the data pipe. If the queue is empty at this time, it will be transmitted through the data pipe. Feasibility check module feedback.

Furthermore, the transmission feasibility check module mentioned in the present invention is a self-defined abstract structure and may not necessarily exist in an actual switch. The transmission feasibility check module is designed to provide a specific location where the data frame can check the status of the subsequent time-aware integer query module and the egress port transmission control module, and to provide a waiting function for the data frame before being sent from the egress port.

As shown in Figure 7, the workflow of the transmission feasibility check module is as follows:

The transmission feasibility check module is initially in an idle state. When it receives a data frame, it will query the status of the subsequent time-aware integer query module through the data pipeline;

If the specific implementation of the time-aware integer query module is not considered, if the current data frame wants to pass the time-aware integer query module, there are four possible situations, namely: 1. It can pass successfully and the passing time is known; 2. It can pass successfully, but the passing time is not known; 3. It cannot pass this time, but it is known when it may pass next time; 4. It cannot pass this time, and it knows nothing about the next time; but it can be combined with the requirements of the event table The time must have time information. Case 2 cannot actually be put into the event table as a reasonable time, so it is equivalent to case 4; the final time-aware integer query module check can provide three cases 1, 3, and 4.

If the time-aware integer query module check is successful and the time T_send passed by the time-aware integer query module is known, the transmission feasibility check module registers an event for itself to remind itself that the current data frame is sent; recorded as waiting state (1);

When the time-aware integer query module check fails until the next possible time, the time-aware integer query module registers an event for itself to remind itself to check the time-aware integer query module again at the next possible time point. ;Record as waiting state(2);

If the time-aware integer query module check fails and no additional information is known, the subsequent specific working status of the transmission feasibility check module cannot be judged by itself. Other modules are required to register specific events to remind the transmission feasibility check module to follow up. How it works; marked as waiting state (3).

As shown in Figure 8, the process of waiting state (1) is as follows:

After the transmission feasibility check module enters the waiting state (1), it will wait for the reminder event registered by itself. When the reminder event is received, it means that the sending of the data frame has been completed, and then clears the content in the transmission feasibility check module and sends it to the queue through the data pipeline. Request a new data frame. If the feedback given by the queue is that the queue is empty, it returns to the idle state. Otherwise, the data frame is successfully requested and transferred to stage (4) to restart the process of receiving a data frame.

As shown in Figure 9, the process of waiting state (2) is as follows:

In the waiting state (2), if it receives its own reminder event, it will re-enter the door control check (5) state.

As shown in Figure 10, the process of waiting state (3) is as follows:

In the case of waiting state (3), the transmission feasibility check module cannot register a reminder event for itself and can only rely on other modules, usually the later time-aware integer query module or the egress port transmission control module, to register the event reminder that the transmission is feasible. The sex check module wakes up at the right time and proceeds with the next step;

When the transmission feasibility check module is awakened again, there are two situations: 1. The previously attempted check has a confirmed failure result after a period of time, then the transmission feasibility check module re-enters the gate control check state (5); 2. The check result of the previous attempt is finally determined to be successful, then the transmission feasibility check module enters the cache clear (6) state and continues with the subsequent process.

The overall state machine of the transmission feasibility check module is shown in Figure 11.

Furthermore, the time-aware integer query module is used to implement the TAS mechanism specified in 802.1Qbv. This module provides an interface for checking gating control for the transmission feasibility check module.

As shown in Figure 12, the workflow of the time-aware integer query module is as follows:

When the time-aware integer query module receives the check request, it will first check whether the data frame can pass the gate check at the current time based on its own gate configuration information. If it cannot pass, it will give feedback to the transmission feasibility check module that it failed and has time. ; If it can pass the gate control check, it is necessary to perform a backward check. The meaning of backward check here is to check the modules after this module; because in fact, the transmission feasibility check module only senses the status of the integer query module at the check time and then Carry out corresponding actions, so when the transmission feasibility check module checks the time-aware integer query module, it needs the time-aware integer query module to replace the transmission feasibility check module to check subsequent modules, so that the transmission feasibility check module can Provide complete results to allow them to make correct judgments;

If there are more modules that need to be checked, backward checks are also performed in sequence and status is provided to the transmission feasibility check module; if the backward check of the time-aware integer query module passes and the time is known, the transmission feasibility check module is successful and Feedback of known time; in other cases, the transmission feasibility check module fails and the feedback of unknown time is given.

Further, as shown in Figure 13, the workflow of the outbound port transmission control module is as follows:

When the egress port transmission control module is triggered to check, it first determines whether there is a data frame being sent. If so, it will give failure feedback to the transmission feasibility check module and give the time when the current data transmission is completed; if no data is being sent, check Whether to set the self-check, if not set, set and register the self-check event;

The reason for setting up self-check: An egress port has one egress port transmission control module but corresponds to multiple transmission feasibility check modules. At a certain time, T1 may have multiple transmission feasibility check modules all checking the egress port transmission control module, but In principle, from the perspective of the implementation of the event table, even events at the same time are in sequence in the event table. Different sequences will cause the inspection of the egress port transmission control module to show different results, so additional inspections must be carried out. ;

In terms of implementation, self-checking is to register an event with a minimum time order in the future to remind the port transmission control module to determine which data in the transmission feasibility check module can be sent. The minimum time order is 1ns or 1ps; and then determines the data Whether the frame is the highest priority, if so, it can be sent directly, and the time-aware integer query module is given successful feedback, the time is given, and the frame is transferred to the sending state; if it is not the highest priority, it is first put into the buffer to be sent. If it is currently sent If the data in the cache has a lower priority than itself, pass it into the to-be-sent cache and transfer the current data to the sending cache; if there is data with a higher priority than itself, do nothing;

When a self-check event is received, a sending success reminder event is sent to the cache module corresponding to the data frame in the sending cache, and a sending failure reminder event is sent to the cache module corresponding to the data in the cache to be sent. Then enter the sending state.

In a more specific embodiment, assume that the following network topology exists:

Three source nodes ES1, ES2, ES3, one destination node ES4 and one switch 0SW1. And each source node generates a stream, a total of three streams are generated, and the destination of each stream is the destination node ES4. The three streams are represented as S(ES1:ES4), S(ES2:ES4), S(ES3,ES4), and the link rate is 1000Mbps.

The information of each stream is represented by a vector as F(cycle,offset,length,S,priorty), where cycle represents the sending cycle of the stream, in units of ns, and offset represents the offset of the stream sending time relative to zero, in units of ns, length represents the length of the data frame in bits, S represents the source node and destination node of the stream, and priority represents the priority of the data frame (equivalent to the PCP code in vlantag).

The flow information vector of flow S(ES1:ES4) is F(3000,0,512,(ES1:ES4),7). The flow information vector of flow S(ES2:ES4) is F(1500,336,678,(ES2:ES4),5). The flow information vector of flow S(ES3:ES4) is F(1500,886,128,(ES3:ES4),1). The positions of the three streams sent on the timeline are shown in Figure 14.

Set the gating period to 3000ns. In a gating period, flow S (ES1:ES4) arrives at the switch once, with an arrival time of 512ns; flow S (ES2:ES4) arrives at the switch twice, with arrival times of 1014ns and 2514ns. S(ES3:ES4) arrives at the switch twice, with arrival times of 1014ns and 2514ns.

The gate control period of the switch is 3000ns, and the gate control settings are shown in Figure 15.

The overall workflow is: when the system is initialized, the flow sending events will be initialized in advance, so after initialization, there are 5 sending events in the event table, which are the flow sending events of the three nodes. The time when the flow arrives at the switch has been mentioned before. Before the data flow enters the switch, it is not the focus of the present invention. Therefore, the discussion starts from when the flow enters the switch. At 512ns, the flow S (ES1:ES4) is transmitted from node ES1 to the switch. The switching structure switches the data frame to the corresponding egress port, and the data frame enters the corresponding egress module. Passing through the queue dispatcher first, this flow has priority 7 and therefore enters queue 7. Queue 7 finds that the transmission feasibility check module is empty and transfers the data frame of this flow to the transmission feasibility check module. The transmission feasibility check module starts to query the gating status of the time-aware integer query module. The time-aware integer query module queries that the gate status of this queue is currently open. Then the time-aware integer query module queries the egress port transmission control module. Whether the current port can send data frames, the egress port transmission control module finds that the current port has no sending tasks and the current data frame priority is the highest priority 7, so it returns the success status to the time-aware integer query module and gives the sending time. In addition, it also sets itself to the sending state and the sending time is 512ns to 1024ns. The time-aware integer query module then returns the success status to the transmission feasibility check module. The transmission feasibility check module determines that this data frame is available on this port at the current time. Transmit, and then register a data frame sending start and sending end event to the event cache.

At 1014ns, flows S(ES2:ES4) and S(ES3:ES4) are transmitted from the node to the switch. S(ES2:ES4) enters queue 5, and S(ES3:ES4) enters queue 1. At this time, the transmission feasibility check modules corresponding to the two queues are empty, so both queues transfer the data frames to the corresponding transmission feasibility check modules. The transmission feasibility check module began to query the time-aware integer query module for the gate control status, and found that it was currently in slot 1, and neither queue 5 nor queue 1 could send. It returned failure to the transmission feasibility check module and gave a possible time for subsequent sending: 1200ns, which is the time when slot2 starts. After receiving the failure information, the transmission feasibility check module registers a self-reminder event with the event cache. The reminder time is the 1200ns.

At 1024ns, the transmission feasibility check module 7 receives the transmission completion event, clears its stored data frames, and then requests a new data frame from the queue and enters the idle state when it finds that the queue is empty.

At 1200ns, it is assumed that the transmission feasibility check module 1 first receives the self-reminder event. The transmission feasibility check module 1 queries the time-aware integer query module for the gating status. The time-aware integer query module queries that the gate status of this queue is currently open. Then the time-aware integer query module queries the egress port transmission control module. Whether the current port can send data frames, the egress port transmission control module finds that the egress port is idle at the current moment but the data frame is not the highest priority, so it temporarily stores this send request in the send cache and registers a self- Check the event. The transmission feasibility check module 5 also receives the self-reminder event. In the same process as above, the egress port transmission control module finds that the egress port is idle and the priority of the request in the sending cache is lower than this request, so the request in the sending cache is placed Enter the cache to be sent, and put this request into the sending cache, because the self-check event has been registered and will not be registered again. The above two operations will send failure information to the corresponding transmission feasibility check module and declare that it does not know the time to put both modules into a state of waiting for external events.

At 1201ns, the outbound transmission control module receives a self-check event, the data frame request corresponding to the transmission feasibility check module 5 is in the sending buffer, and the data frame request corresponding to the transmission feasibility check module 1 is in the waiting to send buffer. Finally, it can be determined that the data of the transmission feasibility check module 5 can be sent, and the other cannot be sent. Register a successful sending reminder event to the module that can successfully send, and give the start and end time of the transmission as 1201ns to 1879ns. Register a failure event to the module that cannot send to remind it to re-enter the gated check state. The time of the above two events is 1201ns. The transmission feasibility check module 5 determines that this data frame can be transmitted at this port at the current time, and then registers a data frame sending start and sending end event in the event buffer. The transmission feasibility check module 1 re-performs the sending feasibility check, and the time-aware integer query module can pass, but because the outbound transmission control module is in the sending occupied state and this state lasts until 1879ns, the transmission feasibility check module 1 registers a self-reminder event at 1879ns.

At 1879ns, the transmission feasibility check module 5 receives the transmission completion event, clears its stored data frames, and then requests a new data frame from the queue and enters the idle state when it finds that the queue is empty. The transmission feasibility check module 1 receives the self-reminder event, and both the time-aware integer query module and the egress port transmission control module can register a send and start event with a start time of 1879ns and an end time of 2007ns.

In 2007ns, the transmission feasibility check module 1 receives the event of completion of transmission, clears its stored data frames, and then requests a new data frame from the queue and enters the idle state when it finds that the queue is empty.

The process of the data frame arriving at 2514ns within the switch is similar to that described above and will not be described again here.

To sum up, the present invention designs and implements a switch model based on independent TAS software simulation based on the IEEE 802.1Qbv protocol, which is used to verify the feasibility of time-sensitive network system design and provide verification of the gated scheduling algorithm. , which can provide software support for time-sensitive networks for various optimization algorithms.

Embodiments of the present invention also provide an electronic device, which may vary greatly due to different configurations or performance, and may include one or more processors (central processing units, CPU) and one or more memories. Wherein, at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor to implement the steps of the method for implementing the time-sensitive network switch model.

In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including instructions, and the instructions can be executed by a processor in a terminal to complete the implementation method of the above time-sensitive network switch model. For example, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

It should be noted that, in this article, the terms "comprising", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article or terminal device including a series of elements not only includes those elements , but also includes other elements not expressly listed or inherent to such process, method, article or terminal equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or terminal device including the stated element.

References in the specification to "one embodiment," "an embodiment," "exemplary embodiments," "some embodiments," etc. indicate that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment All include that particular feature, structure or characteristic. Additionally, when a particular feature, structure or characteristic is described in connection with an embodiment, it should be within the knowledge of a person skilled in the relevant art to implement such feature, structure or characteristic in conjunction with other embodiments (whether explicitly described or not).

Often, a term can be understood, at least in part, from its usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular, or may be used to describe a combination of features, structures or characteristics in the plural, depending at least in part on context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead, depending at least in part on context, allow for the presence of other factors that are not necessarily explicitly described.

The present invention covers any alternatives, modifications, equivalent methods and solutions within the spirit and scope of the invention. In order to provide the public with a thorough understanding of the present invention, specific details are described in the following preferred embodiments of the present invention, and those skilled in the art can fully understand the present invention without the description of these details. In addition, well-known methods, processes, flows, components, circuits, etc. have not been described in detail in order to avoid unnecessary confusion.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (4)

1. An implementation method of a time-sensitive network switch model, characterized in that the switch model includes a plurality of ingress ports, a switching fabric, an egress module and a plurality of egress ports connected in sequence; wherein the egress module includes queue allocation Server, multiple queues, multiple transmission feasibility check modules, time-aware integer query module and egress port transmission control module; After the data frame enters the switch model, the queue allocator allocates the data frame to the appropriate queue according to the information in the data frame; the queue is used to queue the data frame; the transmission feasibility check module is used to determine the data frame Passability in subsequent links, if passable, will be submitted backwards, otherwise it will be temporarily stored in this module; the time-aware integer query module is used to implement the TAS mechanism specified in the 802.1Qbv protocol; the egress port transmission control module Used to implement strict priority and egress port control functions; The implementation method of the time-sensitive network switch model includes the following steps: The data frame enters the switch model from the ingress port; the switching structure switches the data frame to the corresponding egress module according to the MAC table and switching rules; the queue distributor puts the data frame into the corresponding queue according to the priority; the data frame waits in the transmission feasibility check module Check; the time-aware integer query module checks whether the data frame passes. If it fails, it will give failure feedback to the transmission feasibility check module. If it can pass, it will proceed to the subsequent steps; the egress port transmission control module checks whether the data frame passes. Check, if it cannot pass, failure feedback will be given to the transmission feasibility check module, if it can pass, proceed to subsequent steps; the data frame is transmitted from the egress port; The workflow of the transmission feasibility check module is as follows: The transmission feasibility check module is initially in an idle state. When it receives a data frame, it will query the status of the subsequent time-aware integer query module through the data pipeline; If the current data frame wants to pass the time-aware integer query module, there are four possible situations, namely: 1. It can pass successfully, and the passing time is known; 2. It can pass successfully, but the passing time is not known; 3. This It cannot pass this time, but you can know the time when it may pass next time; 4. It cannot pass this time, and you know nothing about the next time; combined with the premise that the event table requires time to have time information, case 2 cannot be used as a reasonable time Put it into the event table, so it is equivalent to case 4; the final time-aware integer query module check can provide three cases 1, 3, and 4; If the time-aware integer query module check is successful and the time T_send passed by the time-aware integer query module is known, the transmission feasibility check module registers an event for itself to remind itself that the current data frame is sent; it is recorded as waiting state 1; When the time-aware integer query module check fails until the next possible time, the time-aware integer query module registers an event for itself to remind itself to check the time-aware integer query module again at the next possible time point. ;Recorded as waiting state 2; If the time-aware integer query module check fails and no additional information is known, the subsequent specific working status of the transmission feasibility check module cannot be judged by itself. Other modules are required to register specific events to remind the transmission feasibility check module to follow up. How to work; recorded as waiting state 3; The process of waiting state 1 is as follows: After the transmission feasibility check module enters the waiting state 1, it will wait for the reminder event registered by itself. When the reminder event is received, it means that the sending of the data frame has been completed, and then clears the content in the transmission feasibility check module and requests new data from the queue through the data pipeline. data frame, if the feedback given by the queue is that the queue is empty, it returns to the idle state, otherwise the data frame is successfully requested and transferred to stage 4 to restart the process of receiving a data frame; The process of waiting state 2 is as follows: In the case of waiting state 2, if it receives its own reminder event, it will re-enter the door control check state 5; The process of waiting state 3 is as follows: In the case of waiting state 3, the transmission feasibility check module cannot register a reminder event for itself. The subsequent time-aware integer query module or the egress port transmission control module registers an event to remind the transmission feasibility check module to wake up at the appropriate time and proceed. one step of work; When the transmission feasibility check module is awakened again, there are two situations: 1. The previously attempted check has a confirmed failure result after a period of time, then the transmission feasibility check module re-enters the gate control check state 5; 2. The previous attempt The check result is finally determined to be successful, then the transmission feasibility check module enters cache clearing state 6 and continues with the subsequent process; The workflow of the time-aware integer query module is as follows: The time-aware integer query module is used to implement the TAS mechanism specified in 802.1Qbv and provides a gate control interface for the transmission feasibility check module; When the time-aware integer query module receives the check request, it will first check whether the data frame can pass the gate check at the current time based on its own gate configuration information. If it cannot pass, it will give feedback to the transmission feasibility check module that it failed and has time. ;If it can pass the gate control check, it will be checked backwards. The meaning of backward check here is to check the modules after this module; in fact, the transmission feasibility check module only checks the status of the time-aware integer query module and then performs the corresponding action, so when the transmission feasibility check module checks the time-aware integer query module, the time-aware integer query module replaces the transmission feasibility check module to check the subsequent modules, and provides the transmission feasibility check module with complete results for it to make sound judgments; If there are more modules that need to be checked, backward checks are also performed in sequence and status is provided to the transmission feasibility check module; if the backward check of the time-aware integer query module passes and the time is known, the transmission feasibility check module is successful and Feedback of known time; in other cases, the transmission feasibility check module fails and the feedback of unknown time is given; The workflow of the outbound port transmission control module is as follows: When the egress port transmission control module is triggered to check, it first determines whether there is a data frame being sent. If so, it will give failure feedback to the transmission feasibility check module and give the time when the current data transmission is completed; if no data is being sent, check Whether to set the self-check, if not set, set and register the self-check event; The reason for setting up self-check: An egress port has one egress port transmission control module but corresponds to multiple transmission feasibility check modules. At a certain time, T1 may have multiple transmission feasibility check modules all checking the egress port transmission control module, but In principle, from the perspective of the implementation of the event table, even events at the same time are in sequence in the event table. Different sequences will cause the inspection of the egress port transmission control module to show different results, so additional inspections must be carried out. ; The implementation of self-checking is to register an event with a minimum time order in the future to remind the port transmission control module to determine which data in the transmission feasibility check module can be sent. The minimum time order is 1ns or 1ps; and then determine whether the data frame It is the highest priority. If it is, it will be sent directly. It will give the time-aware integer query module successful feedback, give the time and transfer to the sending state; if it is not the highest priority, it will be put into the cache to be sent first. If it is currently in the sending cache If the data priority is lower than your own, pass it into the to-be-sent cache and transfer the current data to the sending cache; if there is data with a higher priority than your own, do nothing; When a self-check event is received, a sending success reminder event is sent to the cache module corresponding to the data frame in the sending cache, and a sending failure reminder event is sent to the cache module corresponding to the data in the cache to be sent. 2. The implementation method of the time-sensitive network switch model according to claim 1, characterized in that the methods of data interaction between modules in the switch model include the following two: data pipelines and events; The basic rules followed during the implementation of the switch model are: if data is only logically interactive and does not require the flow of time, use the data pipeline method; if data interaction requires or will cause the flow of time, use the event method; Among them, an event is defined as: a collection of key time points in a process and its corresponding status information. 3. The implementation method of the time-sensitive network switch model according to claim 1, characterized in that the time-sensitive network where the switch model is located also includes an end node model and an event table; the end node model is divided into source nodes Model and destination node model; The event table contains the data structure and corresponding methods of all events in the time-sensitive network. The events are sorted according to time information and stored in the linked list, and events are triggered sequentially from the head of the linked list. Some events will generate new events after being triggered. Events, new events are also inserted into the appropriate position in the linked list according to time information; events between each model include: data frame sending event, data frame sending completion event, data frame receiving completion event; The source node model is the location where the data frame is generated and only receives the data frame sending event; when the data frame sending event reaches the source node model, the source node model will generate the data frame according to the information in the data frame sending event and detect it successfully. After link connectivity, register a data frame sending event to the event table and generate a data frame sending completion event through the data frame sending event to remind yourself that the data frame sending is completed in the future; After receiving the data frame reception completion event, the destination node model will obtain the information of the data frame and perform statistics, including calculation of transmission delay jitter and recording of status information of the data frame during transmission. 4. The implementation method of the time-sensitive network switch model according to claim 1, characterized in that the workflow of the queue distributor is as follows: Initially, the queue allocator is in idle state. When the queue allocator receives a data frame, it will transfer to the queue allocation state and then transfer the data frame to the corresponding data pipeline according to the defined allocation rules. The data pipeline will send the data frame to the corresponding in the queue; then the queue allocator is in the feedback waiting state. When the queue notifies the queue allocator that the allocation is successful through the data pipeline, the queue allocator will enter the idle state again and wait for the arrival of the next data frame; The workflow of the queue is as follows: When the queue allocator allocates the data frame to the queue, the queue will be triggered to start working; the queue defines two working conditions, namely: 1. The queue allocator allocates the data frame to the queue; 2. The transmission feasibility check module requests data; For case 1: When the queue receives the data frame sent by the queue distributor through the data pipe, it will query the status of the transmission feasibility check module through the data pipe. If the transmission feasibility check module is empty, the data frame just allocated will be passed through. The data pipeline is passed to the transmission feasibility check module, otherwise it is stored in the queue; whether it is stored in the queue or passed to the transmission feasibility check module, when the operation is completed, feedback will be given to the queue allocator through the data pipe; For situation 2: When the transmission feasibility check module sends a data request to the queue, if there are still data frames being queued in the current queue, a data frame will be submitted through the data pipe. If the queue is empty at this time, it will be transmitted through the data pipe. Feasibility check module feedback.