CN116232334B - Analog-to-digital converter and electronic equipment - Google Patents
Analog-to-digital converter and electronic equipment Download PDFInfo
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- CN116232334B CN116232334B CN202310204990.XA CN202310204990A CN116232334B CN 116232334 B CN116232334 B CN 116232334B CN 202310204990 A CN202310204990 A CN 202310204990A CN 116232334 B CN116232334 B CN 116232334B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present disclosure relates to an analog-to-digital converter and an electronic device, the analog-to-digital converter including: a first logic circuit for generating and outputting a first digital control signal based on the first integrated value and the digital signal; and updating the first integrated value; the first digital-to-analog converter is used for performing digital-to-analog conversion on the received first digital control signal to generate and output a first analog signal; the second logic circuit is used for inverting the digital signal to generate an inverted digital signal; generating and outputting a second digital control signal based on the second integrated value and the inverted digital signal; and updating the second integrated value; the second digital-to-analog converter is used for performing digital-to-analog conversion on the received second digital control signal to generate and output a second analog signal; and the output circuit is used for generating and outputting a feedback signal to the second input end of the adder according to the received first analog signal and the second analog signal. The analog-to-digital converter provided by the present disclosure can suppress mismatch errors of the digital-to-analog converter.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design, and in particular, to an analog-to-digital converter and an electronic device.
Background
Analog-to-digital converters are typically implemented by resistors, capacitors, current sources, etc., and one of the problems with Delta-Sigma analog-to-digital converters (i.e., delta-Sigma modulators, DSM) in the prior art is that the mismatch of the digital-to-analog converters inside them creates nonlinear errors, which in turn results in reduced performance of the analog-to-digital converter.
In the related art, a digital calibration algorithm or a dynamic cell configuration algorithm (Dynamic Element Matching, DEM) is generally adopted to calibrate a digital-to-analog converter inside the analog-to-digital converter, so as to reduce the nonlinear error of the digital-to-analog converter and further improve the performance of the analog-to-digital converter. However, the implementation of the digital calibration algorithm increases the complexity of the analog-to-digital converter system design, while the dynamic unit configuration algorithm is easy to implement and has strong universality, the existing dynamic unit configuration algorithm easily enables the capacitor inside the digital-to-analog converter to form two fixed error sequences after repeated rotation selection under the condition that the amplitude of the analog signal input by the analog-to-digital converter is low (for example, -40 dBFS), namely, periodically selects the fixed capacitor sequence, thereby introducing harmonic waves in the signal bandwidth, causing the analog signal output by the digital-to-analog converter to have distortion to a certain extent, and reducing the performance of the analog-to-digital converter.
In view of this, the present disclosure provides an analog-to-digital converter to solve the problem of introducing harmonics in the signal bandwidth by using a dynamic cell configuration algorithm in the prior art.
Disclosure of Invention
The present disclosure provides an analog-to-digital converter comprising: a first logic circuit for receiving a digital signal; generating and outputting a first digital control signal to a first digital-to-analog converter according to the first integrated value stored by the first logic circuit and the digital signal; and updating the first integrated value based on the digital signal; the digital signal is obtained according to the sum of an analog signal to be converted and a feedback signal output by the output circuit; the input end of the first digital-to-analog converter is connected with the output end of the first logic circuit and is used for performing digital-to-analog conversion on the received first digital control signal to generate and output a first analog signal to the output circuit; the second logic circuit is used for receiving the digital signal and inverting the digital signal to generate an inverted digital signal; generating and outputting a second digital control signal to a second digital-to-analog converter according to the second integrated value stored by the second logic circuit and the inverted digital signal; and updating the second integrated value based on the inverted digital signal; the input end of the second digital-to-analog converter is connected with the output end of the second logic circuit and is used for performing digital-to-analog conversion on the received second digital control signal to generate and output a second analog signal to the output circuit; and the input end of the output circuit is connected with the output end of the first digital-to-analog converter and the output end of the second digital-to-analog converter, and is used for generating and outputting the feedback signal according to the received first analog signal and the second analog signal.
In one possible implementation, the first logic circuit includes: a first digital integrator for receiving the digital signal according to a clock signal; generating and outputting a first pointer signal to a first shifter according to a first integrated value stored in the first digital integrator; updating the first integrated value stored by the first digital integrator according to the digital signal; the first decoder is used for receiving the digital signal, converting the digital signal into a thermometer code, and generating and outputting a first thermometer code to the first shifter; and the input end of the first shifter is connected with the output end of the first digital integrator and the output end of the first decoder, and the output end of the first shifter is connected with the input end of the first digital-to-analog converter and is used for generating and outputting a first digital control signal to the first digital-to-analog converter according to the first pointer signal and the first thermometer code.
In a possible embodiment, the first digital integrator is further configured to update the first integrated value stored by the first digital integrator according to a first preset value and the digital signal.
In one possible implementation, the second logic circuit includes: the input end of the inverter is used for receiving the digital signal, inverting the digital signal, and generating and outputting an inverted digital signal to the second digital integrator and the second decoder; the input end of the second digital integrator is connected with the output end of the inverter and is used for receiving the inverted digital signal according to a clock signal; generating and outputting a second pointer signal to a second shifter according to the second integrated value stored in the second digital integrator; updating the second integrated value stored by the second digital integrator according to the inverted digital signal; the input end of the second decoder is connected with the output end of the phase inverter and is used for converting the phase-inverted digital signal into a thermometer code, and generating and outputting a second thermometer code to the second shifter; and the input end of the second shifter is connected with the output end of the second digital integrator and the output end of the second decoder, and the output end of the second shifter is connected with the input end of the second digital-to-analog converter and is used for generating and outputting a second digital control signal to the second digital-to-analog converter according to the second pointer signal and the second thermometer code.
In a possible embodiment, the second digital integrator is further configured to update the second integrated value stored by the second digital integrator according to a second preset value and the inverted digital signal.
In one possible implementation, the first shifter and the second shifter each include a plurality of data selectors that are one of two or more.
In one possible implementation, the first digital-to-analog converter and the second digital-to-analog converter each comprise at least 2 n A plurality of capacitor units connected in parallel; where n is the data length corresponding to the digital signal output by the quantizer.
In one possible implementation, the output circuit includes: and the positive input end of the operational amplifier is connected with the output end of the first digital-to-analog converter, and the negative input end of the operational amplifier is connected with the output end of the second digital-to-analog converter.
In one possible implementation, generating and outputting a first digital control signal to a first digital-to-analog converter according to the first integrated value stored in the first logic circuit and the digital signal includes: based on an incremental data unit average algorithm or a data unit average algorithm, a first digital control signal is generated and output to a first digital-to-analog converter according to the first integrated value stored by the first logic circuit and the digital signal.
According to another aspect of the present disclosure, there is also provided an electronic device comprising the analog-to-digital converter described above.
According to the analog-to-digital converter, the two differential digital-to-analog converters can be respectively indicated by the two independent logic circuits to select the corresponding capacitor units to be connected with the forward reference voltage under the current period for digital-to-analog conversion, so that the selection principle of the two digital-to-analog converters to the capacitor units connected with the forward reference voltage is irrelevant, the randomness of mismatch errors between the two digital-to-analog converters is enhanced, and the mismatch errors are restrained. In addition, compared with the existing IDWA algorithm, the analog-to-digital converter provided by the present disclosure can further reduce offset voltage because no virtual capacitor is added.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram of a prior art analog-to-digital converter circuit.
Fig. 2 is a schematic diagram illustrating the operation of a DWA algorithm according to the prior art.
Fig. 3 is a schematic diagram illustrating the operation of the IDWA algorithm in the prior art.
Fig. 4 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the disclosure.
Fig. 5 is a schematic structural diagram of a first logic circuit according to an embodiment of the disclosure.
Fig. 6 is a schematic structural diagram of a second logic circuit according to an embodiment of the disclosure.
Fig. 7 is a schematic diagram illustrating the operation of a DWA algorithm according to an embodiment of the disclosure.
Fig. 8 is a schematic diagram illustrating a performance comparison of an analog-to-digital converter provided by the present disclosure, an analog-to-digital converter using a conventional IDWA algorithm, and an analog-to-digital converter using a conventional DWA algorithm, when providing a full-width input.
Fig. 9 is a schematic diagram showing a comparison of performance of an analog-to-digital converter provided by the present disclosure, an analog-to-digital converter using a conventional IDWA algorithm, and an analog-to-digital converter using a conventional DWA algorithm, when an input of-40 dBFS is provided in an embodiment of the present disclosure.
Fig. 10 is a schematic diagram of the relationship between the signal-to-noise-distortion ratio average value and the input amplitude of an analog-to-digital converter provided by an embodiment of the present disclosure, an analog-to-digital converter using a conventional IDWA algorithm, and an analog-to-digital converter using a conventional DWA algorithm.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a delta-sigma analog-to-digital converter employing DEM algorithm (i.e., dynamic Element Matching, dynamic cell configuration) in the prior art. The DEM algorithm, specifically DWA (i.e., data Weighted Averaging, data unit averaging) algorithm, will be described below as an example. The DWA algorithm is an implementation mode of the DEM algorithm.
Taking the analog-to-digital converter as an example, the analog-to-digital converter includes a 4-bit digital-to-analog converter, the digital-to-analog converter 6 may include a capacitor array circuit composed of 15 unit capacitors (for example, the capacitor unit C1 to the capacitor unit C15) connected in parallel, and each unit capacitor has a weight of 1/15. When the value corresponding to the first digital signal output from the quantizer 3 to the DEM logic circuit 5 is 3 (i.e., corresponding to the binary data 0011), the DEM logic circuit 5 generates and outputs an indication signal to the digital-to-analog converter 6, where the indication digital-to-analog converter 6 connects the second plates of the capacitor units C1 to C3 to the positive reference voltage (e.g., the first plate may be an upper plate of the unit capacitor, the second plate may be a lower plate of the unit capacitor, and the upper plates of the capacitor units C1 to C3 may be connected to the common mode level, and the lower plate is connected to the positive reference voltage). At this time, the second plates of the remaining unit capacitors (i.e., capacitor cell C4 to capacitor cell C15) in the capacitor array circuit can be connected to a negative reference voltage (e.g., the second plates of the remaining unit capacitors are grounded). When the value corresponding to the second digital signal output from the quantizer 3 to the DEM logic circuit 5 is 7 (i.e., corresponding to the binary data 0111), the DEM logic circuit 5 generates and outputs an indication signal to the digital-to-analog converter 6, which indicates that the digital-to-analog converter 6 sequentially selects the unit capacitors, and the second plates of the capacitor units C4 to C10 are connected to the positive reference voltage, and the second plates of the remaining unit capacitors are connected to the negative reference voltage. In the case that the value corresponding to the third digital signal output from the quantizer 3 to the DEM logic circuit 5 is 6 (i.e. corresponds to binary data 0110), the DEM logic circuit 5 generates and outputs an indication signal to the digital-to-analog converter 6, which indicates that the digital-to-analog converter 6 connects the capacitor cells C11 to C15 and the second plate of the capacitor cell C1 to the positive reference voltage, the second plates of the remaining unit capacitors to the negative reference voltage, and so on.
Since the digital-to-analog converter 6 needs to be instructed to sequentially select the unit capacitors that need to switch the second plate to the positive reference voltage in the above circuit, and the capacitor unit C1 to the capacitor unit C15 need to be selected again after all the capacitor units C1 to C15 are selected once. Thus, a pointer signal is required to indicate from which unit capacitance the current period of the digital-to-analog converter 6 starts to be selected. Fig. 2 is a schematic diagram of unit capacitors selected by the digital-to-analog converter 6 in each period when the digital signal output by the quantizer 3 corresponds to the values of 3, 7, 5, 4, and 8 in sequence, that is, a schematic diagram of the operation process of the DWA algorithm in the above circuit. It should be noted that P, N in fig. 2, 3 and 7 refer to a differential digital-to-analog converter in the analog-to-digital converter (i.e., P corresponds to a capacitor array circuit having one end connected to a positive input terminal of the comparator, N corresponds to a capacitor array circuit having one end connected to a negative input terminal of the comparator), each small square in fig. 2 represents a unit capacitor, a black square indicates that a second plate of the unit capacitor is connected to a positive reference voltage, and a gray square indicates that a second plate of the unit capacitor is connected to a negative reference voltage.
Referring to fig. 1 and 2, when the analog-to-digital converter uses the DWA technology to reduce the nonlinear error of the digital-to-analog converter, each of the unit capacitances in the capacitor array circuit P (i.e., the capacitor array circuit having one end connected to the forward input terminal of the comparator) and the capacitor array circuit N (i.e., the capacitor array circuit having one end connected to the reverse input terminal of the comparator) has the same probability of being selected, and the total number of unit capacitances of the capacitor array circuit P and the second diode board in the capacitor array circuit N connected to the positive reference voltage is equal to 15 in each period. The DWA algorithm can be adopted to carry out first-order shaping on the mismatch error of the capacitor, and the error generated by mismatch is moved out of the signal bandwidth. However, when the analog signal input by the analog-to-digital converter has a low amplitude (for example, -60dBFS to-30 dBFS), harmonics caused by mismatch are mixed in the bandwidth of the input signal, resulting in degradation of the performance of the analog-to-digital converter. For example, when the amplitude of the analog signal input to the analog-to-digital converter is-40 dBFS, the digital signal input to the DEM logic circuit 5 is concentrated on two values of 7 and 8, the DEM logic circuit 5 selects the capacitor cells Ca1 to Ca7 in the capacitor array circuit P, selects the capacitor cells Cb8 to Cb15 in the capacitor array circuit N in the first period, and selects the capacitor cells Ca8 to Ca15 in the capacitor array circuit P and selects the capacitor cells Cb1 to Cb7 in the capacitor array circuit N in the second period. Such a selection would then result in two fixed capacitance sequences, namely capacitance sequence 1: capacitance units Ca1 to Ca7, and capacitance sequence 2: capacitor element Ca8 through capacitor element Ca15, in turn, results in the generation of harmonics at fs/2 and the introduction of harmonics within the signal bandwidth. Wherein fs is the operating clock frequency of the digital-to-analog converter 6.
In the related art, in order to solve the problem that in-band harmonics are caused by periodically selecting a fixed capacitor sequence in the digital-to-analog converter when the amplitude of an analog signal input by the analog-to-digital converter is low (for example, -40 dBFS), random disturbance (Dither) can be added to the DWA logic circuit to destroy the periodic selection behavior, but the addition of the random disturbance breaks up the harmonic energy generated by the mismatch of the digital-to-analog converter to the whole frequency band, so that the in-band noise floor is raised and the signal-to-noise ratio is reduced. Yet another technique that can address the in-band harmonics caused by the DWA algorithm is the Incremental data element averaging algorithm (i.e., elementary DWA, IDWA). The working mode of the algorithm is as follows: k (K is an integer greater than or equal to 1) additional unit capacitors are added to the original capacitor array circuit for rotation, and when K=1, the working principle can be shown as shown in fig. 3. In fig. 3, the number of unit capacitors in the capacitor array circuit P and the capacitor array circuit N is 17, and a Dummy capacitor (i.e., dummy capacitor) is added in addition to 1 unit capacitor for rotation, so as to eliminate offset voltage, the Dummy capacitor does not need to participate in rotation of the unit capacitors (i.e., the power source connected to the second electrode plate of the Dummy capacitor is fixed), the second electrode plate of the Dummy capacitor of the capacitor array circuit P (i.e., the capacitor unit Ca 17) is connected to the positive reference voltage, and the second electrode plate of the Dummy capacitor of the capacitor array circuit N (i.e., the capacitor unit Cb 17) is connected to the negative reference voltage. When the amplitude of the analog signal input by the adc is-40 dBFS, the values corresponding to the digital signal input to the DEM logic circuit 5 are still concentrated on two values of 7 and 8, and the unit capacitors selected by the dac in each period can be shown in fig. 3, i.e. in the first period, the capacitor array circuit P selects the capacitor cells Ca1 to Ca7, in the second period, the capacitor array circuit P selects the capacitor cells Ca8 to Ca15, in the third period, the capacitor array circuit P selects the capacitor cells Ca16 to Ca6, in the fourth period, the capacitor array circuit P selects the capacitor cells Ca7 to Ca14, and so on.
Unlike the DWA algorithm described above, this rotation takes 32 times to occur, so that the IDWA algorithm generates a harmonic frequency of fs/32 and integer multiples thereof, and when the oversampling rate of the analog-to-digital converter is greater than or equal to 16, no harmonics caused by mismatch of the analog-to-digital converter occur in the input signal band. However, in practical applications, if the capacitance in the digital-to-analog converter is increased, the equivalent input noise will be increased. In addition, although 1 virtual capacitor is additionally added to reduce the offset voltage, a larger residual offset voltage still exists due to the influence of mismatch.
In view of this, referring to fig. 4, the disclosure provides an analog-to-digital converter, which can respectively instruct two differential digital-to-analog converters through two independent logic circuits to select corresponding capacitor units to access a forward reference voltage in a current period for digital-to-analog conversion, so that the selection principle of the two digital-to-analog converters to the capacitor units accessed to the forward reference voltage is not related, the randomness of mismatch errors between the two digital-to-analog converters is enhanced, and the mismatch errors are suppressed. In addition, compared with the existing IDWA algorithm, the analog-to-digital converter provided by the present disclosure can further reduce offset voltage because no virtual capacitor is added.
Referring to fig. 4, the present disclosure provides an analog-to-digital converter including a first logic circuit 5, a second logic circuit 6, a first digital-to-analog converter 7, a second digital-to-analog converter 8, and an output circuit 9. Furthermore, the digital-to-analog converter may further include: adder 1, integrator 2, quantizer 3, digital filter 4, and other devices.
Illustratively, the adder 1 comprises a first input for receiving the analog signal to be converted and a second input. The second input is connected to the output of the output circuit 9, and is configured to receive the feedback signal output by the output circuit 9.
The integrator 2 has an input connected to the output of the adder 1 and an output connected to the input of the quantizer 3, for example. The quantizer 3 has an input connected to the output of the integrator 2 and an output connected to the input of the digital filter 4, to the input of the first logic circuit 5 and to the input of the second logic circuit 6. The output of the digital filter 4 is used as the conversion result of the digital-to-analog converter.
The input of the first logic circuit 5 is illustratively connected to the output of the quantizer 3, and the input of the first digital-to-analog converter 7 is connected to the output of the first logic circuit 5. An input of the second logic circuit 6 is connected to an output of the quantizer 3 and an input of the second digital-to-analog converter 8 is connected to an output of the second logic circuit 6. The input of the output circuit 9 is connected to the output of the first digital-to-analog converter 7 and to the output of the second digital-to-analog converter 8, the output of which is connected to the second input of the adder 1.
The first logic circuit 5 is illustratively configured to receive the digital signal, generate and output a first digital control signal to the first digital-to-analog converter according to the first integrated value stored in the first logic circuit and the digital signal, and update the first integrated value according to the digital signal (e.g., add a value corresponding to the digital signal to the first integrated value to obtain an updated first integrated value). The digital signal may be obtained according to a sum of an analog signal to be converted and a feedback signal output by the output circuit, for example: the digital signal is a digital signal output from the quantizer 3 in fig. 4. The first digital-to-analog converter 7 is configured to perform digital-to-analog conversion on the received first digital control signal, and generate and output a first analog signal to the output circuit 9. The second logic circuit 6 is configured to receive the digital signal, generate and output a second digital control signal to the second digital-to-analog converter according to the second integrated value stored in the second logic circuit and the inverted digital signal, and update the second integrated value according to the inverted digital signal (e.g., add a value corresponding to the inverted digital signal to the second integrated value to obtain an updated second integrated value). The second digital-to-analog converter 8 is configured to perform digital-to-analog conversion on the received second digital control signal, and generate and output a second analog signal to the output circuit 9. The output circuit 9 is configured to generate and output a feedback signal according to the received first analog signal and the second analog signal, where the feedback signal may be output to the second input terminal of the adder 1, so as to obtain a sum of the analog signal to be converted and the feedback signal output by the output circuit.
Taking an analog signal to be converted as an analog signal a as an example, the adder 1 receives the analog signal a and a feedback signal output by the output circuit 9, and when the analog-to-digital converter is powered up, the signal output by the output circuit 9 is 0, that is, the feedback signal is 0. The adder 1 generates and outputs an addition signal a to the integrator 2 based on the analog signals a and 0. The integrator 2 generates and outputs an integrated signal a to the quantizer 3 based on the addition signal a. The quantizer 3 quantizes the integrated signal a to generate and output a digital signal a to the first logic circuit 5, the second logic circuit 6, and the digital filter 4 generates and outputs a digital signal A1 by digitally filtering the digital signal a, and uses the digital signal A1 as a conversion result of the analog-to-digital converter. It should be noted that, the working processes of the adder 1, the integrator 2, the quantizer 3 and the digital filter 4 can be referred to in the related art, and the functions and the connection modes thereof can be adjusted according to the needs, which is not described in detail in the disclosure.
Taking the example that the digital signal a corresponds to the binary data 0001 of 4 bits, the first integrated value stored in the first logic circuit is equal to 0, in the case that the first logic circuit 5 receives the digital signal a, the first logic circuit 5 generates and outputs the first digital control signal a to the first digital-to-analog converter 7 according to the first integrated value and the digital signal a, and updates the first integrated value to 1. When receiving the first digital control signal a, the first digital control signal a may be converted into the first analog signal a by the first digital-to-analog converter 7 connecting the second plates of the first capacitor unit to the positive reference voltage and connecting the second plates of the remaining capacitor units to the negative reference voltage in the capacitor array circuit. For example: the first digital-to-analog converter 7 includes a capacitor array circuit a, in which there are 16 capacitor units in parallel, i.e., capacitor units Ca1 to Ca16, and when the first digital-to-analog converter 7 receives the first digital control signal a, the first digital-to-analog converter 7 makes the second plate of the capacitor unit Ca1 access the positive reference voltage, makes the second plate of the capacitor unit Ca2 to the second plate of the capacitor unit Ca16 access the negative reference voltage, and further makes the first digital control signal a input to the first digital-to-analog converter 7 be converted into the first analog signal a. It should be noted that, the total number of the capacitor units in the capacitor array circuit a may be determined according to the actual situation, and the values of the positive reference voltage and the negative reference voltage may also be determined according to the actual situation, which is not limited in the disclosure.
Taking the example that the digital signal a corresponds to the binary data 0001 of 4 bits as well, the second integrated value stored in the second logic circuit is equal to 0, the second logic circuit 6 inverts the digital signal a to generate an inverted digital signal a (corresponds to the binary data 1110) when the second logic circuit 6 receives the digital signal a. At this time, the second logic circuit 6 generates and outputs the second digital control signal a to the second digital-to-analog converter 8 based on the second integrated value and the inverted digital signal a, and updates the first integrated value to 14. When receiving the second digital control signal a, the second digital control signal a may be converted into the second analog signal a by enabling the second plates of the first to fourteenth capacitor units in the capacitor array circuit to be connected to the positive reference voltage and enabling the second plates of the remaining capacitor units to be connected to the negative reference voltage. For example: the second digital-to-analog converter 8 includes a capacitor array circuit B, in which there are 16 capacitor units in parallel, that is, capacitor units Cb1 to Cb16, and when the second digital-to-analog converter 8 receives the second digital control signal a, the second digital-to-analog converter 8 makes the second plates of the capacitor units Cb1 to Cb14 access the positive reference voltage, makes the second plates of the capacitor units Cb15 to Cb16 access the negative reference voltage, and further makes the second digital control signal a input to the second digital-to-analog converter 8 convert into the second analog signal a. It should be noted that, the total number of the capacitor units in the capacitor array circuit B may be determined according to the actual situation, and the values of the positive reference voltage and the negative reference voltage may also be determined according to the actual situation, which is not limited in the disclosure.
The output circuit 9 may generate and output the feedback signal a to the adder 1 based on the first analog signal a and the second analog signal a, for example, in case of receiving the first analog signal a and the second analog signal a. The adder 1 may generate and output a summation signal B to the integrator 2 based on the feedback signal a and the analog signal a. The operation of the output circuit 9 and the adder 1 may be referred to in the related art, and the disclosure is not repeated herein.
The first logic circuit and the second logic circuit operate simultaneously, and the first digital-to-analog converter and the second digital-to-analog converter operate simultaneously. In other words, the second logic circuit generates and outputs the second digital control signal to the second digital to analog converter while the first logic circuit generates and outputs the first digital control signal to the first digital to analog converter. The second digital-to-analog converter generates and outputs a second analog signal to the output circuit while the first digital-to-analog converter generates and outputs a first analog signal to the output circuit.
In one possible implementation, generating and outputting a first digital control signal to a first digital-to-analog converter according to the first integrated value stored in the first logic circuit and the digital signal includes: based on an incremental data unit average algorithm or a data unit average algorithm, a first digital control signal is generated and output to a first digital-to-analog converter according to the first integrated value stored by the first logic circuit and the digital signal.
Illustratively, a data unit averaging algorithm (i.e., DWA algorithm) may be employed for reducing circuit complexity, while an incremental data unit averaging algorithm (i.e., IDWA algorithm) may be employed for further enhancing the randomness of the mismatch error between the first digital-to-analog converter 7 and the second digital-to-analog converter 8. Those skilled in the art can determine according to the actual situation, and this disclosure is not described herein in detail.
In one possible implementation, referring to fig. 4 and 5, the first logic circuit 5 includes: a first digital integrator 51, a first decoder 52 and a first shifter 53.
Illustratively, the input of the first digital integrator 51 is connected to the output of the quantizer 3, the input of the first decoder 52 is connected to the output of the quantizer 3, the input of the first shifter 53 is connected to the output of the first digital integrator 51 and to the output of the first decoder 52, and the output thereof is connected to the input of the first digital-to-analog converter 7.
Illustratively, the first digital integrator 51 is configured to receive a digital signal (e.g., a digital signal output from the quantizer 3) according to a clock signal, generate and output a first pointer signal to the first shifter according to a first integrated value stored in the first digital integrator 51, and update the first integrated value stored in the first digital integrator according to the digital signal. The first pointer signal may be used to indicate an i-th capacitive cell Cai in the capacitive array circuit a, where i is determined by the first integrated value. For example: the first digital integrator 51, upon receiving the digital signal a output from the quantizer 3 above, can generate and output a first pointer signal from the original first integrated value stored internally. After the first digital integrator 51 generates and outputs the first pointer signal, the first digital integrator 51 may update the first integrated value stored in the first digital integrator 51 according to the received digital signal.
Illustratively, if the first pointer signal indicates the ith capacitive element and the first thermometer code value is a, the i+1-th to i+a-th capacitive elements in the capacitive array circuit a are connected to a positive reference voltage.
For ease of understanding, taking a specific value as an example, in the first period after power-up, the original first integrated value stored in the first digital integrator 51 may be 0 (or may be another value, which may be determined according to practical situations and is not limited herein), and the digital signal a input to the first digital integrator 51 corresponds to 4 bits of binary data 0001. At this time, the first pointer signal generated by the first digital integrator 51 according to the original first integrated value and output to the first shifter 53 may be used to indicate the 0 th capacitor cell in the capacitor array circuit a, which is equivalent to indicating that the selection of the capacitor cell requires the selection of the capacitor cell from the first (0+1) capacitor cell Ca1 to switch on the positive reference voltage in the current period. After the first digital integrator 51 outputs the first pointer signal to the first shifter 53, the first digital integrator may update the first integrated value 0 stored in the first digital integrator to the first integrated value 1 according to the received digital signal a (corresponding to the value 1). In the second period after power-up, the original first integrated value stored inside the first digital integrator 51 is 1 (i.e., the first integrated value updated in the first period), and the digital signal B input to the first digital integrator 51 corresponds to 4-bit binary data 0011. At this time, the first pointer signal generated by the first digital integrator 51 according to the original first integrated value and output to the first shifter 53 may be used to indicate the first capacitor unit in the capacitor array circuit a, which is equivalent to indicating that the selection of the capacitor unit in the current period requires the selection of the capacitor unit from the second (1+1) capacitor unit Ca2 to switch on the positive reference voltage. After the first digital integrator 51 outputs the second first pointer signal to the first shifter 53, the first digital integrator may update the first integrated value 1 stored in the first digital integrator to the first integrated value 4 according to the received digital signal B (corresponding to the value 3). The process of generating the first pointer signal by the first digital integrator 51 may refer to the related art, and the disclosure is not repeated herein.
The first decoder 52 is for receiving a digital signal (e.g., a digital signal output from the quantizer 3), converting the digital signal into a thermometer code, and generating and outputting a first thermometer code to the first shifter 53. For example: the digital signal a output from the quantizer 3 corresponds to 4-bit binary data 0001, and the first decoder 52 generates a first thermometer code a of 000000000000001 from the digital signal a.
Illustratively, the first shifter 53 is configured to generate and output a first digital control signal to the first digital-to-analog converter 7 according to the first pointer signal and the first thermometer code. For example: the first shifter 53 generates and outputs the first digital control signal a to the first digital-to-analog converter 7 when the first integrated value corresponding to the first pointer signal received by the first shifter 53 is 2 and the first thermometer code a output by the first decoder is 000000000000011. At this time, the first digital control signal is used to instruct the first digital-to-analog converter 7 to switch the second plates of the capacitor cells Ca3 to Ca4 in the capacitor array circuit a to the positive reference voltage, and switch the second plates of the remaining capacitor cells to the negative reference voltage.
In a possible implementation, the first digital integrator 51 is further configured to update the first integrated value stored in the first digital integrator according to the first preset value and the digital signal. For example: the first preset value stored in the first digital integrator 51 is 2, and the updated first integrated value is equal to 3 when the first digital integrator 51 receives the binary data 0001 corresponding to the first digital signal a after power-up. The first preset value corresponds to the original first integrated value stored in the first digital integrator 51 after the power-up.
In one possible implementation, referring to fig. 6, the second logic circuit 6 includes: an inverter 61, a second digital integrator 62, a second decoder 63 and a second shifter 64.
Illustratively, the input of the inverter 61 is connected to the output of the quantizer 3, the input of the second digital integrator 62 is connected to the output of the inverter 61, the input of the second decoder 63 is connected to the output of the inverter 61, the input of the second shifter 64 is connected to the output of the second digital integrator 62 and to the output of the second decoder 63, and the output thereof is connected to the input of the second digital-to-analog converter 8.
Illustratively, the inverter 61 is configured to receive a digital signal (e.g., the digital signal output by the quantizer 3), invert the digital signal (bit-wise invert), and generate and output an inverted digital signal to the second digital integrator 62 and the second decoder 63. For example: the digital signal a output from the quantizer 3 corresponds to 4-bit binary data 0001, and the inverter 61 generates and outputs an inverted digital signal a 1110 from the digital signal a.
Illustratively, the second digital integrator 62 is configured to receive the inverted digital signal according to the clock signal, generate and output a second pointer signal to the second shifter 64 according to the second integrated value stored in the second digital integrator 62, and update the second integrated value stored in the second digital integrator according to the inverted digital signal. For example: the second integrator 62, upon receiving the inverted digital signal a output from the inverter 61 hereinabove, can generate and output a second pointer signal from the original second integrated value stored internally. After the second digital integrator 62 generates and outputs the second pointer signal, the second digital integrator 62 may update the second integrated value stored by the second digital integrator 62 according to the received inverted digital signal.
Illustratively, if the second pointer signal indicates the ith capacitive element and the second thermometer code value is a, the i+1-th to i+a-th capacitive elements in the capacitive array circuit B (see below) are connected to a positive reference voltage.
To facilitate understanding, taking a specific value as an example, in the first period after power-up, the original second integrated value stored in the second digital integrator 62 may be 0 (or may be other values, which may be determined according to practical situations and are not limited herein), and the inverted digital signal a input to the second digital integrator 62 corresponds to the 4-bit binary data 1110. At this time, the second pointer signal generated by the second digital integrator 62 according to the original second integrated value and output to the second shifter 64 may be used to indicate the 0 th capacitor unit in the capacitor array circuit B, which is equivalent to indicating that the selection of the capacitor unit in the current period requires the selection of the capacitor unit to switch on the positive reference voltage from the first (0+1) capacitor unit Cb 1. After the second digital integrator 62 outputs the second first pointer signal to the second shifter 64, the second digital integrator may update the second integrated value 0 stored by the second digital integrator to the second integrated value 14 based on the received inverted digital signal a (corresponding to the value 14). In the second period after power-up, the original second integrated value stored inside the second digital integrator 62 is 14 (i.e., the second integrated value updated in the first period), and the inverted digital signal B input to the second digital integrator 62 corresponds to 4-bit binary data 1100. At this time, the second pointer signal generated by the second digital integrator 62 according to the original second integrated value and output to the second shifter 64 may be used to instruct the fourteenth capacitor cell in the capacitor array circuit a, which is equivalent to instructing that the selection of the capacitor cell requires the positive reference voltage to be switched in from the fifteenth (14+1) capacitor cell Ca15 in the current period. After the second digital integrator 62 outputs the second pointer signal to the second shifter 64, the second digital integrator may update the second integrated value 14 stored by the second digital integrator to the second integrated value 26 based on the received digital signal B (corresponding to the value 12). The second pointer signal is used to indicate the starting position of the capacitor unit to which the positive reference voltage is connected in the current period of the capacitor array circuit B, and the process of generating the second pointer signal by the second digital integrator 62 can refer to the related art, which is not described herein in detail.
Illustratively, the second decoder 63 is configured to convert the inverted digital signal into a thermometer code, generate and output a second thermometer code to the second shifter 64. For example: the inverted digital signal a output from the inverter 61 corresponds to the 4-bit binary data 1110, and the second decoder generates the second thermometer code a011111111111111 according to the inverted digital signal a.
Illustratively, the second shifter 64 is configured to generate and output a second digital control signal to the second digital-to-analog converter 8 according to the second pointer signal and the second thermometer code. For example: the second shifter 64 generates and outputs the second digital control signal a to the second digital-to-analog converter 8 when the second integrated value corresponding to the first and second pointer signals received by the second shifter 64 is 0 and the second thermometer code a output by the second decoder 63 is 011111111111111. At this time, the second digital control signal a is used to instruct the second digital-to-analog converter 8 to switch the second plates of the capacitor units Cb1 to Cb14 in the capacitor array circuit to the positive reference voltage, and switch the second plates of the remaining capacitor units to the negative reference voltage.
In a possible implementation, the second digital integrator 62 is further configured to update the second integrated value stored in the second digital integrator 62 according to the second preset value and the inverted digital signal. The second preset value may not be equal to the first preset value, or may be equal to the first preset value. For example: the first preset value stored in the first digital integrator 62 is 0, and the second preset value stored in the second digital integrator 62 may be other values than 0, or may be equal to 0, taking the second preset value being equal to 3 as an example, when the second digital integrator 62 receives the binary data 1100 corresponding to the first inverted digital signal a after power is on, the updated second integrated value is equal to 15. The second preset value corresponds to the original second integrated value stored in the second digital integrator 62 after the power-up.
If the first integrated value, the second integrated value, and the range indicated by the i+1 to i+a-th capacitance units exceed the total number of capacitance units, the cycle count may be started from the first capacitance unit, for example, if 16 capacitance units are total, the integrated value is 17, and the positive reference voltage is switched in from the second capacitance unit as in the integrated value 1. For another example, if the i+1th to i+A are the 16 th to 17 th capacitor units, the 16 th capacitor unit and the 1 st capacitor unit are connected to the positive reference voltage.
In one possible implementation, referring to fig. 7, the order in which the second digital-to-analog converter selects the capacitor units may be reversed from the order in which the first digital-to-analog converter selects the capacitor units. For example: taking the numerical values corresponding to the digital signals input into the first digital integrating circuit as 3, 7, 6, 4 and 8 in sequence, wherein a first preset value stored in the first digital integrator is equal to 0, a second preset value stored in the second digital integrator is equal to 16 as an example, in a first period, a first pointer P0 corresponds to the first integral value to be 0, a first thermometer code corresponds to the numerical value 3, a first digital-to-analog converter selects a capacitor unit Ca1 to a capacitor unit Ca3, a second plate of the capacitor unit Ca is connected with positive reference voltage, and second plates of other capacitor units are connected with negative reference voltage. The second pointer N0 corresponds to a second integral value of 16, the second thermometer code corresponds to a value of 12, 16+1 is 17, which is equal to 1, and since the second pointer N0 is in reverse order, 12 capacitor units are connected to the positive reference voltage from the 16 th capacitor unit, that is, the second digital-analog converter selects capacitor units Cb5 to Cb16 to make the second plate connected to the positive reference voltage, and the second plates of the other capacitor units are connected to the negative reference voltage. In the second period, the first pointer P1 corresponds to a first integral value of 3, the first thermometer code corresponds to a value of 7, and the first digital-to-analog converter selects the capacitor cells Ca4 to Ca10, so that the second plates of the capacitor cells are connected to a positive reference voltage, and the second plates of the other capacitor cells are connected to a negative reference voltage. The second pointer N1 corresponds to a second integral value of 12 (16+12), the second thermometer code corresponds to a value of 8, 12+1 is 13, and because of the reverse order, the positive reference voltage is connected to the total of 8 capacitance units from the 13 capacitance units with the last number, that is, cb4, that is, the capacitance units Cb1 to Cb4 and Cb13 to Cb16 are selected by the second digital-analog converter, so that the second plate of the capacitance units is connected to the positive reference voltage, the second plates of the rest capacitance units are connected to the negative reference voltage, and so on. It can be seen that the order of selecting the capacitive units in the second digital-to-analog converter (i.e., from capacitive unit Cb16 reciprocal to capacitive unit Cb 1) can be reversed from the order of selecting the capacitive units in the first digital-to-analog converter (i.e., from capacitive unit Ca1 to capacitive unit Ca 16) by a related technique. The specific implementation method can be referred to the related art, and the disclosure is not repeated here.
The analog-to-digital converter provided by the disclosure can enable a first preset value stored by a first digital integrator to be unequal to a second preset value stored by a second digital integrator, and/or enable the sequence of a second digital-to-analog converter digital capacitor unit to be different from that of the first digital-to-analog converter digital capacitor unit, so that the starting positions of capacitor array circuit A and capacitor unit in capacitor array circuit B when rotating are enabled to be different, and/or the rotating sequence is enabled to be different, thereby further enhancing the randomness of mismatch errors between the two digital-to-analog converters and further inhibiting the mismatch errors.
In one possible implementation, each of the first shifter 53 and the second shifter 64 includes a plurality of data selectors that are alternatively selected.
For example, in the case where the digital signal output from the quantizer 3 corresponds to the nbit binary data, if the thermometer codes output from the first decoder and the second decoder are m bits, the first shifter 53 and the second shifter 64 each include a data selector array circuit composed of a plurality of data selectors selected from two. The data selector array circuit may be composed of (m+1) or (n) data selectors, that is, the data selector array circuit is composed of (m+1) parallel data selector groups, each of which includes n data selectors connected in series. For example: in the case where n is equal to 2 and m+1 is equal to 4, the data selector array circuit is composed of 4 parallel two-out-of-one data selector groups, each of which includes 2 two-out-of-one data selectors connected in series. The operation of the data selector array circuit can be seen in the related art, and the disclosure is not repeated here.
In a possible embodiment, the first digital-to-analog converter 7 and the second digital-to-analog converter 8 each comprise at least 2 n And a plurality of capacitor units connected in parallel. Where n is the data length corresponding to the digital signal output from the quantizer 3. For example: the data length corresponding to the digital signal output by the quantizer 3 is 4 bits, and the first digital-to-analog converter 7 and the second digital-to-analog converter 8 each include at least 16 capacitor units connected in parallel.
In one possible implementation, the output circuit 9 comprises: an operational amplifier.
The operational amplifier has a positive input connected to the output of the first digital-to-analog converter 7 and a negative input connected to the output of the second digital-to-analog converter 8, for example.
Illustratively, the operational amplifier receives a first analog signal output by a first digital-to-analog converter 7 via a forward input and a second analog signal output by a second digital-to-analog converter 8 via an inverse input.
In addition, taking a 3-order, 5-bit quantizer and an osr=32 oversampling analog-to-digital converter as an example, the effects of the analog-to-digital converter using the conventional DWA algorithm, the analog-to-digital converter using the conventional IDWA algorithm, and the effects of the analog-to-digital converter proposed in the present disclosure on the shaping mismatch errors of the digital-to-analog converter are compared. The following simulation results each assumed a unit capacitance mismatch of 0.5%.
In fig. 8 to 9, waveform 1 corresponds to an analog-to-digital converter employing a conventional IDWA algorithm, waveform 2 corresponds to an analog-to-digital converter provided by the present disclosure, and waveform 3 corresponds to an analog-to-digital converter employing a conventional DWA algorithm.
FIG. 8 shows a comparison of the results of the three techniques at full amplitude input (0 dBFS). It can be seen that at full amplitude input, there are no harmonics within the signal bandwidth. Compared with the other two algorithms, the offset voltage of the analog-digital converter residue of the traditional IDWA algorithm is larger. The analog-to-digital converter and the analog-to-digital converter adopting the traditional DWA algorithm can well inhibit offset voltage because the total capacitance number of the analog-to-digital converter which is turned over to positive reference voltage in each period is 15.
FIG. 9 shows a comparison of the results of the three techniques at a 40 dBus input. Analog-to-digital converters employing conventional DWA algorithms have significant harmonics in the signal bandwidth (fs/64=0.015625 x fs) compared to the other two algorithms. Meanwhile, it can be seen that the analog-to-digital converter adopting the conventional IDWA algorithm and the analog-to-digital converter provided by the disclosure can shift the harmonic wave out of band, which is determined by the working principle of the IDWA algorithm, so that the analog-to-digital converter adopting the conventional IDWA algorithm has the same effect as the analog-to-digital converter provided by the disclosure in terms of harmonic suppression generated by mismatch of the digital-to-analog converter.
Fig. 10 scans the input voltage range, comparing the suppression effect of the mismatch error of the digital-to-analog converter with three algorithms. The analog-to-digital converter employing the conventional DWA algorithm has poor mean and standard deviation results of the signal-to-noise-and-distortion ratio at smaller input amplitudes (-40 dBus). Compared with the analog-to-digital converter provided by the disclosure, the analog-to-digital converter provided by the disclosure has better result and smaller standard deviation of signal-to-noise distortion ratio along with the amplitude fluctuation of the input signal.
According to another aspect of the present disclosure, there is also provided an electronic device comprising an analog-to-digital converter as described in any one of the above.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. An analog-to-digital converter, the analog-to-digital converter comprising:
a first logic circuit for receiving a digital signal; generating and outputting a first digital control signal to a first digital-to-analog converter according to the first integrated value stored by the first logic circuit and the digital signal; and updating the first integrated value based on the digital signal; the digital signal is obtained according to the sum of an analog signal to be converted and a feedback signal output by the output circuit;
the input end of the first digital-to-analog converter is connected with the output end of the first logic circuit and is used for performing digital-to-analog conversion on the received first digital control signal to generate and output a first analog signal to the output circuit;
the second logic circuit is used for receiving the digital signal and inverting the digital signal to generate an inverted digital signal; generating and outputting a second digital control signal to a second digital-to-analog converter according to the second integrated value stored by the second logic circuit and the inverted digital signal; and updating the second integrated value based on the inverted digital signal;
the input end of the second digital-to-analog converter is connected with the output end of the second logic circuit and is used for performing digital-to-analog conversion on the received second digital control signal to generate and output a second analog signal to the output circuit;
And the input end of the output circuit is connected with the output end of the first digital-to-analog converter and the output end of the second digital-to-analog converter, and is used for generating and outputting the feedback signal according to the received first analog signal and the second analog signal.
2. The analog-to-digital converter of claim 1, wherein the first logic circuit comprises:
a first digital integrator for receiving the digital signal according to a clock signal; generating and outputting a first pointer signal to a first shifter according to a first integrated value stored in the first digital integrator; updating the first integrated value stored by the first digital integrator according to the digital signal;
the first decoder is used for receiving the digital signal, converting the digital signal into a thermometer code, and generating and outputting a first thermometer code to the first shifter;
and the input end of the first shifter is connected with the output end of the first digital integrator and the output end of the first decoder, and the output end of the first shifter is connected with the input end of the first digital-to-analog converter and is used for generating and outputting a first digital control signal to the first digital-to-analog converter according to the first pointer signal and the first thermometer code.
3. The analog-to-digital converter of claim 2, wherein the first digital integrator is further configured to update the first integrated value stored by the first digital integrator based on a first preset value and the digital signal.
4. The analog-to-digital converter of claim 1, wherein the second logic circuit comprises:
the input end of the inverter is used for receiving the digital signal, inverting the digital signal, and generating and outputting an inverted digital signal to the second digital integrator and the second decoder;
the input end of the second digital integrator is connected with the output end of the inverter and is used for receiving the inverted digital signal according to a clock signal; generating and outputting a second pointer signal to a second shifter according to the second integrated value stored in the second digital integrator; updating the second integrated value stored by the second digital integrator according to the inverted digital signal;
the input end of the second decoder is connected with the output end of the phase inverter and is used for converting the phase-inverted digital signal into a thermometer code, and generating and outputting a second thermometer code to the second shifter;
and the input end of the second shifter is connected with the output end of the second digital integrator and the output end of the second decoder, and the output end of the second shifter is connected with the input end of the second digital-to-analog converter and is used for generating and outputting a second digital control signal to the second digital-to-analog converter according to the second pointer signal and the second thermometer code.
5. The analog-to-digital converter of claim 4, wherein said second digital integrator is further configured to update a second integrated value stored by said second digital integrator based on a second preset value and said inverted digital signal.
6. An analog to digital converter according to claim 2 or 3, wherein the first shifter and the second shifter each comprise a plurality of one-out-of-two data selectors.
7. The analog-to-digital converter of claim 1, wherein the first digital-to-analog converter and the second digital-to-analog converter each comprise at least 2 n A plurality of capacitor units connected in parallel; where n is the data length corresponding to the digital signal output by the quantizer.
8. The analog-to-digital converter of claim 1, wherein the output circuit comprises:
and the positive input end of the operational amplifier is connected with the output end of the first digital-to-analog converter, and the negative input end of the operational amplifier is connected with the output end of the second digital-to-analog converter.
9. The analog-to-digital converter of claim 1, wherein generating and outputting a first digital control signal to a first digital-to-analog converter based on the first integrated value stored by the first logic circuit and the digital signal comprises: based on an incremental data unit average algorithm or a data unit average algorithm, a first digital control signal is generated and output to a first digital-to-analog converter according to the first integrated value stored by the first logic circuit and the digital signal.
10. An electronic device comprising an analog-to-digital converter as claimed in any one of claims 1 to 9.
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