CN116232329A - Multi-phase clock filter and analog-to-digital/digital-to-analog conversion system based on injection locking - Google Patents

Abstract

The present application discloses an injection-locked multi-phase clock filter and an analog-to-digital/digital-to-analog conversion system. The filter includes: 2n paths and a ring oscillator, and each path includes an input buffer and an output buffer. The output end of each input buffer is connected to a node with the input end of the corresponding output buffer, and the input ends of the input buffer respectively receive clock signals of different phases; the ring oscillator includes 2n delay units forming a loop, Between the adjacent nodes in the 1st, 3rd, ..., 2n-1 paths, n delay units are sequentially connected and the output end of the last delay unit is connected to the node of the 2nd path, in the 2nd, 4th, ..., the adjacent nodes in the 2n paths are sequentially connected to n delay units, and the output terminal of the last delay unit is connected to the node of the first path. This application improves phase noise, reduces jitter, averages the accumulated skew over the entire clock path, and reduces the burden of calibration and temperature drift.

Description

Multi-phase clock filter and analog-to-digital/digital-to-analog conversion system based on injection locking

technical field

The invention generally relates to the technical field of integrated circuits, in particular to an injection-locked multi-phase clock filter and an analog-to-digital/digital-to-analog conversion system.

Background technique

With the development of communication technology, the amount of data generated per unit time is increasing, and the required communication speed is also increasing. Therefore, high-speed analog-to-digital converters (ADC) become more and more important. For 32GS/S or 64GS/S sampling rate, clock-interleaved ADC is a more conventional architecture. For the clock interleaving circuit, complex clock generation circuits are required to create interleaving of multiple phase clocks. For the clock generation circuit, functionally speaking, the relative order of the phases must be satisfied. In addition, low power consumption and low clock jitter are required performance.

For modern wired and optical communications, the AD/DA sampling rate is getting faster and faster, and the requirements for time domain accuracy are getting higher and higher. However, low jitter and skew are more difficult to achieve due to limited transistor noise floors and more complex clocking schemes. Since jitter and skew are accumulated along the entire clock path, we need to find a way to filter out as much jitter as possible in post.

Contents of the invention

The purpose of the present invention is to provide a multi-phase clock filter based on injection locking, which can improve phase noise, reduce jitter, average the accumulated offset on the entire clock path, and reduce the burden of calibration and temperature drift.

This application discloses an injection-locked multi-phase clock filter, including:

2n paths, each path including an input buffer and an output buffer, the output of each input buffer is connected to a node with the input of the corresponding output buffer, the input of the plurality of input buffers The terminals receive clock signals of different phases respectively;

A ring oscillator, said ring oscillator comprising 2n delay units forming a loop, wherein n delay units are sequentially connected between adjacent nodes in the 1st, 3rd, ..., 2n-1 paths And the output end of the last delay unit is connected to the node of the second path, wherein n delay units are sequentially connected between adjacent nodes in the 2nd, 4th, ..., 2n paths and the output of the last delay unit The end is connected to the node of the first path, where n is greater than or equal to 2.

In a preferred example, a start-up circuit is also included, the start-up circuit includes a pull-down circuit and a pull-up circuit, and the pull-up circuit is connected to the delay unit between the nodes of the 2k-1 and 2k+1 paths The output terminal is used to pull up the output signal of the delay unit, and the pull-down circuit is connected to the output terminal of the delay unit between the nodes of the 2k and 2k+2 paths and is used to pull down the output signal of the delay unit, wherein k≤n.

In a preferred example, the pull-up circuit includes a pull-up transistor and a first turn-off transistor, the gate of the pull-up transistor is connected to a pull-up start signal, the source of the pull-up transistor is connected to a voltage source, and the pull-up transistor is connected to a voltage source. The drain of the pull-up transistor is connected to the output terminal of the delay unit, the gate of the first turn-off transistor is connected to the pull-up start signal, the source of the first turn-off transistor is connected to the ground terminal, and the first turn-off transistor The drain of the off transistor is connected to the delay unit.

In a preferred example, the pull-down circuit includes a pull-down transistor and a second turn-off transistor, the gate of the pull-down transistor is connected to the pull-down start signal, the source of the pull-down transistor is connected to the ground terminal, and the drain of the pull-down transistor is The output terminal of the delay unit is connected, the gate of the second off transistor is connected to the pull-down start signal, the source of the second off transistor is connected to the power supply terminal, and the drain of the second off transistor is connected to the the delay unit.

In a preferred example, the input buffer of each path increases by π*(n+1)/n sequentially along the loop direction of the 2n delay units corresponding to the received clock signal.

In a preferred example, the multiphase clock filter includes 8 paths, wherein the phase of the node of the first path is 45°, the phase of the node of the second path is 225°, and the node of the third path The phase of the node of the 4th path is 270°, the phase of the node of the 4th path is 90°, the phase of the node of the 5th path is 135°, the phase of the node of the 6th path is 315°, the phase of the node of the 7th path is 0°, the phase of the node of the 8th path is 180°.

In a preferred example, two inverters are connected between the 2k-1th path and the 2kth path, and the connection directions of the two inverters are opposite, where k is greater than or equal to 1 and less than or equal to n.

The application also discloses an analog-to-digital/digital-to-analog conversion system comprising:

A multi-phase input clock for generating a multi-phase clock signal;

The multi-phase clock filter as described above is used to receive and filter the multi-phase clock signal;

A plurality of sub-analog/digital/digital-analog conversion units are used to receive the filtered multi-phase clock signal and perform analog-to-digital/digital-to-analog conversion;

A pseudo-polyphase clock filter having the same structure as the polyphase clock filter, wherein the pseudo-polyphase clock filter receives a common-mode signal and outputs a polyphase clock signal;

A gating device, the two input terminals of the gating device respectively receive the filtered multi-phase clock signal of the poly-phase clock filter and the multi-phase clock signal of the pseudo-poly-phase clock filter;

A digital calibration circuit that receives the output of the gate and provides a calibration signal to the multiphase clock filter.

Compared with the prior art, the present invention has the following beneficial effects:

With the help of a clock filter based on polyphase injection locking, the AD/DA conversion system of the present application can improve phase noise and reduce jitter. In addition, it averages the accumulated skew over the entire clock path, reducing the burden of calibration and temperature drift.

A large number of technical features are recorded in this specification, which are distributed in various technical solutions. If it is necessary to list all possible combinations of technical features (ie, technical solutions) of this application, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above summary of the invention in this specification, the various technical features disclosed in the following various embodiments and examples, and the various technical features disclosed in the drawings can be freely combined with each other to form Various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, feature A+B+C is disclosed in one example, and feature A+B+D+E is disclosed in another example, and features C and D are equivalent technical means that play the same role. It can be used as soon as it is used, and it is impossible to use it at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as recorded because it is technically infeasible, and A+B+ The C+E scheme should be considered as documented.

Description of drawings

Fig. 1 shows a schematic diagram of an injection locking-based multi-phase clock filter in an embodiment of the present application.

Fig. 2 shows a schematic diagram of an initial state of a DC balance of a multiphase clock filter in an embodiment of the present application.

Fig. 3 shows a schematic diagram of an initial state of a sub-polyphase clock filter with a start-up circuit in an embodiment of the present application.

Fig. 4 shows a schematic topology diagram of a delay unit in an embodiment of the present application.

Fig. 5 shows a schematic diagram of an ultra-high-speed AD/DA conversion system in an embodiment of the present application.

FIG. 6 shows a schematic diagram of an ultra-high-speed AD/DA conversion system with calibration in an embodiment of the present application.

Explanation of reference signs:

101.1～101.8: access

102: Ring Oscillator

103: Input buffer

104: output buffer

105: delay unit

106, 107: Cross-coupled inverters

P1: pull-up transistor

N1: first turn-off transistor

N2: pull-down transistor

P2: second turn-off transistor

601: Multi-phase input clock

602: Multiphase Clock Filter Based on Injection Locking

603: sub-analog/digital-analog conversion unit

604:: Pseudo polyphase clock filter

605: Strobe

606: Digital Calibration Circuit

Detailed ways

In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that the technical solutions claimed in this application can be realized even without these technical details and various changes and modifications based on the following implementation modes.

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manner of the present application will be further described in detail below in conjunction with the accompanying drawings.

An embodiment of the present application discloses an injection-locked oscillator (ILO)-based multi-phase clock filter, the structure of which is shown in FIG. 1 , including: 2n channels 101 and a ring oscillator 102 . Each path 101 includes an input buffer 103 and an output buffer 104, the output end of each input buffer 103 on each path 101 is connected to a node with the input end of the corresponding output buffer 104, each The input terminals of the input buffer 103 on the path 101 respectively receive clock signals of different phases. Among them, n can be set to 4, 8, 12, 16 and so on. As shown in FIG. 1 , it is described by taking eight paths (for example, n=4) 101.1 , 101.2 , . . . , 101.8 from left to right as an example. The output end of each input buffer 103 is connected to the input end of the corresponding output buffer 104 at a node, for example, the output end of the input buffer 103 of the first path 101.1 is connected to the input end of the corresponding output buffer 104 At node n1, the output end of the input buffer 103 of the second path 101.1 is connected to the input end of the corresponding output buffer 104 at node n5, ..., the output end of the input buffer 103 of the eighth path 101.1 is connected to the corresponding The input terminal of the output buffer 104 is connected to the node n8.

The ring oscillator 102 includes 2n delay units 105 forming a loop, wherein n delay units are sequentially connected between adjacent nodes in the 1, 3, ..., 2n-1 paths and the last The output end of the delay unit is connected to the node of the second path, wherein n delay units are sequentially connected between adjacent nodes in the 2nd, 4th, ..., 2n paths and the output end of the last delay unit is connected to the first A node of 1 path, where n is greater than or equal to 2. Taking the eight paths in Figure 1 as an example, a delay unit is connected between node n1 and node n6, between node n6 and node n3, between node n3 and node n8, and the input end is connected to the delay unit of node n8. The output terminal is connected to node n5, a delay unit is connected between node n5 and node n2, between node n2 and node n7, and between node n7 and node n4, and the output terminal of the delay unit whose input terminal is connected to node n4 is connected to node n1.

In one embodiment, the input buffer 103 of each channel increases by π*(n+1)/n sequentially along the loop direction of the 2n delay units corresponding to the received clock signal. As shown in Figure 1, the multiphase clock filter includes 8 paths, and the input buffer 103 of each path increases 5π/4 sequentially along the loop direction of the 8 delay units corresponding to the received clock signal, that is, along the node The clock signals received by the input buffer 103 from n1 , node n6 , node n3 , node n8 , node n5 , node n2 , node n7 , and node n4 increase by 225° sequentially. In one embodiment, the phase of node n1 of the first path is 45°, the phase of node n5 of the second path is 225°, the phase of node n6 of the third path is 270°, and the phase of node n6 of the fourth path is 270°. The phase of node n2 is 90°, the phase of node n3 of the fifth path is 135°, the phase of node n7 of the sixth path is 315°, the phase of node n8 of the seventh path is 0°, the phase of the eighth path The phase of node n4 is 180°. It should be understood that in other embodiments of the present application, the phase of the nodes of each path may also be other phase values, as long as it is ensured that the phase of each path increases by 225° sequentially in the loop direction.

In one embodiment, two inverters are connected between the 2k-1th path and the 2kth path, and the connection directions of the two inverters are opposite, that is, two cross-coupled inverters, wherein k Greater than or equal to 1 and less than or equal to n. For example, there are two inverters 106 and 107 between the first path and the second path, the input end of the inverter 106 is connected to the node n1, the output end of the inverter 106 is connected to the node n5, and the inverter 107 The input end of the inverter 106 is connected to the node n5, and the output end of the inverter 106 is connected to the node n1. It should be understood that between the 1st path and the 2nd path, between the 3rd path and the 4th path, ..., between the 2n-1th path and the 2nth path, there is a cross-coupling anti-phase device.

The ring oscillator shown in Figure 1 is an even-order oscillator, which means that there is a significant dc steady state. Figure 2 shows the DC steady state of an 8-phase loop oscillator, where nodes n1-n8 have a DC quiescent voltage of 01010101 (as shown in Table 1 below), forming a loop and preventing the loop oscillator. The reason is that we use pseudo-differential CMOS delay cells instead of fully differential circuits to avoid CMOS-CML transitions. To make the differential gain stronger, we can increase the size of the cross-coupled inverters. However, in doing so, the parasitic resistance will prevent us from achieving high frequency operation. Therefore, this approach is not advisable in ultra-high-speed designs.

n6 next value n6 n3 n8 n5 n2 n7 n4 n1 1 1 0 1 0 1 0 1 0

Table 1 Initial state of DC balance

To solve this problem, our solution is to give some non-equilibrium initial states to get out of the DC equilibrium state. Specifically, the multi-phase clock filter also includes a start-up circuit, the start-up circuit includes a pull-down circuit and a pull-up circuit, and the pull-up circuit is connected to the delay between the nodes of the 2k-1 and 2k+1 paths The output terminal of the unit is used to pull up the output signal of the delay unit, and the pull-down circuit is connected to the output terminal of the delay unit between the nodes of the 2k and 2k+2 paths and used to pull down the output signal of the delay unit , where k≤n. The pull-up circuit includes a pull-up transistor and a first turn-off transistor, the gate of the pull-up transistor is connected to a pull-up start signal, the source is connected to a voltage source, and the drain is connected to the output terminal of the delay unit. The gate of a turn-off transistor is connected to the pull-up start signal, the source is connected to the ground terminal, and the drain is connected to the delay unit. The pull-down circuit includes a pull-down transistor and a second turn-off transistor, the gate of the pull-down transistor is connected to the pull-down start signal, the source is connected to the ground terminal, and the drain is connected to the output terminal of the delay unit, and the second turn-off transistor The gate is connected to the pull-down start signal, the source is connected to the power supply terminal, and the drain is connected to the delay unit.

Referring to FIG. 3, the output end of the delay unit between the node n1 of the first path and the third path n6 is connected to the pull-up transistor P1 and the first turn-off transistor N1, and the gate of the pull-up transistor P1 is connected to the The start signal is pulled, the source is connected to the power supply terminal, and the drain is connected to the output terminal of the delay unit (for example, node n6). The gate of the first turn-off transistor N1 is connected to the pull-up start signal, the source is connected to the ground terminal, and the drain is connected to the delay unit. When the pull-up enable signal is low, the pull-up transistor P1 is turned on, and the first turn-off transistor N1 is turned off, so that the corresponding delay unit is turned off, and the signal of the corresponding node (eg, node n6 ) is pulled high. The output end of the delay unit between the node n5 of the second path and the fourth path n2 is connected to the pull-down transistor N2 and the second turn-off transistor P2, the gate of the pull-down transistor N2 is connected to the pull-up start signal, and the source is It is connected to the ground terminal, the drain is connected to the output terminal of the delay unit (for example, node n2), the gate of the second turn-off transistor P2 is connected to the pull-down start signal, the source is connected to the power supply terminal, and the drain is connected to the delay unit. When the pull-down enable signal is high, the pull-down transistor N2 is turned on, and the second turn-off transistor N2 is turned off, so that the corresponding delay unit is turned off, and the signal of the corresponding node (eg, node n2 ) is pulled down.

When both the pull-up start signal and the pull-down start signal are enabled, the pull-up transistor P1 pulls up the signal of node n6, the turn-off transistor N1 closes the delay unit between node n1 and node n6, and the pull-down transistor N1 pulls up the signal of node n2 Low, turning off transistor P2 turns off the delay cell between node n5 and node n2. This loop is broken by tri-stating the delay cell between node n1 and node n6 and the delay cell between node n5 and node n2. Force node n6 to 1, then node n3, node n8 and node n5 will be automatically set to 010. Since we disconnected the delay unit after node n5, node n2, node n7 and node n4 will initially be set to 010. When the start signal comes, node n2 will be switched to 1, and this state will be passed to node n7. On the other hand, node n6 will be switched to 0 and the state will be passed to node n3. Since there are 3 delay units before the state of node n6 reaches node n5, there will be no signal collision on node n2. The signals of nodes n1-n8 are shown in Table 2 below.

n6 next value n6 n3 n8 n5 n2 next value n2 n7 n4 n1 0 1 0 1 0 1 0 1 0 1

Table 2 has the initial state of the startup circuit

Figure 4 shows the topology of the delay cell in Figure 1. The delay is implemented with 7-bit control to cover a wide tuning range and resolution.

Figure 5 shows how to use a clock filter based on polyphase injection locking in an ultra-high-speed AD/DA conversion system. We receive the N-phase clock from the PLL and clock distribution, pass the clock filter based on polyphase injection locking as described above, and then distribute the clock to each sub AD/DA. The output clock can be M-phase, which is different from the number of phases of the input clock. The main path in Figure 5 sends the 8-phase high-speed clock from the top of the figure to the multi-phase clock filter based on injection locking. An adjustable-strength buffer drives the ring oscillator in an injection-locked polyphase clock filter. This tunable buffer can adjust the strength to provide a trade-off between lock range and filter coefficient. A tunable delay element between nodes n1 and n8 forms a ring oscillator loop. The main path and ring oscillators are summed at n1 to n8. In addition, this loop can be closed for power saving and low-speed operation.

Another embodiment of the present application discloses an analog-to-digital/digital-to-analog (AD/DA) conversion system, the structure of which is shown in FIG. The polyphase clock filter 602 as described above, a plurality of sub-analog/digital-to-analog conversion units 603, a pseudo-polyphase clock filter 604 with the same structure as the polyphase clock filter 602, a gate 605 and a digital calibration circuit 606. Multiphase input clock 601 is used to generate a multiphase clock signal. The multi-phase clock filter 602 is used for receiving and filtering the multi-phase clock signal. Multiple sub-ADC/DAC conversion units 603 are used to receive the filtered multi-phase clock signal and perform AD/DAC conversion. The pseudo-multiphase clock filter 604 receives the common mode signal VCM and outputs a multiphase clock signal. The two input terminals of the gate 605 respectively receive the filtered multiphase clock signal (or frequency-divided clock) of the polyphase clock filter and the polyphase clock signal (or frequency division clock) of the pseudo-polyphase clock filter. divided clock). The digital calibration circuit 606 receives the output of the gate 605, and filters the polyphase clock according to the filtered polyphase clock signal of the polyphase clock filter and the polyphase clock signal of the pseudo polyphase clock filter calibrated.

Calibration is required when using an ILO-based clock filter in an ultra-high-speed AD/DA conversion system, as shown in Figure 5, to ensure the lock condition and optimum performance in terms of noise filtering, phase offset, etc. Figure 6 shows the calibration scheme. The frequency of the ILO can be calibrated using the frequency of the master clock or the replica clock.

With the help of clock filters based on polyphase injection locking, the application can be improved in terms of phase noise and jitter reduced. An added benefit of this filter is that it also averages the accumulated skew over the entire clock path, reducing the burden of calibration and temperature drift.

It should be noted that in the application documents of this patent, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these No such actual relationship or order exists between entities or operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. In the application documents of this patent, if it is mentioned that an action is performed according to a certain element, it means that the action is performed based on at least the element, which includes two situations: the action is only performed based on the element, and the action is performed based on the element and Other elements perform the behavior. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 types, and 2 or more, 2 or more times, or 2 or more types.

The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are indirectly in contact with each other, but still co-operate or interact with each other, and can mean that one or more other elements are coupled between the elements said to be coupled to each other or connect.

This specification includes combinations of the various embodiments described herein. Individual references to embodiments (eg, "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated to be mutually exclusive or to those skilled in the art Clearly mutually exclusive, otherwise the embodiments are not mutually exclusive. It should be noted that unless the context clearly indicates or requires otherwise, the term "or" is used in this specification in a non-exclusive sense.

All documents mentioned in this specification are considered to be included in the disclosure content of the application in their entirety so that they can be used as a basis for amendments when necessary. In addition, it should be understood that the above descriptions are only preferred embodiments of this specification, and are not intended to limit the protection scope of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the protection scope of one or more embodiments of this specification.

Claims (8)

1. A polyphase clock filter based on injection locking, characterized in that, comprising: 2n paths, each path including an input buffer and an output buffer, the output of each input buffer is connected to a node with the input of the corresponding output buffer, the input of the plurality of input buffers The terminals receive clock signals of different phases respectively; A ring oscillator, said ring oscillator comprising 2n delay units forming a loop, wherein n delay units are sequentially connected between adjacent nodes in the 1st, 3rd, ..., 2n-1 paths And the output end of the last delay unit is connected to the node of the second path, wherein n delay units are sequentially connected between adjacent nodes in the 2nd, 4th, ..., 2n paths and the output of the last delay unit The end is connected to the node of the first path, where n is greater than or equal to 2. 2. The multiphase clock filter based on injection locking according to claim 1, further comprising a startup circuit, the startup circuit includes a pull-down circuit and a pull-up circuit, and the pull-up circuit is connected to the 2k- The output terminal of the delay unit between the nodes of the 1st and 2k+1 paths is used to pull up the output signal of the delay unit, and the pull-down circuit is connected between the nodes of the 2k and 2k+2 paths The output terminal of the delay unit is used to pull down the output signal of the delay unit, where k≤n. 3. The multi-phase clock filter based on injection locking according to claim 2, wherein the pull-up circuit includes a pull-up transistor and a first turn-off transistor, and the gate of the pull-up transistor is connected to a pull-up transistor. A start signal, the source of the pull-up transistor is connected to a voltage source, the drain of the pull-up transistor is connected to the output terminal of the delay unit, the gate of the first turn-off transistor is connected to a pull-up start signal, the The source of the first turn-off transistor is connected to the ground terminal, and the drain of the first turn-off transistor is connected to the delay unit. 4. The multi-phase clock filter based on injection locking according to claim 2, wherein the pull-down circuit includes a pull-down transistor and a second shutdown transistor, the gate of the pull-down transistor is connected to a pull-down start signal, so The source of the pull-down transistor is connected to the ground terminal, the drain of the pull-down transistor is connected to the output end of the delay unit, the gate of the second turn-off transistor is connected to the pull-down start signal, and the source of the second turn-off transistor The pole is connected to the power supply terminal, and the drain of the second turn-off transistor is connected to the delay unit. 5. The multi-phase clock filter based on injection locking according to claim 1, wherein the input buffer of each path increases π* successively along the loop direction of the 2n delay units corresponding to the received clock signal (n+1)/n. 6. The multi-phase clock filter based on injection locking according to claim 1, wherein the multi-phase clock filter comprises 8 paths, wherein, the phase of the node of the first path is 45°, and the phase of the node of the first path is 45°, The phase of the nodes of the 2 paths is 225°, the phase of the nodes of the 3rd path is 270°, the phase of the nodes of the 4th path is 90°, the phase of the nodes of the 5th path is 135°, the phase of the nodes of the 6th path The phase of the node of the 7th path is 315°, the phase of the node of the 7th path is 0°, and the phase of the node of the 8th path is 180°. 7. The multiphase clock filter based on injection locking according to claim 1, wherein two inverters are connected between the 2k-1 path and the 2k path, and the two inverters The direction of connection is opposite, where k is greater than or equal to 1 and less than or equal to n. 8. An analog-to-digital/digital-to-analog conversion system, comprising: A multi-phase input clock for generating a multi-phase clock signal; The multi-phase clock filter according to any one of claims 1-7, configured to receive and filter the multi-phase clock signal; A plurality of sub-analog/digital/digital-analog conversion units are used to receive the filtered multi-phase clock signal and perform analog-to-digital/digital-to-analog conversion; A pseudo-polyphase clock filter having the same structure as the polyphase clock filter, wherein the pseudo-polyphase clock filter receives a common-mode signal and outputs a polyphase clock signal; A gating device, the two input terminals of the gating device respectively receive the filtered multi-phase clock signal of the poly-phase clock filter and the multi-phase clock signal of the pseudo-poly-phase clock filter; A digital calibration circuit that receives the output of the gate and provides a calibration signal to the multiphase clock filter.

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