CN116225318A - Command scheduling method, flash memory controller, flash memory device and storage medium - Google Patents

Abstract

The embodiment of the application relates to the field of storage equipment application, and discloses a command scheduling method, a flash memory controller, flash memory equipment and a storage medium. Acquiring a read command and issuing the read command to a high-priority first-in first-out queue, wherein the read command comprises at least one instruction; each instruction in the high priority first-in-first-out queue is executed. By storing the write command in the low priority first-in first-out queue, issuing the acquired read command to the high priority first-in first-out queue and executing each instruction in the high priority first-in first-out queue, the method and the device can enable the read command issued later to be executed in preference to the write command issued earlier under the condition of maintaining the total bandwidth, and therefore delay of the read command is reduced.

Description

Command scheduling method, flash memory controller, flash memory device and storage medium

technical field

The present application relates to the application field of storage devices, in particular to a command scheduling method, a flash memory controller, a flash memory device and a storage medium.

Background technique

Flash memory device, such as: Solid State Drives (SSD), is a storage device with semiconductor flash memory (NAND Flash) as the medium, and its main components include flash memory media, flash memory controller, dynamic random access memory (DRAM), etc. . An important function of the flash memory controller is to perform storage operations as a driver of the flash memory chip, and its main operations include erasing, writing and reading.

As the functions of flash memory become more and more complex, it becomes more and more difficult for solidified flash memory controllers to meet the flexible control requirements of flash memory. way to optimize the flexibility of flash memory operations.

However, considering the cost and power consumption, the coprocessor used by the flash memory controller will be as few as possible, so the computing power of the coprocessor is usually relatively tight, and the coprocessor will try to fill the hardware first-in-first-out queue (FIFO) as much as possible. , however, when a new read command comes, it is necessary to complete the issued command in the hardware first-in-first-out queue before starting to process the new read command, which will cause a large delay in the read command.

Contents of the invention

The embodiment of the present application provides a command scheduling method, a flash memory controller, a flash memory device, and a storage medium, which can make the read commands issued later be executed prior to the write commands issued earlier while maintaining the total bandwidth, thereby reducing the Read command latency.

The embodiment of the present application provides the following technical solutions:

In the first aspect, the embodiment of the present application provides a command scheduling method, which is applied to a flash memory controller. The flash memory controller includes a high-priority first-in-first-out queue and a low-priority first-in-first-out queue, wherein the low-priority first-in-first-out queue Used to store write commands;

Command dispatch methods include:

Acquiring a read command, and issuing the read command to a high-priority first-in-first-out queue, wherein the read command includes at least one instruction;

Executes each instruction in the high-priority FIFO queue.

In some embodiments, prior to obtaining the read command, the method includes:

Determine the high-priority FIFO queue and the low-priority FIFO queue.

In some embodiments, the method also includes:

Acquiring a write command and sending the write command to a low-priority first-in-first-out queue, wherein the write command includes at least one instruction.

In some embodiments, the flash memory controller also includes an arbitration module, which is used to decide and execute the instructions in the first-in-first-out queue;

Methods also include:

The control arbitration module selects a FIFO queue from the high-priority FIFO queue and the low-priority FIFO queue, and executes the instructions in the selected FIFO queue.

In some embodiments, the control arbitration module selects a FIFO queue from the high-priority FIFO queue and the low-priority FIFO queue, and executes the instructions in the selected FIFO queue, including:

Prioritize the execution of instructions in the high-priority first-in-first-out queue;

If the instruction in the low-priority FIFO queue is not executed within the preset time, execute an instruction in the low-priority FIFO queue;

Continue to execute instructions in the high-priority FIFO queue.

In some embodiments, the method also includes:

When all the instructions in the high-priority FIFO queue have been executed, execute the instructions in the low-priority FIFO queue;

If there are new instructions in the high-priority FIFO queue, continue to execute the instructions in the high-priority FIFO queue.

In some embodiments, each instruction is an atomic instruction, and each atomic instruction is executed consecutively during execution.

In some embodiments, the flash memory controller includes at least one channel, and each channel includes a high-priority FIFO queue and a low-priority FIFO queue.

In the second aspect, the embodiment of the present application provides a flash memory controller, which applies the command scheduling method of the first aspect, and the flash memory controller includes:

A high-priority first-in-first-out queue is used to store read commands, wherein the read commands include at least one instruction;

A low-priority first-in-first-out queue for storing write commands, wherein the write commands include at least one instruction;

The arbitration module is used to decide and execute the instructions in the first-in-first-out queue.

In a third aspect, the embodiment of the present application provides a flash memory device, including:

Such as the flash memory controller of the second aspect;

At least one flash medium communicates with the flash controller.

In the fourth aspect, the embodiment of the present application also provides a non-volatile computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by the processor, the processor Execute the command scheduling method as in the first aspect.

The beneficial effects of the embodiment of the present application are: different from the prior art, the command scheduling method provided by the embodiment of the present application is applied to a flash memory controller, and the flash memory controller includes a high-priority first-in-first-out queue and a low-priority First-in-first-out queues, wherein the low-priority first-in-first-out queues are used to store write commands. The command scheduling method includes: obtaining read commands, and sending the read commands to high-priority first-in-first-out queues, wherein the read commands include At least one instruction; each instruction in the high-priority FIFO queue is executed. The write command is stored in the low-priority FIFO queue, the acquired read command is issued to the high-priority FIFO queue, and each instruction in the high-priority FIFO queue is executed. This application can maintain the total bandwidth. In some cases, the read command issued later is executed prior to the write command issued earlier, thereby reducing the delay of the read command.

Description of drawings

One or more embodiments are exemplified by the pictures in the corresponding drawings, and these exemplifications do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the drawings are not limited to scale.

FIG. 1 is a schematic structural diagram of a flash memory device provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a flash memory controller provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a command scheduling provided by an embodiment of the present application;

FIG. 4 is a schematic flowchart of a command scheduling method provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another flash memory controller provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of an arbitration module provided by an embodiment of the present application;

FIG. 7 is a schematic flow diagram of a decision-executing instruction in a first-in-first-out queue provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a refinement process of step S701;

FIG. 9 is a schematic flow diagram of another decision-making execution of instructions in the first-in-first-out queue provided by the embodiment of the present application;

Fig. 10 is a schematic diagram of another command scheduling provided by the embodiment of the present application;

FIG. 11 is a schematic structural diagram of another flash memory controller provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

It should be noted that, if there is no conflict, various features in the embodiments of the present application may be combined with each other, and all of them are within the protection scope of the present application. In addition, although the functional modules are divided in the schematic diagram of the device, and the logical order is shown in the flowchart, in some cases, the division of modules in the device or the sequence shown in the flowchart can be performed in different ways. or the steps described. Furthermore, words such as "first", "second", and "third" used in this application do not limit the data and execution order, but only distinguish the same or similar items with basically the same function and effect.

The technical scheme of the present application is specifically described below in conjunction with the accompanying drawings of the description:

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a flash memory device provided in an embodiment of the present application;

As shown in FIG. 1 , the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110 . Wherein, the flash memory device 100 communicates with the host 200 in a wired or wireless manner to realize data interaction.

The flash memory medium 110, as the storage medium of the flash memory device 100, is also called flash memory, NAND Flash, Flash memory or Flash particles, belongs to a kind of storage device, is a kind of non-volatile memory, and can It can save data for a long time, and its storage characteristic is equivalent to that of a hard disk, so that the flash memory medium 110 can become the basis of the storage medium of various portable digital devices.

The controller 120 includes a processor 121 , a cache 122 , a flash memory controller 123 and an interface 124 .

The processor 121 is respectively connected to the cache memory 122, the flash memory controller 123 and the interface 124, wherein the processor 121 and the cache memory 122, the flash memory controller 123 and the interface 124 can be connected through a bus or other methods, and the processor is used to run the memory stored in The non-volatile software programs, instructions and modules in the register 122 implement any method embodiment of the present application. On this basis, through firmware development, it is also used to be responsible for the core processing of the flash translation layer (Flash translation layer, FTL).

The cache memory 122 is mainly used for caching the read/write command sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read/write command sent by the host 200 .

The flash memory controller 123 is connected with the flash memory medium 110 , the processor 121 and the cache memory 122 , and is used for accessing the back-end flash memory medium 110 and managing various parameters and data I/O of the flash memory medium 110 .

The interface 124 is connected to the host 200, the processor 121 and the buffer 122, and is used to receive the data sent by the host 200, or to receive the data sent by the processor 121 to realize the data transmission between the host 200 and the processor 121. The interface 124 can SATA-2 interface, SATA-3 interface, SAS interface, MSATA interface, PCI-E interface, NGFF interface, CFast interface, SFF-8639 interface and M.2NVME/SATA protocol.

Please refer to FIG. 2. FIG. 2 is a schematic structural diagram of a flash memory controller provided by an embodiment of the present application;

As shown in Figure 2, the flash memory controller includes multiple channels (CH for short), for example: channel 0 (CH 0), channel 1 (CH 1), ..., channel 15 (CH 15), each channel ( CH) includes a first-in-first-out queue (First InputFirst Output, FIFO), and at least one flash memory chip (Die for short) is mounted under each channel (CH), for example: flash memory chip 0 (Die for short) is mounted under channel 0 (CH0) 0), flash memory chip 1 (Die 1), flash memory chip 2 (Die 2) and flash memory chip 3 (Die3), flash memory chip 4 (Die 4) and flash memory chip 5 (Die 5) are mounted under channel 1 (CH 1) , flash memory chip 6 (Die 6) and flash memory chip 7 (Die 7), ..., flash memory chip 60 (Die 60), flash memory chip 61 (Die 61), flash memory chip 62 (Die 62) are mounted under channel 15 (CH 15) 62) and a flash memory chip 63 (Die 63), wherein a plurality of flash memory chips (Die) under the same channel share a group of control buses (bus).

Wherein, the first-in-first-out queue (FIFO) is used for buffering read commands and/or write commands, and follows the first-in-first-out rule, that is, the first command written into the queue is also the first command taken out of the queue. There are multiple flash memory chips (Die) packaged in a flash memory particle, and the flash memory chip (Die) is the basic unit for receiving and executing flash memory commands, and a flash memory chip (Die) can only independently execute one command at a time.

It can be understood that an important function of the flash memory controller is to perform storage operations as a driver of a flash memory chip (Die), and its main operations include erasing, writing and reading. The erasing operation of the flash media is based on a block (Block), and the writing and reading operations are based on a page (Page). A block usually includes hundreds or thousands of pages.

Specifically, after the flash memory controller issues the erase command and address, the flash media starts to perform the erase operation, which usually takes several milliseconds, during which the flash memory controller cannot perform other erasing or erasing of the flash media. Read and write operations need to wait for the erase to complete.

Specifically, after the flash memory controller sends the write command, address and transmits the write data, the flash medium starts to perform the write operation, which usually takes hundreds of microseconds to several milliseconds, during which the flash memory controller can no longer For other erasing or reading and writing operations on the flash media, you need to wait for the writing to complete.

Specifically, after the flash memory controller sends the read command and address, the flash memory medium starts to perform the read operation, which usually takes tens of microseconds, during which time the flash memory controller cannot perform other erasures on the flash memory medium Or read and write operations, you need to wait for the read to complete. After the reading is completed, the data is temporarily stored in the cache space of the flash memory medium, and then the flash memory controller can start to transmit the read data, and the read command ends after the transmission is completed.

Further, when the flash medium is performing erasing, writing, and reading operations, the flash medium is in a busy (Busy) state, and at this time the flash controller can send a query status (Read Status) command to confirm whether the flash medium has completed the corresponding command, and then Confirm whether follow-up operation instructions can be sent. Specifically, after the flash memory controller sends commands and data to a flash memory chip (Die), the flash memory chip (Die) executes the command and is in a busy (Busy) state, and the flash memory controller can communicate to other flash memory chips through the control bus (bus). The chip (Die) issues commands and data. After sending commands and data to other flash memory chips (Die), the flash memory controller can query the flash memory chips that were in the busy (Busy) state by sending a query status (Read Status) command. (Die) Whether to complete the corresponding command, if completed, a follow-up command can be issued to this flash memory chip (Die), so that the bus bandwidth can be fully utilized and the overall performance can be improved.

However, as the performance of flash memory becomes higher and higher, and its functions become more powerful and complex, it becomes more and more difficult for solidified flash memory controllers to meet the flexible control requirements of flash memory. Some flash memory controllers begin to add coprocessors (Coprocessing Center Process Unit, S-CPU), optimize the flexibility of flash memory operation through the combination of software and hardware. The flash memory controller usually adds several coprocessors (S-CPU), and each coprocessor (S-CPU) is responsible for command processing of one or more channels (CH), wherein the coprocessor (S-CPU) is A processor developed and applied to assist the central processing unit in completing processing tasks that it cannot perform or perform inefficiently and ineffectively.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of command scheduling provided by an embodiment of the present application;

In the embodiment of the present application, the flash memory controller includes a coprocessor (S-CPU), and each channel (CH) of the flash memory controller includes a first-in-first-out queue (FIFO). After the upper layer command, the coprocessor (S-CPU) in the flash memory controller splits each upper layer command into at least one instruction and sends it to the hardware first-in-first-out queue (FIFO), and then through the control bus of the channel ( bus) sends instructions and data to each flash memory chip mounted on the channel, and each flash memory chip (Die) executes the corresponding command and is in a busy (Busy) state.

As shown in Figure 3, the host issues four commands in sequence: upper-layer command A, upper-layer command B, upper-layer command C, and upper-layer command D. The coprocessor (S-CPU) splits the upper-layer commands and passes them through the control bus of the channel. (bus) sends corresponding instructions and data to flash memory chip 0 (Die 0), flash memory chip 1 (Die 1), flash memory chip 2 (Die 2) and flash memory chip 3 (Die 3), and each flash memory chip (Die 3) ) executes the corresponding command and is in a busy (Busy) state.

Specifically, after the coprocessor (S-CPU) obtains the upper-layer command A, it splits the upper-layer command A to obtain instruction A0, and sends the instruction A0 to the first-in-first-out queue (FIFO), and then the coprocessor (S-CPU) The CPU) obtains the upper-level command B, the upper-level command C, and the upper-level command D in sequence, and splits the upper-level command B to obtain instruction B0, splits the upper-level command C to obtain instruction C0 and instruction C2, and splits the upper-level command D to obtain instruction D0 and instruction D2, and then sequentially issue instruction B0, instruction C0, and instruction D0 to the first-in-first-out queue (FIFO).

Further, the coprocessor (S-CPU) sends corresponding instructions and data to each flash memory chip mounted on the channel through the control bus (bus) of the channel, for example: the upper layer command A is the flash memory chip 0 (Die 0) Write command, instruction A0 is the write instruction and data transmission instruction of upper layer command A, the first instruction in the first-in first-out queue (FIFO) is instruction A0, therefore, send instruction A0 to flash memory chip 0 (Die 0), among them, The data transmission instruction included in the instruction A0 will take a long time, and then the flash memory chip 0 (Die 0 ) starts to perform the write operation and is in a busy (Busy) state.

Further, the coprocessor (S-CPU) continues to send the next instruction B0 in the first-in-first-out queue (FIFO) to the flash memory chip 1 (Die1), and then sends the first-in-first-out queue ( The command C0 in the FIFO) sends the command D0 in the first-in-first-out queue (FIFO) to the flash memory chip 3 (Die3). When each flash memory chip completes the read operation or write operation and exits the busy (Busy) state, the coprocessor (S-CPU) continues to issue instructions C1, instruction D1, and instruction A1 to the first-in-first-out queue (FIFO) in order to query instructions Whether C0, instruction D0, and instruction A0 have been executed, and respectively send the instruction C1, instruction D1, and Instruction A1.

Further, after the instruction C0 and instruction D0 are in the execution completion state, the coprocessor (S-CPU) continues to issue the instruction C2 and instruction D2 to the first-in-first-out queue (FIFO), and send them to the flash memory chip 2 (Die2 ), the flash memory chip 3 (Die3) issues the instruction C2 and the instruction D2 in the first-in-first-out queue (FIFO) to carry out the data transmission of the upper-layer command C and the upper-layer command D respectively, and then the execution of the upper-layer command C and the upper-layer command D is completed. After the coprocessor (S-CPU) sends instruction A1 and instruction B1 in the first-in-first-out queue (FIFO) to flash memory chip 0 (Die0) and flash memory chip 1 (Die1) respectively, upper-layer command A and upper-layer command B follow The execution is completed.

Among them, the upper layer command A is the write command of the flash memory chip 0 (Die 0), the upper layer command B is the write command of the flash memory chip 1 (Die 1), the upper layer command C is the read command of the flash memory chip 2 (Die 2), and the upper layer command D is the read command of the flash memory chip 3 (Die 3), the command A0 is the write command and data transmission command of the upper command A, the command B0 is the write command and data transmission command of the upper command B, and the command C0 is the read command of the upper command C, Instruction D0 is the read instruction of upper-layer command D, instruction A1 is the query status instruction of upper-layer command A, instruction B1 is the query status instruction of upper-layer command B, instruction C1 is the query status instruction of upper-layer command C, and instruction D1 is the query status instruction of upper-layer command D. Query status instruction, instruction C2 is the read data transmission instruction of the upper layer command C, and instruction D2 is the read data transfer instruction of the upper layer command D.

It is understandable that the response delay of flash memory devices, such as solid-state drives, to read and write commands is an important indicator for judging the quality of a product. The faster the host side requires the response of read and write commands, the better. Since the data of the write command is transmitted from the host to the SSD, the SSD returns a completion signal to the host, so the subsequent delay in writing data to the flash media is invisible to the host; while the read command must wait for the data to be transferred from the flash to the host. After the media is read, further transmission to the host is considered complete, so the delay of the read command on the flash memory side is an important part of the delay of the entire read command.

However, considering the cost and power consumption, the coprocessor (S-CPU) used by the flash controller will be as few as possible, so the computing power of the coprocessor (S-CPU) is usually relatively tight. Therefore, the coprocessor (S-CPU) will try to fill up the hardware first-in-first-out queue (FIFO) to minimize the bus waste caused by the untimely scheduling of the coprocessor (S-CPU), thereby increasing the bandwidth. However, when a new read command comes, it is necessary to complete the issued command in the first-in-first-out queue (FIFO) before starting to process the new read command, which will cause a large delay in the read command, for example: 3. The central coprocessor (S-CPU) first issues instruction A0 and instruction B0. When the read command C is received, although the instruction B0 has not yet started to be executed, the position of the read instruction C0 in the first-in-first-out queue (FIFO) After the instruction B0, the instruction C0 can only be executed after the instruction B0 is executed, resulting in a large read delay.

Based on this, an embodiment of the present application provides a command scheduling method, so that the read command issued later is executed prior to the write command issued earlier, so as to reduce the delay of the read command while maintaining the total bandwidth.

Please refer to FIG. 4. FIG. 4 is a schematic flowchart of a command scheduling method provided in an embodiment of the present application;

Wherein, the command scheduling method is applied to a flash memory controller, and the flash memory controller includes a high-priority first-in-first-out queue (FIFO-H) and a low-priority first-in-first-out queue (FIFO-L), wherein the low priority first-in-first-out queue (FIFO-L) The dequeue is used to store write commands.

Specifically, please refer to FIG. 5, which is a schematic structural diagram of another flash memory controller provided by an embodiment of the present application;

As shown in Figure 5, the flash memory controller includes at least one channel (CH), for example: channel 0 (CH 0), channel 1 (CH1), ..., channel 15 (CH 15), each channel (CH) It includes a high-priority first-in-first-out queue (FIFO-H) and a low-priority first-in-first-out queue (FIFO-L). At least one flash memory chip (Die for short) is mounted under each channel (CH), for example: channel 0 Mount flash chip 0 (Die 0), flash memory chip 1 (Die 1), flash memory chip 2 (Die 2) and flash memory chip 3 (Die 3) under (CH 0), mount flash memory chips under channel 1 (CH 1) 4 (Die 4), flash memory chip 5 (Die 5), flash memory chip 6 (Die 6) and flash memory chip 7 (Die7), ..., flash memory chip 60 (Die 60), flash memory Die 61 (Die61), flash memory chip 62 (Die 62) and flash memory chip 63 (Die 63), wherein multiple flash memory dies (Die) under the same channel share a set of control buses (bus).

In the embodiment of the present application, the flash memory controller also includes at least one coprocessor (S-CPU), and the coprocessor (S-CPU) is used to split the upper layer command sent by the host into at least one instruction, and pass the control bus (bus) sends commands to the corresponding high priority first-in first-out queue (FIFO-H) and/or low priority first-in first-out queue (FIFO-L).

As shown in Figure 4, the command scheduling method includes:

Step S401: Obtain a read command, and issue the read command to a high-priority first-in-first-out queue;

Specifically, the read command includes at least one instruction, and the flash memory controller receives the read command sent by the host, and controls the coprocessor (S-CPU) to split the read command to obtain a read instruction and a read data transfer instruction, and then through the control bus ( bus) sends the read command to a high-priority first-in-first-out queue (FIFO-H).

In the embodiment of this application, before obtaining the read command, the method includes:

Determine the high-priority FIFO queue and the low-priority FIFO queue.

Specifically, the flash memory controller determines a high-priority first-in-first-out queue (FIFO-H) and a priority first-in-first-out queue (FIFO-L) before obtaining the read command and/or write command, wherein the high priority first-in-first-out queue The output queue (FIFO-H) and the priority first-in-first-out queue (FIFO-L) have the same bit width and depth.

In the embodiment of the present application, the method also includes:

Obtain the write command and issue the write command to the low-priority first-in-first-out queue.

Specifically, the write command includes at least one instruction, and the flash memory controller receives the write command sent by the host, and controls the coprocessor (S-CPU) to split the write command to obtain a write instruction and a data transmission instruction, and then transmits the instruction through the control bus (bus ) sends the write command and the data transmission command to a low-priority first-in-first-out queue (FIFO-L).

In the embodiment of the present application, the flash memory controller also includes an arbitration module, which is used to decide and execute the instructions in the first-in-first-out queue, wherein the arbitration module includes but is not limited to a round-robin arbitrator (Round-Robin), a fixed priority Arbitrator (Fixed-Priority) and other arbitrators. Preferably, a fixed-priority arbiter (Fixed-Priority) is used in this embodiment of the application.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of an arbitration module provided by an embodiment of the present application;

As shown in FIG. 6 , the arbitration module is respectively connected to a high-priority first-in-first-out queue (FIFO-H), a priority first-in-first-out queue (FIFO-L), and a control bus (bus).

Specifically, the arbitration module has two different interfaces to connect to the high-priority FIFO queue and the priority FIFO queue respectively, so as to identify the source of each instruction.

Step S402: Execute each instruction in the high-priority FIFO queue.

Specifically, the flash memory controller controls the arbitration module to decide to execute each instruction in the high-priority first-in-first-out queue (FIFO-H).

Please refer to FIG. 7. FIG. 7 is a schematic flowchart of a decision-making and executing instruction in the first-in-first-out queue provided by the embodiment of the present application;

As shown in Figure 7, the process of deciding to execute the instructions in the first-in-first-out queue includes:

Step S701: the control arbitration module selects a first-in-first-out queue in a high-priority first-in-first-out queue (FIFO-H) and a low-priority first-in-first-out queue (FIFO-L), and executes the selected first-in-first-out queue instructions.

Specifically, please refer to FIG. 8, which is a schematic diagram of a detailed flow of step S701;

As shown in Figure 8, step S701: the control arbitration module selects a FIFO queue from the high-priority FIFO queue and the low-priority FIFO queue, and executes the instructions in the selected FIFO queue, including :

Step S7011: Prioritize the execution of instructions in the high-priority FIFO queue;

Specifically, the arbitration module preferentially executes the instructions in the high-priority first-in-first-out queue (FIFO-H), sends the instructions to the corresponding flash memory chip (Die) through the control bus (bus), and the flash memory chip (Die) executes the instruction. instruction.

Step S7012: judging whether to execute the instructions in the low-priority FIFO queue within the preset time;

Specifically, the preset time is configured by a register and determined according to the cycle number of the hardware-driven clock. For example, if the clock is 600MHz and the configuration is 600*1024, the preset time is 1ms.

Further, if the instruction in the low-priority first-in-first-out queue (FIFO-L) is not executed within the preset time, then enter step S7013: execute an instruction in the low-priority first-in-first-out queue; Execute the instructions in the low-priority FIFO-L queue within the time, then return to step S7011: preferentially execute the instructions in the high-priority FIFO-L queue.

Step S7013: Execute an instruction in the low-priority FIFO queue;

Specifically, if the instruction in the low-priority first-in-first-out queue (FIFO-L) is not executed within the preset time, the arbitration module passes an instruction in the low-priority first-in-first-out queue (FIFO-L) through the control The bus (bus) issues to the corresponding flash memory chip (Die), and the flash memory chip (Die) executes the instruction.

Step S7014: Continue to execute the instructions in the high-priority FIFO queue.

Specifically, after the arbitration module executes an instruction in the low-priority first-in-first-out queue (FIFO-L), if there are still instructions in the high-priority first-in-first-out queue (FIFO-H), the arbitration module will continue to send the high-priority Each instruction in the priority first-in-first-out queue (FIFO-H) is sent to the corresponding flash memory chip (Die) through the control bus (bus), and the flash memory chip (Die) executes the instruction.

In the embodiment of the present application, by judging whether to execute the instructions in the low-priority FIFO queue within the preset time, the present application can reduce the delay of the read command and ensure the timely execution of the write command.

In the embodiment of the present application, each instruction in the high-priority first-in-first-out queue (FIFO-H) and the low-priority first-in-first-out queue (FIFO-L) is an atomic instruction, and each atomic instruction is executed Continuous execution during the process, for example: write command A0 includes write command A0-Cmd, write address A0-Addr, and write data A0-Data, which is an atomic operation that cannot be interrupted and needs to be executed continuously. The issuing sequence is : Start→A0-Cmd→A0-Addr→A0-Data→End, or, the issuing sequence of the atomic instruction of the read command is: Start→0x00→address→0x30→End, the instructions between Start-End need to be continuous Executes and cannot be interrupted.

It is understandable that because flash memory operations need to follow certain rules and cannot be randomly ordered, all atomic instructions start with the Start instruction and end with the End instruction. The instructions between Start-End need to be executed continuously and cannot be blocked. broken.

In the embodiment of the present application, through the continuous execution of each atomic instruction during the execution process, the present application can ensure that the atomic instructions are not interrupted, which is applicable to the atomicity rules of flash memory type operations.

Please refer to FIG. 9. FIG. 9 is a schematic flow diagram of another decision-making instruction in the first-in-first-out queue provided by the embodiment of the present application;

As shown in Figure 9, the process of deciding to execute the instructions in the first-in-first-out queue includes:

Step S901: Execute the instructions in the low-priority FIFO queue when all the instructions in the high-priority FIFO queue have been executed;

Specifically, when all the instructions in the high-priority first-in-first-out queue (FIFO-H) have been executed, the arbitration module sends the instructions in the low-priority first-in-first-out queue (FIFO-L) through the control bus (bus) Send it to the corresponding flash memory chip (Die), and the flash memory chip (Die) executes the instruction.

Step S902: judging whether there is a new instruction in the high-priority FIFO queue;

Specifically, if there is a new instruction in the high-priority FIFO-H, then enter step S903: continue to execute the instruction in the high-priority FIFO-H; if the high-priority FIFO-H If there is no new instruction in -H), then return to step S901, and continue to execute the instructions in the low-priority FIFO queue.

Step S903: Continue to execute the instructions in the high-priority FIFO queue.

Specifically, if there are new instructions in the high-priority first-in-first-out queue (FIFO-H), the arbitration module sends each instruction in the high-priority first-in-first-out queue to the corresponding flash memory through the control bus (bus) Chip (Die), the instruction is executed by the flash memory chip (Die), until the next time the preset time is reached, the instruction in the low-priority first-in-first-out queue (FIFO-L) or the high-priority first-in-first-out queue is not executed When the execution of the instruction is completed, the instruction in the low-priority first-in-first-out queue (FIFO-L) is executed.

Please refer to FIG. 10. FIG. 10 is a schematic flowchart of another command scheduling provided by the embodiment of the present application;

In the embodiment of the present application, after the flash memory device receives the upper layer commands sequentially issued by the host, the coprocessor (S-CPU) in the flash memory controller splits each upper layer command into at least one instruction, and writes The corresponding instruction of the command is issued to the low priority first-in-first-out queue (FIFO-L), and the corresponding instruction of the read command is issued to the high-priority first-in-first-out queue (FIFO-H). The arbitration module of the channel sends instructions and data to each flash memory chip mounted on the channel through the control bus (bus) of the channel, and each flash memory chip (Die) executes the corresponding command and is in a busy (Busy) state.

As shown in Figure 10, the host sends four commands in sequence: upper-layer command A, upper-layer command B, upper-layer command C, and upper-layer command D. The coprocessor (S-CPU) splits the upper-layer command into at least one instruction, and the next sent to the corresponding high-priority first-in-first-out queue (FIFO-H) or low-priority first-in-first-out queue (FIFO-L), and then the arbitration module decides to execute the instruction in which first-in-first-out queue and passes the control of the channel The bus (bus) sequentially sends corresponding instructions and data to flash memory chip 0 (Die 0), flash memory chip 1 (Die1), flash memory chip 2 (Die 2) and flash memory chip 3 (Die 3), and each flash memory chip (Die 3) ) executes the corresponding command and is in a busy (Busy) state.

Specifically, after the coprocessor (S-CPU) obtains the upper-layer command A, it splits the upper-layer command A to obtain instruction A0, and sends the instruction A0 to the low-priority first-in-first-out queue (FIFO-L), and then the coprocessor (S-CPU) The processor (S-CPU) sequentially obtains the upper-layer command B, upper-layer command C, and upper-layer command D, and splits the upper-layer command B to obtain instruction B0, splits the upper-layer command C to obtain instruction C0 and instruction C2, and splits the upper-layer command D Split to obtain instruction D0 and instruction D2, and then issue instruction B0 to the low-priority first-in-first-out queue (FIFO-L), instruction C0, and instruction D0 to the high-priority first-in-first-out queue (FIFO-H) in sequence.

It is understandable that it takes time to issue upper-level commands, so the time for issuing instructions A0, B0, C0, and D0 is sequentially increased, not in parallel at an instant. Since the command A0 is issued first, there is no command in the high priority FIFO-H, and there is only command A0 in the low priority FIFO-L, so the arbitration module will send the flash chip first 0 (Die 0) sends command A0, and flash memory chip 0 (Die 0) starts to execute the write operation and is in a busy (Busy) state.

Since the execution of instruction A0 also takes a period of time, and this time is often much longer than the time for the software to issue a single instruction, so after instruction A0 is executed, instruction C0 and instruction D0 are already in the high-priority first-in-first-out queue (FIFO- H), so the next instruction C0 and instruction D0 can be executed first. After the execution of instruction C0 and instruction D0 is completed, there is no instruction temporarily in the high-priority FIFO-H, so the arbitration module can then send the low-priority FIFO-L to the flash memory chip 1 (Die1). ), the coprocessor (S-CPU) will continue to issue instructions C1 and D1 to the high-priority first-in-first-out queue (FIFO-H) during the period during which flash memory chip 1 (Die1) executes instruction B0 , the arbitration module sends command C1 and command D1 to flash memory chip 3 (Die3) and flash memory chip 0 (Die0) respectively, to query whether the execution of command C0 and command D0 is completed.

Further, after the instruction C0 and instruction D0 are in the execution completion state, the instruction C2 and instruction D2 are already in the high-priority first-in-first-out queue (FIFO-H), and the arbitration module continues to send flash memory chips 2 (Die2), Flash memory chip 3 (Die3) issues command C2 and command D2 to perform data transmission of upper layer command C and upper layer command D respectively. 1. After the flash memory chip 1 (Die1) issues the instruction A1 and the instruction B1 in the low-priority first-in-first-out queue (FIFO-L), the upper-layer command A and the upper-layer command B are executed accordingly.

Among them, the upper layer command A is the write command of the flash memory chip 0 (Die 0), the upper layer command B is the write command of the flash memory chip 1 (Die 1), the upper layer command C is the read command of the flash memory chip 2 (Die 2), and the upper layer command D is the read command of the flash memory chip 3 (Die 3), the command A0 is the write command and data transmission command of the upper command A, the command B0 is the write command and data transmission command of the upper command B, and the command C0 is the read command of the upper command C, Instruction D0 is the read instruction of upper-layer command D, instruction A1 is the query status instruction of upper-layer command A, instruction B1 is the query status instruction of upper-layer command B, instruction C1 is the query status instruction of upper-layer command C, and instruction D1 is the query status instruction of upper-layer command D. Query status instruction, instruction C2 is the read data transmission instruction of the upper layer command C, and instruction D2 is the read data transfer instruction of the upper layer command D.

In the embodiment of the present application, by providing a command scheduling method, it is applied to the flash controller, and the flash controller includes a high priority first-in-first-out queue and a low-priority first-in-first-out queue, wherein the low-priority first-in-first-out queue For storing write commands, the command scheduling method includes: obtaining a read command, and sending the read command to a high-priority first-in-first-out queue, wherein the read command includes at least one instruction; executing each command in the high-priority first-in-first-out queue an instruction. The write command is stored in the low-priority FIFO queue, the acquired read command is issued to the high-priority FIFO queue, and each instruction in the high-priority FIFO queue is executed. This application can maintain the total bandwidth. In some cases, the read command issued later is executed prior to the write command issued earlier, thereby reducing the delay of the read command.

Please refer to FIG. 11 again. FIG. 11 is a schematic structural diagram of another flash memory controller provided by an embodiment of the present application;

As shown in FIG. 11 , the flash controller 111 includes at least one high-priority FIFO queue 1111 , at least one low-priority FIFO queue 1112 and at least one arbitration module 1113 . Wherein, FIG. 11 takes a high-priority FIFO queue 1111 , a low-priority FIFO queue 1112 and an arbitration module 1113 as examples.

Specifically, the flash memory controller 111 includes at least one channel (CH), and each channel (CH) includes a high-priority FIFO queue 1111, a low-priority FIFO queue 1112, and an arbitration module 1113, wherein , the arbitration module 1113 communicates with the high-priority FIFO queue 1111 and the low-priority FIFO queue 1112 respectively through two ports.

The flash memory controller 111 is configured to execute the command scheduling method in any of the above embodiments, for example: acquire a read command, and issue the read command to a high-priority first-in-first-out queue, wherein the read command includes at least one instruction; Each instruction in the priority FIFO queue.

The high-priority first-in-first-out queue 1111 is used to store read commands, wherein the read commands include at least one instruction.

The low-priority FIFO queue 1112 is used to store write commands, wherein the write commands include at least one instruction.

The arbitration module 1113 is used for decision-making to execute the instructions in the first-in-first-out queue, for example: preferentially execute the instructions in the high-priority first-in-first-out queue 111; instruction, then execute an instruction in the low-priority FIFO queue 1112; continue to execute the instructions in the high-priority FIFO queue 1111. Or, when all instructions in the high-priority FIFO queue 1111 have been executed, execute the instructions in the low-priority FIFO queue 1112; if there are new instructions in the high-priority FIFO queue 1111, Then continue to execute the instructions in the high-priority FIFO queue 1111.

The embodiment of the present application also provides a non-volatile computer storage medium, the computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors, for example, performing any of the above-mentioned method embodiments. The command scheduling method, for example, executes the steps described above.

The above-described device or device embodiments are only illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as modular units may or may not be physical units, that is It can be located in one place, or it can be distributed to multiple network module units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solutions or the part that contributes to related technologies can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, disk , optical disk, etc., including several instructions until a computer device (which may be a personal computer, server, or network device, etc.) executes the methods of each embodiment or some parts of the embodiment.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; under the thinking of the present application, the above embodiments or technical features in different embodiments can also be combined, The steps can be performed in any order, and there are many other variations of the different aspects of the application as above, which are not presented in detail for the sake of brevity; although the application has been described in detail with reference to the preceding examples, those of ordinary skill in the art It should be understood that it is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technology of each embodiment of the application. scope of the program.

Claims (10)

1. The command scheduling method is characterized by being applied to a flash memory controller, wherein the flash memory controller comprises a high-priority first-in first-out queue and a low-priority first-in first-out queue, and the low-priority first-in first-out queue is used for storing write commands;

the method comprises the following steps:

acquiring a read command and issuing the read command to the high-priority first-in first-out queue, wherein the read command comprises at least one instruction;

each of the instructions in the high priority first-in-first-out queue is executed.

2. The method of claim 1, wherein prior to the acquiring the read command, the method comprises:

determining the high priority first-in first-out queue and the low priority first-in first-out queue;

the method further comprises the steps of:

and acquiring a write command and issuing the write command to the low-priority first-in-first-out queue, wherein the write command comprises at least one instruction.

3. The method of claim 1 or 2, wherein the flash memory controller further comprises an arbitration module for deciding to execute instructions in a first-in-first-out queue;

the method further comprises the steps of:

and controlling the arbitration module to select one first-in first-out queue from the high-priority first-in first-out queue and the low-priority first-in first-out queue, and executing the instruction in the selected first-in first-out queue.

4. The method of claim 3, wherein the controlling the arbitration module to select one of the high priority fifo queue and the low priority fifo queue and execute instructions in the selected fifo queue comprises:

preferentially executing the instructions in the high-priority first-in first-out queue;

if the instruction in the low priority first-in first-out queue is not executed within the preset time, executing one instruction in the low priority first-in first-out queue;

and continuing to execute the instruction in the high-priority first-in first-out queue.

5. The method according to claim 4, wherein the method further comprises:

executing the instructions in the low priority first-in first-out queue when all instructions in the high priority first-in first-out queue are executed;

and if the high-priority first-in first-out queue has a new instruction, continuing to execute the instruction in the high-priority first-in first-out queue.

6. The method of any of claims 1-2 or 4-5, wherein each of the instructions is an atomic instruction, each of the atomic instructions being executed continuously during execution.

7. The method of any of claims 1-2 or 4-5, wherein the flash memory controller comprises at least one channel, each channel comprising one of the high priority first-in-first-out queues and one of the low priority first-in-first-out queues.

8. A flash memory controller, wherein the method of any one of claims 1-7 is applied, the flash memory controller comprising:

a high priority first-in first-out queue for storing read commands, wherein the read commands comprise at least one instruction;

a low priority first-in first-out queue for storing write commands, wherein the write commands include at least one instruction;

and the arbitration module is used for deciding to execute the instructions in the first-in first-out queue.

9. A flash memory device, comprising:

the flash memory controller of claim 8;

and the at least one flash memory medium is in communication connection with the flash memory controller.

10. A non-transitory computer readable storage medium storing computer executable instructions which, when executed by a processor, cause the processor to perform the command scheduling method of any one of claims 1-7.

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