CN116225148A - Current mirror circuit, chip and electronic equipment - Google Patents

Abstract

Embodiments of the present disclosure provide a current mirror circuit, a chip, and an electronic device, the current mirror circuit including: the circuit comprises a reference current generation circuit, an input stage transistor circuit and an output stage transistor circuit, wherein the input stage transistor circuit and the output stage transistor circuit form a cascode current mirror structure, and the reference current generation circuit is configured to generate a reference current; the input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current, so as to adjust the mirror proportion; the output stage transistor circuit is configured to output different output currents according to different mirror ratios. The current mirror circuit solves the problems of inconvenient operation and large circuit area existing in the conventional current mirror circuit when the current mirror circuit determines that the variable output current is required.

Description

Current mirror circuit, chip and electronic equipment

technical field

Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to current mirror circuits, chips and electronic devices.

Background technique

At present, the current mirror is widely used in the design of various analog circuits. Its characteristic is that the output current is a "copy" of the input current in a certain proportion, and is used to provide multiple constant currents. Usually, when the current mirror circuit is determined, the ratio of the output current to the input current is fixed, that is, the ratio of the mirror current is fixed. Therefore, if a variable output current needs to be obtained, it needs to be realized through different circuits. For example, for the commonly used current mirror circuit in Figure 1, the mirror ratio corresponds to the width-to-length ratio of Mn1 and Mn2. If the width-to-length ratio of Mn1 and Mn2 is 1:1, the ratio of the input current Iref to the output current Io It is also 1:1, that is, Io=Iref, that is, the mirror image ratio is 1; if the width-to-length ratio of Mn1 and Mn2 is 1:10, the ratio of the input current Iref to the output current Io is also 1:10, that is, Io= 10*Iref, that is, the mirror ratio is 10. According to the current mirror circuit in Figure 1, it can be seen that if you want to change the ratio of the mirror current, you need to change the width-to-length ratio of Mn1 and Mn2, that is, you need to change the circuit, which is very inconvenient. In addition, for a current mirror circuit with a large mirror ratio, since a larger aspect ratio needs to be set, the area of the circuit will be greatly increased.

To sum up, when the existing current mirror circuit is determined and needs to obtain a variable output current, the problems of inconvenient operation and large circuit area need to be solved urgently.

Contents of the invention

The embodiments described herein provide a current mirror circuit, a chip and an electronic device, in order to provide a current mirror circuit with an adjustable mirror ratio.

According to the first aspect of the present disclosure, a current mirror circuit is provided, including: a reference current generating circuit, an input-stage transistor circuit, and an output-stage transistor circuit, the input-stage transistor circuit and the output-stage transistor circuit form a common-source common A gate current mirror structure, wherein the reference current generation circuit is configured to generate a reference current; the input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current, thereby adjusting Mirror ratio: the output stage transistor circuit is configured to output different output currents according to different mirror ratios.

Optionally, the input stage transistor circuit includes: a first transistor, a second transistor, a third transistor, and a resistor, wherein the first pole of the first transistor is respectively coupled to the control pole of the first transistor, the The first pole of the third transistor, the output terminal of the reference current generating circuit, the second pole of the first transistor is coupled to the ground terminal; the first pole of the second transistor is coupled to the third transistor The second pole, the second pole of the second transistor is coupled to one end of the resistor, and the control pole of the second transistor is respectively coupled to the first pole of the third transistor and the input of the output stage transistor circuit terminal; the control electrode of the third transistor is coupled to the control voltage; the other end of the resistor is coupled to the ground terminal.

Optionally, the output stage transistor circuit includes: a fourth transistor, wherein a first pole of the fourth transistor outputs the output current, a second pole of the fourth transistor is coupled to a ground terminal, and the first The control electrodes of the four transistors are used as the input terminals of the output-stage transistor circuit and are coupled to the input-stage transistor circuit.

Optionally, the reference current generating circuit includes: a current source, wherein one end of the current source is connected to a power supply voltage, and the other end of the current source is coupled to the input stage as an output end of the reference current generating circuit transistor circuit.

Optionally, the control voltage is greater than or equal to the sum of the gate-source voltage of the third transistor and the overdrive voltage of the second transistor.

Optionally, the aspect ratio of the second transistor is N times that of the first transistor, where N is greater than or equal to 80.

Optionally, the width-to-length ratio of the second transistor is equal to the width-to-length ratio of the fourth transistor.

Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type transistors.

According to a second aspect of the present disclosure, there is provided a chip comprising the current mirror circuit according to any one of the first aspects.

According to a third aspect of the present disclosure, an electronic device is provided, including the chip described in the second aspect.

The current mirror circuit in the embodiment of the present disclosure, the chip and the current mirror circuit in the electronic device include a reference current generation circuit, an input-level transistor circuit, and an output-level transistor circuit, and the input-level transistor circuit and the output-level transistor circuit form a cascode The current mirror structure, wherein, the reference current generation circuit is configured to generate a reference current; the input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current, thereby adjusting the mirror ratio; the output stage transistor circuit , are configured to output different output currents according to different mirror ratios. It can be seen that the input stage transistor circuit in the current mirror circuit of the embodiment of the present disclosure can adjust the equivalent transconductance of the input stage according to the change of the reference current. Under the premise that the equivalent transconductance of the output stage is determined, the equivalent transconductance of the input stage The change of the transconductance is equivalent to changing the ratio of the equivalent transconductance of the input stage to the output stage. If the ratio of the equivalent transconductance changes, the ratio of the corresponding output current to the input current will change, that is, the mirror ratio will change, so that The current mirror circuit with adjustable mirror ratio can obtain variable output current based on the adjustable mirror ratio without changing the circuit structure.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be known that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure. in:

Fig. 1 is an exemplary circuit diagram of an existing current mirror circuit;

Fig. 2 is a schematic block diagram of a current mirror circuit according to an embodiment of the present disclosure

3 is an exemplary circuit diagram of a current mirror circuit according to an embodiment of the present disclosure;

4 is a schematic diagram of a curve showing the ratio of the output current to the reference current Iref as the reference current Iref varies according to an embodiment of the present disclosure;

Elements in the drawings are schematic and not drawn to scale.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts also fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and related technologies, and will not be interpreted in an idealized or overly formal manner, Unless otherwise expressly defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

In all the embodiments of the present disclosure, since the source and the drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current direction between the source and the drain of the N-type transistor and the P-type transistor is opposite , therefore, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is called the control pole, and the remaining two ends of the MOS transistor are respectively called the first pole and the second pole. In addition, terms such as "first" and "second" are only used to distinguish one element (or a part of a element) from another element (or another part of a element).

In order to solve the problems of inconvenient operation and large circuit area in the existing current mirror circuit when the current mirror circuit is determined and needs to obtain a variable output current, a new current mirror circuit is proposed. The current mirror circuit of the embodiment of the present disclosure enables the input stage transistor circuit to adjust the equivalent transconductance of the input stage according to the change of the reference current Iref, thereby obtaining a current mirror circuit with an adjustable mirror ratio, and furthermore, without changing the circuit structure. A variable output current is obtained based on an adjustable mirror ratio. The current mirror circuit of the present disclosure will be described in detail below.

2 is a schematic block diagram of a current mirror circuit 100 according to an embodiment of the present disclosure, including: a reference current generation circuit 110, an input-stage transistor circuit 120, an output-stage transistor circuit 130, an input-stage transistor circuit 120 and an output stage The transistor circuit 130 forms a cascode current mirror structure. The specific cascode current mirror structure refers to a structure in which the transistors in the input stage transistor circuit 120 and the output stage transistor circuit 130 are cascoded, and the cascode structure is a commonly used structure in current mirror circuits.

In FIG. 2 , the reference current generation circuit 110 is configured to generate a reference current Iref. The reference current Iref is the input current in the current mirror circuit, and the way to generate the reference current Iref is not limited, that is, the structure of the reference current generating circuit 110 is not limited, for example, it can be a current source, or a combined structure of a voltage source and impedance .

The input-stage transistor circuit 120 is coupled to the reference current generating circuit 110 and the output-stage transistor circuit 130 respectively, and the input-stage transistor circuit 120 is composed of transistors. The specific input stage transistor circuit 120 is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current Iref, thereby adjusting the mirror ratio. The equivalent transconductance of the input stage is the equivalent transconductance of the branch corresponding to the input current (reference current Iref) in the current mirror structure, that is, the equivalent transconductance of the transistor circuit 120 of the input stage. On the premise that the equivalent transconductance of the output stage is determined, adjusting the equivalent transconductance of the input stage is equivalent to changing the ratio of the equivalent transconductance of the input stage to the output stage, the ratio of the equivalent transconductance changes, and the corresponding output current The ratio of I4 to the input current will change, that is, the mirror ratio will change, thus obtaining a current mirror circuit with adjustable mirror ratio.

The output stage transistor circuit 130 is configured to output different output currents I4 according to different mirror ratios. The ratio of the output current I4 to the input current (reference current Iref) is a mirror ratio, so the corresponding output current I4 can be output according to different mirror ratios. In practical applications, the output stage transistor circuit 130 can be one output current branch; it can also be a plurality of output current branches connected in parallel, and each output current branch forms a common source with the input stage transistor circuit 120 respectively. Common gate current mirror structure.

According to the above description, the input stage transistor circuit 120 in the current mirror circuit of the embodiment of the present disclosure can adjust the equivalent transconductance of the input stage according to the change of the reference current Iref. On the premise that the equivalent transconductance of the output stage is determined, the input stage’s The change of the equivalent transconductance is equivalent to changing the ratio of the equivalent transconductance of the input stage to the output stage, the ratio of the equivalent transconductance changes, and the corresponding ratio of the output current I4 to the input current (reference current Iref) will change, That is, the mirror ratio will change, so that a current mirror circuit with adjustable mirror ratio can be obtained.

Further, as shown in FIG. 3 , the embodiment of the present disclosure provides an exemplary circuit diagram of a current mirror circuit. In FIG. 3 , the input stage transistor circuit 120 includes: a first transistor Mn1, a second transistor Mn2, a third transistor Mn3, and a resistor R, wherein the first poles of the first transistor Mn1 are respectively coupled to the first transistor Mn1 the control electrode of the third transistor Mn3, the output terminal of the reference current generation circuit 110, the second electrode of the first transistor Mn1 is coupled to the ground terminal; the first electrode of the second transistor Mn2 The pole is coupled to the second pole of the third transistor Mn3, the second pole of the second transistor Mn2 is coupled to one end of the resistor R, and the control poles of the second transistor Mn2 are respectively coupled to the third transistor The first pole of Mn3 is the input terminal of the output stage transistor circuit 130; the control pole of the third transistor Mn3 is coupled to the control voltage; the other end of the resistor R is coupled to the ground terminal. Wherein, the control voltage is greater than or equal to the sum of the gate-source voltage of the third transistor Mn3 and the overdrive voltage of the second transistor Mn2. The width-to-length ratio of the second transistor Mn2 is N times the width-to-length ratio of the first transistor Mn1 , wherein N is greater than or equal to 80. Setting N to be greater than or equal to 80 is to satisfy that the equivalent transconductance of the second transistor Mn2 is much smaller than the equivalent transconductance of the second transistor Mn2 to a certain extent. Of course, the value of N can be adjusted adaptively in practical applications. In addition, the first transistor Mn1, the second transistor Mn2, and the third transistor Mn3 are N-type transistors.

As shown in FIG. 3 , the output stage transistor circuit 130 includes: a fourth transistor Mn4, wherein the first pole of the fourth transistor Mn4 outputs the output current I4, and the second pole of the fourth transistor Mn4 is coupled to ground terminal, the control electrode of the fourth transistor Mn4 is coupled to the input-stage transistor circuit 120 as the input terminal of the output-stage transistor circuit 130 . In addition, the fourth transistor Mn4 is an N-type transistor

As shown in Figure 3, the reference current generation circuit 110 includes: a current source 111, wherein one end of the current source 111 is connected to the power supply voltage Vdd, and the other end of the current source 111 is used as the output end of the reference current generation circuit 110 coupled to the input stage transistor circuit 120 .

The working principle of the current mirror circuit 100 of the embodiment of the present disclosure is described in conjunction with the circuit diagram in FIG. 3: according to the change of the reference current Iref, the change of the mirror image ratio can be divided into four intervals, and the four intervals are described below. Principle description.

Section 1: The product of the reference current Iref and the resistance R is much smaller than the gate-source voltage of the second transistor Mn2, that is, Iref*R<<Vgs2, where the much smaller value can be less than 50 times or more, that is, Iref*R≤ (Vgs2)/50. Since Iref*R<<Vgs2, the source negative feedback effect of the resistance R on the second transistor Mn2 is negligible, the equivalent transconductance Gm≈gm2 of the combination of Mn2 and R, and the width-to-length ratio of the second transistor Mn2 is at least The aspect ratio of the first transistor Mn1 is 80 times. It can be seen that gm1<<gm2, therefore gm1<<Gm, so almost all of the reference current Iref flows into Mn2. And because Iref*R<<Vgs2, the voltage drop on the resistor R is much smaller than Vgs2, so the voltage at point A is Vgs2≈VA=Vgs4, if the ratio of the width to length ratio of the second transistor Mn2 to the width to length ratio of the fourth transistor Mn4 is 1:a (a is greater than or equal to 1), you can get I2:I4=1:a, and because the reference current Iref almost all flows into Mn2, so Iref≈I2, so Iref:I4≈1:a, the mirror image ratio I4 /Iref≈a:1. For example, generally when the width-to-length ratio of the second transistor Mn2 is equal to the width-to-length ratio of the fourth transistor Mn4 , that is, when a=1, I4/Iref≈1:1 can be obtained.

In section 2, Iref gradually increases after exceeding section 1 until Iref=(VB-Vgs3)/R. Taking section 1 as Iref*R≤Vgs2/50 as an example, section 2 can be expressed as Vgs2/R*50 <Iref≤(VB-Vgs3)/R, Vgs3 is the gate-source voltage of the third transistor Mn3. With the gradual increase of Iref in this interval section, the voltage drop on the resistance R continues to increase, and the negative feedback effect of the source electrode formed by R on Mn2 is gradually strengthened, then the equivalent transconductance Gm of Mn2 and R combined = gm2/( 1+gm2*R), that is, Gm<gm2. From the fact that the aspect ratio of the second transistor Mn2 is at least 80 times that of the first transistor Mn1, it can be seen that gm1<<gm2, although the equivalent transconductance Gm<gm2 of the combination of Mn2 and R, the value of Gm is still much larger than gm1 , so in this interval, Iref still maintains the state that almost all of it flows into Mn2. It can be seen from the circuit connection relationship that although Mn4 still forms a mirror image relationship with the combination of Mn2+R, the equivalent transconductance Gm is reduced compared with the previous one due to the negative feedback effect of the source of the resistor R (compared to the decrease in section 1), Therefore, the mirror image ratio between Mn4 and this combination is increased on the basis of the previous a:1, that is, the mirror image ratio I4/Iref>a:1. For example, generally when the aspect ratio of the second transistor Mn2 is equal to the aspect ratio of the fourth transistor Mn4, that is, when a=1, the mirror image ratio I4/Iref>1 can be obtained.

Interval segment 3, Iref>(VB-Vgs3)/R. When Iref>(VB-Vgs3)/R, the drain-source voltage Vds of Mn2 is almost 0, and Mn2 works in the linear region, then the current I2 flowing through Mn2 is as follows: I2=(VB-Vgs3)/R. As Iref continues to increase, the current flowing through Mn2 will also keep the value of the above formula unchanged. At this time, the sum of I2 and the current I1 flowing through Mn1 is equal to Iref, that is, I1=Iref-I1=Iref-(VB-Vgs3)/R, and because Mn2 works in the linear region at this time, the combination of Mn2 and R loses the pair current At this time, the current of Mn4 will mirror the current I1 flowing through Mn1. From the proportional relationship between the width and length ratio of Mn1 and Mn4, I4=a*N*I1=a*N*[Iref-(VB-Vgs3 )/R], and because [Iref-(VB-Vgs3)/R]<Iref, so I4<a*N*Iref, that is, I4/Iref<a*N. For example, generally when the width-to-length ratio of the second transistor Mn2 is equal to the width-to-length ratio of the fourth transistor Mn4, that is, when a=1, the mirror image ratio I4/Iref<N can be obtained.

Interval segment 4, Iref>>(VB-Vgs3)/R, where the much larger value may be at least 50 times larger. Now Iref almost all flows through Mn1, then I1=Iref, from the mirror image relationship between Mn1 and Mn4 (i.e. the ratio of the width to length ratio of Mn1 and Mn4), it can be seen that I4=a*N*I1=a*N*Iref, that is I4/Iref=a*N. For example, generally when the aspect ratio of the second transistor Mn2 is equal to the aspect ratio of the fourth transistor Mn4, that is, when a=1, the mirror image ratio I4/Iref=N can be obtained.

In summary, with the change of the reference current Iref, the current mirror structure realizes the change effect of the current mirror ratio from a to a*N, where a is the ratio of the width to length ratio of Mn4 and Mn2, and N is the ratio of Mn2 to Mn1 The ratio of width to length. From the above description of the working principle, it can be seen that compared with the existing current mirror circuit, the current mirror circuit of the present disclosure can adjust the mirror ratio in a large range without changing the circuit structure, and the operation is simpler and can also Save circuit area.

Further, in order to more intuitively represent the effect of changing the current mirror ratio with the change of the reference current Iref, Fig. 4 shows the curve of the ratio of the mirror current (output current I4) to the reference current Iref as the reference current Iref changes, Fig. 4 The curve in is a schematic diagram of the corresponding curve when a=1, N=100. It can be seen from Figure 4 that: in interval 1, the mirror image ratio is almost 1; in interval 2, the mirror image ratio begins to rise, but the speed of increase is not fast; , the mirror ratio barely rises to almost 100.

The embodiment of the present disclosure also provides a chip. The chip includes a current mirror circuit according to an embodiment of the present disclosure. The chip is, for example, a power management chip that needs to adjust the mirror image ratio.

The embodiment of the present disclosure also provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a smart mobile terminal, a smart home and other smart devices.

To sum up, the current mirror circuit in the embodiment of the present disclosure can obtain different mirror ratios according to the change of the reference current, and then can obtain variable output current based on the adjustable mirror ratio without changing the circuit structure.

The flowcharts and block diagrams in the figures show the architecture, functions and operations of possible implementations of devices and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

Unless the context clearly dictates otherwise, as used herein and in the appended claims, the singular includes the plural and vice versa. Thus, when referring to the singular, the plural of the corresponding term will generally be included. Similarly, the words "comprise" and "include" are to be interpreted as being inclusive and not exclusive. Likewise, the terms "include" and "or" should be construed as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, said "example" is exemplary and explanatory only, and should not be considered to be exclusive or inclusive .

Further aspects and ranges of adaptations will become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A current mirror circuit, characterized in that, comprises: a reference current generating circuit, an input stage transistor circuit, an output stage transistor circuit, and the input stage transistor circuit and the output stage transistor circuit form a cascode current mirror structure, Wherein, the reference current generating circuit is configured to generate a reference current; The input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current, thereby adjusting the mirror image ratio; The output stage transistor circuit is configured to output different output currents according to different mirror ratios. 2. The current mirror circuit according to claim 1, wherein the input stage transistor circuit comprises: a first transistor, a second transistor, a third transistor, a resistor, Wherein, the first pole of the first transistor is respectively coupled to the control pole of the first transistor, the first pole of the third transistor, and the output end of the reference current generating circuit, and the first pole of the first transistor The diode is coupled to the ground terminal; The first pole of the second transistor is coupled to the second pole of the third transistor, the second pole of the second transistor is coupled to one end of the resistor, and the control poles of the second transistor are respectively coupled to the The first pole of the third transistor, the input end of the output stage transistor circuit; The control electrode of the third transistor is coupled to a control voltage; The other end of the resistor is coupled to the ground. 3. The current mirror circuit according to claim 2, wherein the output stage transistor circuit comprises: a fourth transistor, Wherein, the first pole of the fourth transistor outputs the output current, the second pole of the fourth transistor is coupled to the ground terminal, and the control pole of the fourth transistor is used as the input terminal of the output stage transistor circuit to couple to connected to the input stage transistor circuit. 4. The current mirror circuit according to claim 1, wherein the reference current generating circuit comprises: a current source, Wherein, one end of the current source is connected to a power supply voltage, and the other end of the current source is coupled to the input-stage transistor circuit as an output end of the reference current generating circuit. 5. The current mirror circuit according to claim 2, wherein the control voltage is greater than or equal to the sum of the gate-source voltage of the third transistor and the overdrive voltage of the second transistor. 6. The current mirror circuit according to claim 2, wherein the aspect ratio of the second transistor is N times that of the first transistor, wherein N is greater than or equal to 80. 7. The current mirror circuit according to claim 3, wherein the width-to-length ratio of the second transistor is equal to the width-to-length ratio of the fourth transistor. 8. The current mirror circuit according to claim 3, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type transistors. 9. A chip, comprising the current mirror circuit according to any one of claims 1-8. 10. An electronic device, comprising the chip according to claim 9.

Images