CN116203406A - Scan register, operation method thereof, scan chain and chip - Google Patents

Abstract

A scan register and an operation method thereof, a scan chain and a chip are provided. The scan register includes an enable terminal, a data input terminal, a scan input terminal, a flip-flop unit, and an output control unit. The enabling end controls the scanning register to be in a working mode or a scanning mode according to the enabling signal; the data input end receives a first data signal in an operating mode; the scanning input end receives a first scanning signal in a scanning mode; the trigger unit comprises an input end, a first output end and a second output end which is in phase opposition with the first output end, and outputs a first output signal corresponding to a first data signal or a first output signal corresponding to a first scanning signal through the first output end in a working mode or a scanning mode; the output control unit is connected with the trigger unit and comprises a scanning output end, and is used for controlling the scanning output end to output a first output signal corresponding to the first data signal in a scanning mode and outputting a constant signal in a working mode. The scan register can reduce dynamic power consumption.

Description

Scan register and operation method thereof, scan chain, chip

technical field

Embodiments of the present disclosure relate to a scan register and an operation method thereof, a scan chain, and a chip.

Background technique

With the development of integrated circuit manufacturing technology, the size and quantity of electronic components integrated on the chip are getting smaller and smaller, and any defect on the chip may cause the circuit to malfunction. Therefore, before the chip leaves the factory, it is necessary to perform a scan test (scan test) on the testing machine to detect and ensure that the chip has no manufacturing defects.

Since the chip can be regarded as a collection of a large number of registers and combinational logic between registers, when scanning and testing the chip, it is necessary to convert these registers into scan registers that can be controlled and observed, that is, in ordinary registers Gates are added to form scan registers, and these scan registers are connected end-to-end to form one or more scan chains. The chip can be scanned and tested based on the scan chain.

Contents of the invention

At least one embodiment of the present disclosure provides a scan register, which includes: an enable terminal configured to control the scan register to be in a working mode or a scan mode according to an enable signal; a data input terminal configured to be in the working mode receiving the first data signal; the scanning input terminal is configured to receive the first scanning signal in the scanning mode; the trigger unit includes an input terminal for receiving the first data signal or the first scanning signal, The first output terminal and the second output terminal that is inverse phase to the first output terminal are configured to output a first output signal corresponding to the first data signal through the first output terminal in the working mode, Or in the scan mode, the first output terminal outputs the first output signal corresponding to the first scan signal; the output control unit is connected to the trigger unit and includes a scan output terminal, configured to control the The scanning output terminal outputs the first output signal corresponding to the first data signal in the scanning mode, and outputs a constant value signal in the working mode.

For example, in the scan register provided in at least one embodiment of the present disclosure, the output control unit includes a NOR gate, the NOR gate includes a first terminal, a second terminal and a third terminal, and the NOR gate's first terminal One end is connected to the second output end of the flip-flop unit to receive a second output signal that is inverse to the first output signal, and the second end of the NOR gate receives a second output signal that is inverse to the enable signal. phase inversion signal, the third terminal of the NOR gate is used as the scanning output terminal, and outputs the first output signal obtained by NOR operation of the second output signal and the inversion signal or The constant signal.

For example, in the scanning register provided in at least one embodiment of the present disclosure, the second terminal of the NOR gate receives the inverted signal through an inverter.

For example, in the scan register provided in at least one embodiment of the present disclosure, the output control unit includes a NAND gate, the NAND gate includes a first terminal, a second terminal and a third terminal, and the NAND gate One end is connected to the second output end of the flip-flop unit to receive a second output signal inverted from the first output signal, and the second end of the NAND gate is connected to the enable end to receiving the enabling signal, the third terminal of the NAND gate is used as the scanning output terminal, and outputs the first output signal obtained by performing a NAND operation on the second output signal and the enabling signal or the constant signal.

For example, in the scan register provided in at least one embodiment of the present disclosure, the flip-flop unit includes a flip-flop, and the flip-flop includes a D flip-flop, a T flip-flop, a JK flip-flop or an RS flip-flop.

For example, in the scan register provided by at least one embodiment of the present disclosure, the constant value signal is 1 or 0.

For example, at least one embodiment of the present disclosure further provides an operation method of a scan register, the operation method includes: controlling the scan register to be in the working mode or the scanning mode according to the enabling signal; in the working mode receiving the first data signal in the scanning mode; receiving the first scanning signal in the scanning mode; outputting the first data signal through the first output terminal of the flip-flop unit in the working mode Corresponding to the first output signal; in the scan mode, output the first output signal corresponding to the first scan signal through the first output terminal of the flip-flop unit; control the scan register The scanning output end outputs the first output signal corresponding to the first data signal in the scanning mode, and outputs the constant value signal in the working mode.

For example, at least one embodiment of the present disclosure further provides a scan chain including a plurality of cascaded scan registers according to at least one embodiment of the present disclosure.

For example, in the scan chain provided in at least one embodiment of the present disclosure, the scan output end of each scan register is connected to the scan input end of the next adjacent scan register in the cascade.

For example, at least one embodiment of the present disclosure further provides a chip, including the scan register according to any one of claims 1-6.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure .

Fig. 1 is a structural schematic diagram of a scanning register;

FIG. 2 is a schematic structural diagram of a scan chain;

FIG. 3 is a schematic block diagram of a scan register provided by at least one embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of an exemplary scan register provided by at least one embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of another exemplary scan register provided by at least one embodiment of the present disclosure; and

FIG. 6 is a schematic structural diagram of a scan chain provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort fall within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known parts (elements) may be omitted. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is represented by the same or similar reference numeral in each drawing.

There are a large number of logic circuits in a semiconductor integrated circuit (such as a chip). In order to detect the quality of the semiconductor integrated circuit, it is necessary to detect a large number of logic circuits to determine whether there is a fault inside the chip. Scan test (scantest) is a widely used test technology. Scan test can test the function and performance of each logic circuit in the chip by forming a scan chain (scan chain) with multiple scan registers connected to the logic circuit inside the chip. Very observable and controllable.

The scan register is a test device formed by adding a multiplexer on the basis of a flip-flop or a register. Replaced with a scan register capable of scanning. Compared with ordinary registers, the scan register has three additional ports: the enable terminal, the scan input terminal and the scan output terminal. Generally, the output terminals of the general registers are multiplexed as the scan output terminals of the scan registers.

Figure 1 shows a circuit structure of a scan register. For example, the scan register SDFF includes an input control unit 10 and a flip-flop unit 20 . For example, the input control unit 10 can be an alternative multiplexer, and the input control unit 10 has a data input terminal D, a scan input terminal SI and an enable terminal SE. The data input terminal D of the input control unit 10 is connected to the logic circuit, and can receive a data signal (such as the first data signal in this disclosure) from the logic circuit, so as to store the data signal in the scan register SDFF. The scan input terminal SI of the input control unit 10 can receive a test signal (such as the first scan signal in the present disclosure), thereby registering the test signal in the scan register SDFF, the test signal is obtained according to a test pattern (pattern), for example initialization value.

For example, the input control unit 10 can control the operation mode of the scan register SDFF according to the enable signal received by the enable terminal, and the operation mode of the scan register SDFF includes a work mode (mode) and a scan mode. For example, when the enable signal received by the enable terminal SE of the input control unit 10 is a low-level signal, the scan register SDFF is in the working mode, and the input control unit 10 conducts the data input terminal D to the flip-flop unit 20, by This data signal is registered in the flip-flop unit 20; when the enable signal received by the enable terminal SE of the input control unit 10 is a high level signal, the scan register SDFF is in scan mode, and the input control unit 10 will scan the input terminal SI is turned on to the flip-flop unit 20 , whereby the test signal is registered in the flip-flop unit 20 .

The input terminal of the flip-flop unit 20 is connected to the input control unit 10 through the node N1, thereby registering a data signal or a test signal in the flip-flop unit 20 according to the clock signal CK. The flip-flop unit 20 also includes an output terminal Q and an inverting output terminal QB, and the inverting output terminal QB is inverted with the output terminal Q through an inverter. The output end of the flip-flop unit 20 is connected to the logic circuit, so that when the scan register SDFF is in the working mode, the data signal registered in the flip-flop unit 20 can be output to the logic circuit according to the clock signal CK, so as to ensure the normal operation of the logic circuit. run. The output end of the flip-flop unit 20 is also multiplexed as a scan output end to connect with other scan registers, so that when the scan register SDFF is in the scan mode, the test signal registered in the flip-flop unit 20 can be shifted according to the clock signal CK. Exist in other scan registers; Or, the output terminal of flip-flop unit 20 can also output the test signal registered in the flip-flop unit 20 to the logic circuit according to the clock signal CK when the scan register SDFF is in the working mode, to test the logic Whether there is a fault in the circuit.

FIG. 2 shows a circuit structure diagram of an exemplary combinational logic circuit and a scan chain. As shown in Figure 2, a scan chain is formed by connecting multiple scan registers end to end. For example, the output terminals Q of the scan registers SDFF1, SDFF2, and SDFF3 are connected to the scan input terminal SI to connect the three scan registers in series to form a scan chain. Functionally, the scan chain can be divided into a working path and a scanning path. The working path is used to connect to the logic circuit when the chip is working normally, so as to ensure the normal working of the chip. The scan path is used to serially input multiple initialization values for multiple scan registers when testing the chip, and output scan test output results according to the test pattern input to the logic circuit, so as to detect the function and performance of the logic circuit.

For example, the output terminal C1 of the NAND gate 41 of the combinational logic circuit is connected to the data input terminal D of the scanning register SDFF1, and the output terminal Q of the scanning register SDFF1 is connected to the input terminal of the NAND gate 42 of the combinational logic circuit. The output terminal C2 of the NAND gate 42 is connected to the data input terminal D of the scanning register SDFF2, and the output terminal Q of the scanning register SDFF2 is connected to the input terminal of the NAND gate 44 of the combinational logic circuit, and the output of the NAND gate 44 of the combinational logic circuit The terminal C3 is connected to the data input terminal D of the scan register SDFF3, and the output terminal Q of the scan register SDFF3 is connected to the input terminal of the NOR gate 45 of the combinational logic circuit. This connection path is the working path of the scan chain.

For example, the scan input terminal SI of the scan register SDFF1 is used as the input terminal of the scan chain, the scan output terminal Q of the scan register SDFF1 is connected to the scan input terminal SI of the scan register SDFF2, and the scan output terminal Q of the scan register SDFF2 is connected to the scan register SDFF3. The scan input terminal SI and the scan output terminal Q of the scan register SDFF3 serve as the output terminal of the scan chain, and this connection path is the scan path of the scan chain.

The scan test includes two processes of scan shift and scan capture. During the scan shifting process, multiple initialization values of the test pattern can be serially input into multiple registers inside the chip through the scan path of the scan chain; during the scan capture process, the chip can be combined through the working path of the scan chain The result of the logic (test result) is passed into each register, and then the test result of the serial output is compared with the expected result (initialization value) to judge whether there is a defect inside the chip.

During the normal operation or scan test of the chip, dynamic power consumption (Dynamic Power) will be generated due to the transition of the transistor. Dynamic power consumption includes dynamic switching power consumption (Switching Power) and short circuit power consumption (Short Circuit Power). The formula of dynamic power consumption P is as follows:

P＝C _load *Vdd ² *f

Among them, C _load is the load capacitance, Vdd is the power supply voltage, and f is the flipping frequency.

It can be known from the formula of dynamic power consumption that the methods to reduce dynamic power consumption mainly include reducing the switching frequency, reducing the power supply voltage and reducing the load capacitance. However, the method of reducing the switching frequency will greatly affect the running speed of the chip, and the method of reducing the power supply voltage, such as setting multiple voltage domains or performing dynamic voltage scaling (Dynamic Voltage Scaling, DVS), is relatively complicated. Reducing the load capacitance is a simple and feasible method. The load capacitance includes wire capacitance, transistor capacitance, pin capacitance, etc. The interconnection wire capacitance can be reduced through good layout and wiring; Small logic stages and smaller transistor devices can reduce device transistor capacitance; reducing device fan-in and fan-out can reduce load capacitance.

The inventors of the present disclosure have found that in the scan chain, the scan input terminals of multiple scan registers are connected to the scan output terminal of the previous scan register, and since the scan output terminals multiplex the output terminal Q of the register, the actual operation of the logic circuit , as long as the state of the Q terminal of the scan register on the scan chain is reversed, the states of the components on the scan path will also be reversed, resulting in a large amount of dynamic power consumption, such as the power on the wire load. power consumption or charge and discharge power consumption of pin capacitance, etc. However, in the normal working process of the logic circuit, in fact, only the working path of the scan chain needs to be used, and the scan path does not need to be used, that is, the scan path only needs to be used when performing a scan test. Therefore, in the actual working process of the logic circuit, a large amount of dynamic power consumption generated on the scanning path is invalid power consumption, and measures can be taken to avoid or reduce this invalid dynamic power consumption.

At least one embodiment of the present disclosure provides a scan register. The scanning register includes an enabling terminal, a data input terminal, a scanning input terminal, a flip-flop unit and an output control unit. The enabling terminal is configured to control the scanning register to be in the working mode or scanning mode according to the enabling signal; the data input terminal is configured to receive the first data signal in the working mode; the scanning input terminal is configured to receive the first scanning signal in the scanning mode; trigger The device unit includes an input end for receiving a first data signal or a first scan signal, a first output end and a second output end inverted from the first output end, and is configured to output the first output end and The first output signal corresponding to the first data signal, or output the first output signal corresponding to the first scan signal through the first output terminal in the scan mode; the output control unit is connected to the trigger unit and includes a scan output terminal, configured to The scan output terminal is controlled to output a first output signal corresponding to the first data signal in scan mode, and to output a constant value signal in work mode.

At least one embodiment of the present disclosure further provides an operation method of the scan register. The operation method includes controlling the scanning register to be in the working mode or the scanning mode according to the enable signal; receiving the first data signal in the working mode; receiving the first scanning signal in the scanning mode; passing the first output of the flip-flop unit in the working mode The end outputs the first output signal corresponding to the first data signal; in the scanning mode, the first output signal corresponding to the first scanning signal is output through the first output end of the flip-flop unit; the scanning output end of the control scanning register is in the scanning mode outputting the first output signal corresponding to the first data signal, and outputting a constant value signal in the working mode.

At least one embodiment of the present disclosure further provides a scan chain and a chip including the above-mentioned scan register.

The scan register and its operation method, scan chain and chip provided by at least one embodiment of the present disclosure make the signal output by the scan output terminal of the scan register in the working mode be a constant value signal through the output control unit, so that the scan path of the scan chain is working The static state of not flipping in the mode can reduce the dynamic power consumption of the scan path of the scan chain in the working mode and alleviate the problem of voltage drop. Moreover, the structure of the output control unit is simple, which can provide more wiring layout for the chip. The space is beneficial to reduce the area of the chip and save the design cost. In at least one embodiment, the number of buffers on the scan path of the scan chain can be reduced to reduce hold time violations.

Fig. 3 shows a schematic block diagram of a scanning register provided by at least one embodiment of the present disclosure. As shown in FIG. 3 , the scan register 100 includes a data input terminal D, a scan input terminal SI, an enable terminal SE, a flip-flop unit 20 and an output control unit 30 .

For example, the enable terminal SE is configured to control the scan register to be in the working mode or the scan mode according to the enable signal. For example, when the enable signal received by the enable terminal SE is a low-level signal, the scan register 100 is in the working mode, and when the enable signal received by the enable terminal SE is a high-level signal, the scan register 100 is in the scan mode.

For example, the scan register 100 further includes an input control unit 10 configured to control the scan register to receive the first data signal or the first scan signal. For example, the input control unit 10 may be a two-to-one multiplexer, or may be a control switch composed of tri-state gates as shown in FIG. 4 , which is not limited in the embodiments of the present disclosure.

For example, one input end of the input control unit 10 is the data input end D of the scan register 100, configured to receive the first data signal in the working mode, and the other input end of the input control unit 10 is the scan input end S1 of the scan register 100. , configured to receive a first scan signal in scan mode. For example, the output terminal of the input control unit 10 is connected to the input terminal D1 of the flip-flop unit 20 . For example, when the enable signal received by the enable terminal SE is a low-level signal, the input control unit 10 registers the first data signal received by the data input terminal D in the flip-flop unit 20, and when the enable signal received by the enable terminal SE When the enable signal is a high-level signal, the input control unit 10 registers the first scan signal received by the scan input terminal SI in the flip-flop unit 20 .

For example, the flip-flop unit 20 includes an input terminal D1, a first output terminal Q, and a second output terminal QB that is inverted from the first output terminal. The input terminal D1 of the flip-flop unit 20 is used to receive the first data signal or the first scan signal. For example, the input terminal D1 of the flip-flop unit 20 can receive the first data signal when the scan register 100 works normally, or can receive the first scan signal (for example, an initialization value) during the scan shift of the scan register 100, or can A first data signal is received as a test result during scan capture of the scan register 100 .

For example, the flip-flop unit 20 is configured to output the first output signal corresponding to the first data signal through the first output terminal Q in the working mode, or output the first output signal corresponding to the first scan signal through the first output terminal Q in the scanning mode. first output signal.

For example, when the scan register 100 is working normally, the first output terminal Q of the flip-flop unit 20 outputs the first output signal corresponding to the first data signal to the logic circuit, so as to realize the combinatorial logic function. At this time, the scan register is used as a common shift register. For example, if the first data signal is 0, the first output signal corresponding to the first data signal is also 0.

For example, when the scan register 100 is used for scan testing, the first output terminal Q of the flip-flop unit 20 outputs the first scan signal (for example, an initialization value) pre-registered in the flip-flop unit 20 to the logic circuit, thereby ensuring The input value input to each test cell of the logic circuit during testing is equal to the initialization value.

For example, the trigger unit 20 may include a trigger, for example, the trigger may be a D flip-flop, a T flip-flop, a JK flip-flop, or an RS flip-flop. The specific circuit structure of the device unit is not limited.

For example, the output control unit 30 is connected to the flip-flop unit 20 and includes a scanning output terminal SO, configured to control the scanning output terminal SO to output a first output signal corresponding to the first data signal in the scanning mode, and output a constant output signal in the working mode. value signal.

For example, when the scan register 100 is used for scan test, the scan output terminal SO of the output control unit 30 outputs the first output signal corresponding to the first data signal as the test result, so as to compare the first output signal with the initialization value. Comparison, if the two match, it means that the logic of the test unit connected to the scan register 100 in the logic circuit is correct; if the two do not match, it means that the test unit is faulty.

For example, when the scan register 100 is working normally, the scan output terminal SO of the output control unit 30 outputs a constant value signal, for example, the constant value signal is 1 or 0. Here, the constant value signal means that when the scan register 100 is in normal operation, the signal output by the scan output terminal SO remains static, that is, the state of the scan output terminal SO remains static, and the scan output terminal SO will not change with the flipping of the scan register. The inversion occurs, so that the elements on the scanning path connected to the scanning output terminal SO will not invert, thereby reducing the dynamic power consumption of the scanning register in normal operation and alleviating the problem of voltage drop.

For example, in at least one embodiment of the present disclosure, the output control unit 30 is directly connected to the first output terminal of the flip-flop unit 20 or connected to the first output terminal through an inverter. For example, the output control unit 30 is directly connected to the first output terminal of the flip-flop unit 20 to receive the first output signal, or the output control unit 30 is connected to the first output terminal of the flip-flop unit 20 through an inverter to receive the first output signal corresponding to the first output signal. An output signal inverting the second output signal, for example, the output control unit 30 is directly connected to the second output terminal of the flip-flop unit 20 to receive the second output signal.

For example, in an embodiment of the present disclosure, as shown in FIG. 4 , the output control unit 30 includes a NOR gate. The NOR gate includes a first terminal 1, a second terminal 2 and a third terminal 3, and the first terminal 1 of the NOR gate is connected to the second output terminal QB of the flip-flop unit 20 to receive the first output signal inverted from the first output signal. Two output signals, the second terminal 2 of the NOR gate receives the inversion signal SEB which is inverse to the enable signal, and the third terminal 3 of the NOR gate is used as the scanning output terminal SO, and the output is performed by the second output signal and the inversion signal OR the first output signal or the constant value signal obtained by the negation operation.

For example, when the scan register is working normally, the enable signal is a low-level signal 0, and the inverted signal SEB, which is inverse to the enable signal, is a high-level signal 1.

If the first output signal is a high-level signal 1, the second output signal is a low-level signal 0, that is, the first terminal 1 of the NOR gate receives a low-level signal 0, and the second terminal 2 of the NOR gate After receiving the high-level signal 1, after the NOR operation, the third terminal 3 of the NOR gate is used as the scanning output terminal SO to output the low-level signal 0.

If the first output signal is a low-level signal 0, the second output signal is a high-level signal 1, that is, the first terminal 1 of the NOR gate receives a high-level signal 1, and the second terminal 2 of the NOR gate After receiving the high-level signal 1, after the NOR operation, the third terminal 3 of the NOR gate is used as the scanning output terminal SO to output the low-level signal 0.

That is to say, when the scan register is working normally, the scan output terminal SO always outputs a constant value signal (low level signal 0), and the scan output terminal SO does not reverse with the inversion of the first output terminal Q, thereby reducing dynamic power consumption .

For example, when the scan register performs scan shifting, the enable signal is a high-level signal 1, and the inverted signal SEB, which is inverse to the enable signal, is a low-level signal 0.

If the first output signal is a high-level signal 1, the second output signal is a low-level signal 0, that is, the first terminal 1 of the NOR gate receives a low-level signal 0, and the second terminal 2 of the NOR gate After receiving the low-level signal 0, after the NOR operation, the third terminal 3 of the NOR gate is used as the scanning output terminal SO to output the high-level signal 1, which is consistent with the first output signal.

If the first output signal is a low-level signal 0, the second output signal is a high-level signal 1, that is, the first terminal 1 of the NOR gate receives a high-level signal 1, and the second terminal 2 of the NOR gate After receiving the low-level signal 0, after the NOR operation, the third terminal 3 of the NOR gate is used as the scan output terminal SO to output the low-level signal 0, which is consistent with the first output signal.

That is to say, the scan output terminal SO outputs the first output signal during the scan shift, thus ensuring the normal scan test process of the scan register.

For example, in this embodiment, the second terminal 2 of the NOR gate is connected to the first output terminal Q through an inverter, so as to receive an inverted signal that is inverted from the first output signal.

For example, in another embodiment of the present disclosure, as shown in FIG. 5 , the output control unit 30 includes a NAND gate. The NAND gate includes a first terminal 4, a second terminal 5 and a third terminal 6, and the first terminal 4 of the NAND gate is connected to the second output terminal QB of the flip-flop unit 20 to receive the first output signal inverted from the first output signal. Two output signals, the second end 5 of the NAND gate is connected to the enable terminal SE to receive the enable signal, the third end 6 of the NAND gate is used as the scanning output end SO, and the output is ANDed by the second output signal and the enable signal The first output signal or constant value signal obtained by the negation operation.

For example, when the scan register is working normally, the enable signal is a low-level signal 0, and the second terminal 5 of the NAND gate receives a low-level signal 0.

If the first output signal is a high-level signal 1, the second output signal is a low-level signal 0, that is, the first terminal 4 of the NAND gate receives a low-level signal 0, and the second terminal 5 of the NAND gate receives The low level signal is 0, and after the NAND operation, the third terminal 6 of the NAND gate is used as the scanning output terminal SO to output the high level signal 1.

If the first output signal is a low-level signal 0, the second output signal is a high-level signal 1, that is, the first terminal 4 of the NAND gate receives a high-level signal 1, and the second terminal 5 of the NAND gate After receiving the low-level signal 0, after the NAND operation, the third terminal 6 of the NAND gate is used as the scanning output terminal SO to output the high-level signal 1.

That is to say, when the scan register is working normally, the scan output terminal SO always outputs a constant value signal (high level signal 1), and the scan output terminal SO does not reverse with the inversion of the first output terminal Q, thereby reducing dynamic power consumption .

For example, when the scan register performs a scan shift, the enable signal is a high-level signal 1.

If the first output signal is a high-level signal 1, the second output signal is a low-level signal 0, that is, the first terminal 4 of the NAND gate receives a low-level signal 0, and the second terminal 5 of the NAND gate After receiving the high-level signal 1, after the NAND operation, the third terminal 6 of the NAND gate serves as the scanning output terminal SO to output the high-level signal 1, which is consistent with the first output signal.

If the first output signal is a low-level signal 0, the second output signal is a high-level signal 1, that is, the first terminal 4 of the NAND gate receives a high-level signal 1, and the second terminal 5 of the NAND gate After receiving the high-level signal 1, after the NAND operation, the third terminal 6 of the NAND gate is used as the scanning output terminal SO to output a low-level signal 0, which is consistent with the first output signal.

That is to say, the scan output terminal SO outputs the first output signal during the scan shift, thus ensuring the normal scan test process of the scan register.

For example, in at least one embodiment of the present disclosure, the output control unit 30 may also be an AND gate, for example, the first terminal of the AND gate is directly connected to the first output terminal of the flip-flop unit 20 to receive the first output signal, and the AND gate The second terminal of the AND gate receives the inversion signal SEB which is inverse to the enable signal, and the third terminal of the AND gate is used as the scanning output terminal SO to output the first output signal obtained by ORing the first output signal and the inversion signal or constant signal.

For example, in at least one embodiment of the present disclosure, the output control unit 30 may also be an OR gate, for example, the first end of the OR gate is directly connected to the first output end of the flip-flop unit 20 to receive the first output signal, or the OR gate The second terminal of the AND gate receives the enable signal, and the third terminal of the AND gate is used as the scan output terminal SO to output the first output signal or a constant value signal obtained by performing an NOR operation on the first output signal and the inverted signal.

The output control unit of the scan register provided by at least one embodiment of the present disclosure has a simple structure, which can provide more space for the wiring layout of the chip, which is beneficial to reducing the area of the chip and saving design costs.

At least one embodiment of the present disclosure further provides a scan chain, the scan chain includes the scan register provided in any one of the above embodiments, and a plurality of scan registers are connected in cascade to form the scan chain.

As shown in FIG. 6 , the scan chain 200 includes a plurality of cascaded scan registers 100, the scan output end SO of each scan register is connected to the scan input end SI of the next adjacent scan register in the cascade, and each scan register The first output terminal Q of is connected to a logic circuit (not shown in the figure).

For example, in at least one example of the embodiments of the present disclosure, the output control unit includes a NOR gate, and the NOR gate includes a first terminal, a second terminal and a third terminal, and the first terminal of the NOR gate and the first terminal of the flip-flop unit The two output terminals are connected to receive a second output signal that is inverse to the first output signal, the second terminal of the NOR gate receives an inversion signal that is inverse to the enable signal, and the third terminal of the NOR gate is used as a scanning output terminal, and outputting the first output signal or a constant value signal obtained by performing an NOR operation on the second output signal and the inverted signal.

For example, in at least one example of the embodiments of the present disclosure, the output control unit includes a NAND gate, and the NAND gate includes a first terminal, a second terminal and a third terminal, and the first terminal of the NAND gate and the second terminal of the flip-flop unit The two output terminals are connected to receive the second output signal which is inverted from the first output signal, the second terminal of the NAND gate is connected to the enabling terminal to receive the enabling signal, the third terminal of the NAND gate is used as a scanning output terminal, and the output The first output signal or a constant value signal obtained by performing a NAND operation on the second output signal and the enable signal.

For example, in at least one example of the disclosed embodiments, the constant value signal is 1 or 0.

For the specific structure and functions of the scan register 100 , reference may be made to the relevant description above, which will not be repeated here.

For example, the path from the scan input terminal SI to the scan output terminal SO in the scan chain 200 is a scan path. During the normal operation of the scan register, the scan chain 200 can keep the scan path in a static state without flipping, thereby reducing the number of scan chains. The dynamic power consumption of the scan path in the working mode alleviates the problem of voltage drop. The fan-out of the first output terminal Q of the scan register reduces the load capacitance of the overall circuit design because the related line load and pin capacitance are reduced, that is, according to the formula P=C _load *Vdd ² *f, The purpose of reducing the dynamic power consumption P is achieved by reducing the C _load .

Due to the margin and clock offset added by various errors caused by the process (Process), voltage (Voltage), and temperature (Temperature) on the chip, hold timing violations often occur on the scan path. Condition. In order to ensure the normal operation of the circuit, a buffer or delay is usually added between two adjacent scan registers of the scan chain to ensure the hold time, as shown in FIG. 2 . In the scan chain provided by at least one embodiment of the present disclosure, the timing speed can be reduced by increasing the threshold voltage of the output control unit of the scan register, for example, the NOR gate in FIG. 4 or the NAND gate in FIG. 5 can be The threshold voltage is adjusted higher to make the timing slower, so that the hold time requirements can be better guaranteed, and the hold time violations can be reduced. In addition, the number of buffers or delay units on the scanning path can be reduced, and the load of the transistor circuit can be reduced, thereby reducing dynamic power consumption.

At least one embodiment of the present disclosure further provides a chip, which includes the scan register provided by any one of the above embodiments. For example, the chip includes a central processing unit (Central Processing Unit, CPU) or a CPU core, a coprocessor (such as a GPU, a DMA processor, etc.), a peripheral controller (such as a storage controller), and the like. Embodiments of the present disclosure are directed to This is not limited.

The chip can achieve technical effects similar to those of the scan register described above, which will not be repeated here.

At least one embodiment of the present disclosure also provides a scanning register operation method, the operating method includes: controlling the scanning register to be in the working mode or scanning mode according to the enable signal; receiving the first data signal in the working mode; receiving the first data signal in the scanning mode The first scanning signal; in the working mode, the first output signal corresponding to the first data signal is output through the first output end of the flip-flop unit; in the scanning mode, the first output end of the flip-flop unit outputs the first scanning signal Corresponding first output signal: controlling the scan output terminal of the scan register to output the first output signal corresponding to the first data signal in the scan mode, and to output a constant value signal in the work mode.

This operation method can achieve a technical effect similar to that of the scanning register described above, which will not be repeated here.

Although the present disclosure has been described in detail with general descriptions and specific implementations above, it is obvious to those skilled in the art that some modifications or improvements can be made on the basis of the embodiments of the present disclosure. Therefore, the modifications or improvements made on the basis of not departing from the spirit of the present disclosure all belong to the protection scope of the present disclosure.

For this disclosure, the following points need to be explained:

(1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

(2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thicknesses of layers or regions are exaggerated or reduced, that is, the drawings are not drawn in actual scale.

(3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above is only a specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (10)

1. A scan register, comprising: The enable terminal is configured to control the scan register to be in the working mode or the scan mode according to the enable signal; a data input terminal configured to receive a first data signal in the working mode; a scan input configured to receive a first scan signal in the scan mode; a flip-flop unit, comprising an input terminal for receiving the first data signal or the first scanning signal, a first output terminal, and a second output terminal inverting the first output terminal, configured to Outputting the first output signal corresponding to the first data signal through the first output terminal in the working mode, or outputting the first output signal corresponding to the first scanning signal through the first output terminal in the scanning mode an output signal; an output control unit, connected to the flip-flop unit and including a scan output terminal, configured to control the scan output terminal to output the first output signal corresponding to the first data signal in the scan mode, in the In the above working mode, it outputs a constant value signal. 2. The scan register according to claim 1, wherein the output control unit comprises a NOR gate, The NOR gate includes a first terminal, a second terminal and a third terminal, the first terminal of the NOR gate is connected to the second output terminal of the flip-flop unit to receive the first output signal Inverted second output signal, the second terminal of the NOR gate receives the inverted signal that is inverse to the enable signal, the third terminal of the NOR gate is used as the scanning output terminal, and the output is determined by the The first output signal or the constant value signal obtained by performing or negating the second output signal and the inverted signal. 3. The scan register according to claim 2, wherein the second terminal of the NOR gate receives the inverted signal through an inverter. 4. The scan register according to claim 1, wherein the output control unit comprises a NAND gate, The NAND gate includes a first terminal, a second terminal and a third terminal, the first terminal of the NAND gate is connected to the second output terminal of the flip-flop unit to receive the first output signal Inverted second output signal, the second terminal of the NAND gate is connected to the enable terminal to receive the enable signal, the third terminal of the NAND gate is used as the scanning output terminal, and the output is determined by The first output signal or the constant value signal is obtained by performing a NAND operation on the second output signal and the enable signal. 5. The scan register according to any one of claims 1-4, wherein the flip-flop unit includes a flip-flop, and the flip-flop includes a D flip-flop, a T flip-flop, a JK flip-flop or an RS flip-flop. 6. The scan register according to any one of claims 1-4, wherein the constant value signal is 1 or 0. 7. A method of operating the scan register as claimed in claim 1, comprising: controlling the scan register to be in the working mode or the scan mode according to the enable signal; receiving the first data signal in the operating mode; receiving the first scan signal in the scan mode; outputting the first output signal corresponding to the first data signal through the first output terminal of the flip-flop unit in the working mode; outputting the first output signal corresponding to the first scan signal through the first output terminal of the flip-flop unit in the scan mode; The scan output end of the scan register is controlled to output the first output signal corresponding to the first data signal in the scan mode, and to output the constant value signal in the work mode. 8. A scan chain, comprising a plurality of cascaded scan registers according to any one of claims 1-6. 9. The scan chain according to claim 8, wherein the scan output of each scan register is connected to the scan input of the next adjacent scan register in the cascade. 10. A chip, comprising the scan register according to any one of claims 1-6.

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