CN116193854B

CN116193854B - Dynamic random access memory and forming method thereof

Info

Publication number: CN116193854B
Application number: CN202310210598.6A
Authority: CN
Inventors: 张帜; 华文宇
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2023-02-28
Filing date: 2023-02-28
Publication date: 2025-09-26
Anticipated expiration: 2043-02-28
Also published as: CN116193854A

Abstract

A dynamic random access memory and a forming method thereof are provided, wherein the structure comprises a plurality of first grooves and a plurality of second grooves which are positioned in a substrate, the first grooves and the second grooves penetrate through an active area and a first isolation structure along a second direction and extend from a first surface to a second surface, the first grooves penetrate through a channel area, the second grooves penetrate through a word line area, a shielding layer positioned in the first grooves is provided with a first size in a direction perpendicular to the surface of the substrate, the shielding layer in the active area is provided with a second size smaller than the first size, the word line grating structure positioned on the side wall of the second grooves comprises two word line layers positioned on the side wall of each second groove and a second isolation structure positioned between the two word line layers, and the second isolation structure isolates the two word line layers from each other. The parasitic capacitance between adjacent word line layers in the first isolation structure is reduced, and the word line impact effect is reduced.

Description

Dynamic random access memory and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a dynamic random access memory and a method for forming the same.

Background

With rapid development of technology nowadays, semiconductor memories are widely used in electronic devices. Dynamic random access memory (dynamic random access memory, DRAM) is one of the volatile memories, which is the most commonly utilized solution for applications storing large amounts of data.

The basic memory cell of the dynamic random access memory is composed of one memory transistor and one memory capacitor, and the memory array is composed of a plurality of memory cells. The storage capacitor is used for storing charge representing stored information, the storage transistor is a switch for controlling charge inflow and discharge of the storage capacitor, and the storage transistor is also connected with an internal circuit in storage and receives a control signal of the internal circuit. Wherein an active region, a drain region, and a gate electrode are formed in the memory transistor, the gate electrode is used for controlling current flow between the source region and the drain region, and is connected to the word line, the drain region is used for forming a bit line contact region, and is connected to the bit line source region for forming a storage node contact region, so as to be connected to the storage capacitor. With the continued development of integrated circuit fabrication technology, further increases in device density of memory chips are needed to obtain greater amounts of data storage.

However, there are still a number of problems with existing dynamic random access memories.

Disclosure of Invention

The invention solves the technical problem of providing a dynamic random access memory and a forming method thereof, which can improve the stability of the performance of a device.

In order to solve the problems, the invention provides a dynamic random access memory, which comprises a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and a first isolation structure which are arranged along a first direction, the first isolation structure is positioned between the adjacent active areas, the plurality of active areas are parallel to a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of mutually separated channel areas which are arranged along the second direction, word line areas which are positioned between the adjacent channel areas, the word line areas positioned in different active areas are arranged along the first direction, a plurality of first grooves and a plurality of second grooves which are positioned in the substrate and penetrate through the active areas and the first isolation structure along the second direction, the first grooves penetrate through the channel areas, the second grooves penetrate through the word line areas, the first grooves are positioned in the first grooves, the second grooves are positioned in the first side wall of the second isolation structure, the first grooves are positioned in the first side wall of the second isolation structure, the second grooves are positioned in the second side wall of the second isolation structure, the dimension of the first groove is larger than the first groove, the second groove is positioned in the first groove is positioned in the second groove, the dimension of the second groove is positioned between the two isolation structures, and the first groove is positioned in the second groove is positioned in the first side wall, and the side wall is positioned between the two isolation structures, and the first groove is positioned in the second groove is positioned in the dimension between the first groove, and the isolation structures, and has the first isolation structures, and the structures are in the two structures.

Optionally, the first surface and the second surface each expose the first isolation structure.

Optionally, the first surface exposes the first isolation structure, the structure further comprises a third groove located between adjacent active areas, the third groove extends from the second surface to the first surface, the bottom of the third groove exposes the first isolation structure and the shielding layer, and the first dielectric layer is located in the third groove.

Optionally, the surface of the shielding layer in the first isolation structure has a first distance from the second surface, the surface of the shielding layer in the active region has a second distance from the second surface, the first distance is greater than the second distance, or the surface of the shielding layer in the first isolation structure has a third distance from the first surface, the surface of the shielding layer in the active region has a fourth distance from the first surface, the third distance is greater than the fourth distance, or the first distance is greater than the second distance, and the third distance is greater than the fourth distance.

The semiconductor device comprises a shielding layer, a first insulating layer, a second insulating layer and a second insulating layer, wherein the first insulating layer is positioned between the shielding layer and the side wall and the bottom of the first groove, the second insulating layer is positioned on the surface of the shielding layer, the material of the first insulating layer comprises a dielectric material, the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride, the material of the second insulating layer comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride and silicon oxycarbonitride.

Optionally, the word line gate structure further comprises a third insulating layer located between the two word line layers and the bottoms of the second isolation structures and the bottoms of the second trenches, the top surface of the word line layer is lower than the first surface, and the word line gate structure further comprises a fourth insulating layer located on the top surface of the word line layer.

Optionally, a shield extraction layer on the first face, the shield extraction layer being electrically interconnected with the shield layer.

Optionally, a shield extraction layer on the second side, the shield extraction layer being electrically interconnected with the shield layer.

Optionally, the material of the shielding layer comprises a conductor material, and the conductor material comprises metal.

Optionally, the semiconductor device further comprises a plurality of first source-drain doped regions positioned in the first face of each active region, and a plurality of capacitor structures positioned on the first face, wherein each capacitor structure is electrically connected with one first source-drain doped region.

The semiconductor device comprises an active area, a first source-drain doped area, a second source-drain doped area, a plurality of bit lines, a metal interconnection layer, a logic wafer and a logic wafer, wherein the second source-drain doped area is positioned in a second face of each active area, the bit lines are positioned on the second face and are parallel to the first direction, each bit line is electrically connected with the second source-drain doped area in one active area, the metal interconnection layer is positioned on the second face and is electrically interconnected with the plurality of bit lines, and the logic wafer is bonded with the substrate from the surface of the metal interconnection layer, and a plurality of logic devices are arranged in the logic wafer.

Correspondingly, the invention provides another method for forming the dynamic random access memory, which comprises the steps of providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas which are arranged along a first direction and an initial first isolation structure, the first surface is exposed out of the surface of the initial first isolation structure, the initial first isolation structure is positioned between adjacent active areas, the plurality of active areas are parallel to a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of channel areas which are mutually separated and are arranged along the second direction, and word line areas which are positioned between the adjacent channel areas, and the word line areas positioned in different active areas are arranged along the first direction; forming a plurality of first trenches and a plurality of second trenches in the substrate, wherein the first trenches and the second trenches penetrate through the active area and the initial first isolation structure along a second direction, extend from the first surface to the second surface, penetrate through the channel area, penetrate through the word line area, form initial shielding layers in the first trenches, form word line grid structures in the second trenches, the word line grid structures comprise two word line layers positioned on the side wall of each second trench and a second isolation structure positioned between the two word line layers, the second isolation structure isolates the two word line layers from each other, after the word line structures and the initial shielding layers are formed, the substrate is thinned from the direction of the second surface to expose the initial first isolation structure, after the thinning, the initial first isolation structure and the initial shielding layer are etched from the second surface, the size of the initial shielding layer in the initial first isolation structure in the direction perpendicular to the surface of the substrate is reduced, the shielding layer is formed by the initial shielding layer, and the first isolation structure is formed by the initial first isolation structure.

Optionally, the method for forming the shielding layer further comprises the steps of performing first etching treatment on the initial first isolation structure until the initial shielding layer in the initial first isolation structure is exposed, and performing second etching treatment on the exposed initial shielding layer.

Optionally, the first etching treatment process comprises one or both of a dry etching process and a wet etching process, and the second etching treatment process comprises one or both of a dry etching process and a wet etching process.

Optionally, after the shielding layer is formed, a second source-drain doped region is formed in a second face of each active region, and a plurality of bit lines parallel to the first direction are formed on the second face, wherein each bit line is electrically connected with the second source-drain doped region in one active region.

Optionally, the method further comprises the steps of etching the initial first isolation structure and the initial shielding layer, forming a third groove in the substrate, and forming a first dielectric layer in the third groove.

Optionally, the method further comprises forming a first insulating layer on the first trench sidewall and bottom prior to forming the initial shield layer.

Optionally, the first insulating layer and the initial shielding layer are formed by forming a first insulating material layer and a shielding material layer positioned on the surface of the first insulating material layer in the first groove and on the surface of the first face, and flattening the first insulating material layer and the shielding material layer until the first face surface is exposed, forming the first insulating layer by the first insulating material layer, and forming the initial shielding layer by the shielding material layer.

Optionally, the top surface of the initial shielding layer is lower than the first face, the forming method of the initial shielding layer further comprises back etching the shielding material layer after the flattening process, and after the initial shielding layer is formed, a second insulating layer is formed on the surface of the initial shielding layer in the first groove.

Optionally, the method further comprises forming a metal interconnection layer on the second face after the bit lines are formed, wherein the metal interconnection layer is electrically interconnected with the bit lines, providing a logic wafer, wherein the logic wafer is provided with a plurality of logic device layers, and bonding the substrate and the logic wafer to each other by enabling the second face to face the surface of the logic device layers after the metal interconnection layer is formed.

Optionally, the initial shielding layer surface in the initial first isolation structure has a third distance from the first face, and the initial shielding layer surface in the active region has a fourth distance from the first face, the third distance being greater than the fourth distance; the method for forming the initial shielding layer comprises the steps of forming a shielding material layer in the first groove, enabling the first surface to expose the surface of the shielding material layer, forming a mask layer on the first surface, enabling the mask layer to expose the surface of the shielding material layer in the initial first isolation structure, and etching the shielding material layer from the first surface by taking the mask layer as a mask, so that the size of the initial shielding layer in the initial first isolation structure in the direction perpendicular to the surface of the substrate is reduced, and the initial shielding layer is formed.

Optionally, the forming method of the word line grating structure comprises the steps of forming a third insulating layer in the second groove, forming an initial word line layer in the second groove after the third insulating layer is formed, enabling the top surface of the initial word line layer to be flush with the first surface, etching part of the initial word line layer from the direction of the first surface to the direction of the second surface, forming a plurality of fourth grooves parallel to the second direction in the substrate, enabling the fourth grooves to penetrate through the initial word line layer from the direction of the first surface to the direction of the second surface to form the two transition word line layers, forming the second isolation structure in the fourth grooves, back etching the transition word line layer to form the word line layer, and forming the fourth insulating layer in the second groove after the word line layer is formed.

Optionally, after the word line gate structure and the initial shielding layer are formed and before the thinning treatment, a plurality of first source-drain doped regions are formed in a first face of each active region, and after the plurality of first source-drain doped regions are formed, a plurality of capacitor structures are formed on the first face, wherein each capacitor structure is electrically connected with one first source-drain doped region.

Optionally, after forming the shielding layer, forming a shielding extraction layer, wherein the shielding extraction layer is electrically interconnected with the shielding layer.

Optionally, after forming the initial shield layer and before the thinning, further comprising forming a shield extraction layer on the first face, the shield extraction layer being electrically interconnected with the initial shield layer.

Optionally, the initial shielding layer is formed first, then the word line grating structure is formed, the first grooves, the second grooves, the initial shielding layer and the word line grating structure are formed, the method comprises the steps of forming a plurality of initial grooves in the substrate, wherein the initial grooves penetrating through the channel region are the first grooves, the initial grooves penetrating through the word line region are the initial second grooves, a protective layer is formed in the initial second grooves, the initial shielding layer is formed in the first grooves after the protective layer is formed, the protective layer is removed after the initial shielding layer is formed, the initial second grooves are exposed, the initial second grooves are etched to increase the size of the initial second grooves, the second grooves are formed, and the word line grating structure is formed in the second grooves.

Optionally, the initial shielding layer surface has a fifth distance from the second face, and the word line layer has a sixth distance from the second face, and the fifth distance is smaller than the sixth distance.

Correspondingly, the invention provides another method for forming the dynamic random access memory, which comprises the steps of providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and a first isolation structure which are arranged along a first direction, the first surface exposes the surface of the first isolation structure, the first isolation structure is positioned between adjacent active areas, the plurality of active areas are parallel to a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of channel areas which are mutually separated and are arranged along the second direction, and word line areas which are positioned between the adjacent channel areas, and the word line areas positioned in different active areas are arranged along the first direction; forming a plurality of first trenches and a plurality of second trenches in the substrate, each of the first trenches and the second trenches penetrating the active region and the first isolation structure in a second direction and extending from the first surface toward the second surface, the first trenches penetrating the channel region and the second trenches penetrating the word line region, forming a shielding layer in the first trenches, the surface of the shielding layer in the first isolation structure having a third distance from the first surface, the surface of the shielding layer in the active region having a fourth distance from the first surface, the third distance being greater than the fourth distance, forming a word line gate structure in the second trenches, the word line gate structure including two gate layers on sidewalls of the second trenches and a second isolation structure between the two word line layers, the second isolation structure isolating the two word line layers from each other, and thinning the substrate from the second surface to the first surface until the first isolation structure is exposed.

Optionally, the method for forming the shielding layer comprises the steps of forming an initial shielding layer in the first groove, wherein the first face is exposed out of the initial shielding layer, forming a mask layer on the first face, wherein the mask layer is exposed out of the surface of the initial shielding layer in the first isolation structure, and etching the initial shielding layer by taking the mask layer as a mask to form the shielding layer.

Optionally, after forming the shielding layer and before the thinning, further comprising forming a shielding exit layer on the first face, the shielding exit layer being electrically interconnected with the shielding layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

In the dynamic random access memory provided by the technical scheme of the invention, the shielding layer in the first groove has a first size in the direction vertical to the surface of the substrate, the shielding layer in the first isolation structure has a second size, the second size is larger than the first size, and the shielding layer is designed to reduce parasitic capacitance between adjacent word line layers in the first isolation structure and also play a shielding role, so that the coupling effect between the word line layers at two sides of the channel region is reduced, thereby reducing the word line impact effect and improving the device performance on the whole.

In the method for forming the dynamic random access memory provided by the technical scheme of the invention, after the thinning treatment is carried out, the initial first isolation structure and the initial shielding layer are etched from the second surface to form the shielding layer, so that the size of the initial shielding layer in the initial first isolation structure in the direction vertical to the surface of the substrate is reduced, the size of the shielding layer in the first isolation structure is smaller than that of the shielding layer in the active region, and the shielding layer is designed to reduce parasitic capacitance between adjacent word line layers in the first isolation structure, simultaneously play a shielding role, reduce the coupling role between the word line layers at two sides of the channel region, further reduce the word line impact effect and improve the device performance on the whole.

Further, the initial shielding layer in the initial first isolation structure is at a third distance from the first surface, the initial shielding layer in the active region is at a fourth distance from the first surface, and the third distance is smaller than the fourth distance, so that in the finally formed dynamic random access memory, the size of the shielding layer in the first isolation structure is further reduced, the coupling effect between word line layers at two sides of a channel region is reduced, meanwhile, the parasitic capacitance between adjacent word line layers in the first isolation structure is further reduced, and the device performance is further improved as a whole.

In another method for forming a dynamic random access memory provided by the technical scheme of the invention, a shielding layer is formed in the first trench, a third distance is formed between the surface of the shielding layer in the first isolation structure and the first surface, a fourth distance is formed between the surface of the shielding layer in the active region and the first surface, and the third distance is larger than the fourth distance, so that the size of the shielding layer in the first isolation structure is smaller than that of the shielding layer in the active region, and the shielding layer is designed to play a shielding role while reducing parasitic capacitance between adjacent word line layers in the first isolation structure, so that the coupling effect between the word line layers at two sides of the channel region is reduced, and the word line impact effect is reduced, and the device performance is improved as a whole.

Drawings

FIG. 1 is a schematic diagram of a DRAM structure;

FIGS. 2-30 are schematic diagrams illustrating steps of a method for forming a DRAM according to an embodiment of the present invention;

Fig. 31 to 41 are schematic structural views illustrating steps of a method for forming a dram according to another embodiment of the present invention.

Detailed Description

Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

As described in the background, there are still many problems with existing dynamic random access memories. The following will specifically explain.

FIG. 1 is a schematic diagram of a DRAM structure.

Referring to fig. 1, the dynamic random access memory comprises a substrate, wherein the substrate is provided with a first surface 100 and a second surface 101 which are opposite, the substrate comprises a plurality of active areas which are mutually separated and parallel to a first direction X, the plurality of active areas are arranged along a second direction Y, the first direction X is mutually perpendicular to the second direction Y, each active area comprises a plurality of word line areas I and a plurality of channel areas II, the plurality of word line areas I and the plurality of channel areas II in each active area are arranged at intervals along the first direction X, the word line areas I and the plurality of channel areas II in each active area are respectively provided with a plurality of word line wire grooves (not shown in the figure) which extend from the first surface 100 to the second surface 101 and are respectively penetrated through the active areas along the second direction Y, a first insulation layer 102 positioned at the bottom of the word line grooves, two mutually separated word line areas I and 103 positioned on the first insulation layer 102, a plurality of word line areas I and a plurality of channel areas II are respectively arranged at intervals along the first direction X, a plurality of doped word line wire grooves 107 positioned in each first surface 100 and a plurality of drain electrode structures 107 positioned in the first surface area 104, a plurality of drain electrode structures 107 positioned in each drain electrode structures 107 positioned in the first surface area 104 and the first surface area 104 are respectively arranged in the first surface area and are respectively connected with the first drain structures 107, the second source-drain doped region 109 extends from the second face 101 to the first face 100, and a plurality of bit lines 110 parallel to the first direction X are located on the second face 101, each bit line 110 being electrically connected to the second source-drain doped region 109 in one of the active regions.

The above structure is a vertical channel memory, and the shielding structure 106 is a void (air gap) structure, which is used to shield the coupling between the two word line gate structures 103 on both sides of the channel region II, however, the coupling is still large, and the resulting word line impact effect (Row HAMMER EFFECT) cannot meet the performance requirement of the product.

In order to solve the above problems, the technical solution of the present invention provides a dynamic random access memory and a forming method thereof, wherein a shielding layer in the first trench has a first size in a direction perpendicular to the surface of the substrate, the shielding layer in the first isolation structure has a second size, the second size is larger than the first size, and the shielding layer is designed to reduce parasitic capacitance between adjacent word line layers in the first isolation structure, and also to perform a shielding function, thereby reducing coupling function between two word line layers on both sides of a channel region, and reducing word line impact effect, and improving device performance as a whole.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 2 to 30 are schematic structural diagrams illustrating steps of a method for forming a dram according to an embodiment of the invention.

Referring to fig. 2 to 4, fig. 2 is a schematic top view of fig. 3 and 4 from a first side, fig. 3 is a schematic cross-sectional view along DD1 in fig. 2, fig. 4 is a schematic cross-sectional view along EE1 in fig. 2, a substrate 200 is provided, the substrate 200 has a first side 200a and a second side 200b opposite to each other, the substrate 200 includes a plurality of active regions 201 arranged along a first direction X and an initial first isolation structure 202, the first side 200a exposes a surface of the initial first isolation structure 202, the initial first isolation structure 202 is located between adjacent active regions 201, the plurality of active regions 201 are parallel to a second direction Y, the first direction X is perpendicular to the second direction Y, each active region 201 includes a plurality of channel regions I arranged along the second direction Y separately, and word line regions II located between adjacent channel regions I are arranged along the first direction X in different active regions 201.

The initial first isolation structure 202 is used to form a first isolation structure.

Subsequently, a number of first trenches and a number of second trenches are formed in the substrate 200, each of the first trenches and the second trenches penetrating the active region 201 and the initial first isolation structure 202 in a second direction Y and extending from the first face 200a to the second face 200b, the first trenches penetrating the channel region I and the second trenches penetrating the word line region II, an initial shielding layer is formed in the first trenches, and a word line gate structure is formed in the second trenches, the word line gate structure including two word line layers located on sidewalls of each of the second trenches and a second isolation structure located between the two word line layers, the second isolation structure isolating the two word line layers from each other.

In this embodiment, the initial shielding layer is formed first, and then the word line gate structure is formed.

In this embodiment, please refer to fig. 5 to 16 for a method for forming the first trench, the second trench, the initial shielding layer and the word line gate structure.

Referring to fig. 5 to 8, fig. 5 is a schematic top view of fig. 6 to 8 from a first side, fig. 6 is a schematic cross-sectional view along DD1 in fig. 5, fig. 7 is a schematic cross-sectional view along EE1 in fig. 5, fig. 8 is a schematic cross-sectional view along FF1 in fig. 5, and a plurality of initial trenches are formed in the substrate 200, wherein the initial trenches penetrating through the channel region I are the first trenches 203, and the initial trenches penetrating through the word line region II are the initial second trenches 204.

Referring to fig. 9 to 12, fig. 9 is a schematic top view of the first surface 200a in fig. 10 to 12, fig. 10 is a schematic cross-sectional structure along the DD1 direction in fig. 9, fig. 11 is a schematic cross-sectional structure along the EE1 direction in fig. 9, fig. 12 is a schematic cross-sectional structure along the FF1 direction in fig. 9, a protection layer 205 is formed in the initial second trench 204, and after the protection layer 205 is formed, the initial shielding layer 206 is formed in the first trench 203.

In this embodiment, the material of the initial shielding layer 206 includes a metal, and the metal includes titanium nitride. The initial shield layer 206 is used to form a shield layer.

In this embodiment, before the initial shielding layer 206 is formed, a first insulating layer 207 is formed on the sidewall and bottom of the first trench 203.

In this embodiment, the first insulating layer 207 and the initial shielding layer 206 are formed by forming a first insulating material layer (not shown) and a shielding material layer (not shown) on the first insulating material layer within the first trench 203 and on the first surface 200a, and planarizing the first insulating material layer and the shielding material layer until the first surface 200a is exposed.

In this embodiment, the top surface of the initial shielding layer 206 is lower than the first surface 200a.

In this embodiment, the method for forming the initial shielding layer 206 further includes etching back the shielding material layer after the planarization process.

In this embodiment, after the initial shielding layer 206 is formed, a second insulating layer 208 is further formed on the surface of the initial shielding layer 206 in the first trench 203.

In another embodiment, the initial shield layer within the initial first isolation structure has a third distance from the first face, the initial shield layer within the active region has a fourth distance from the first face, the third distance is less than the fourth distance. The initial shielding layer is in different sizes in the initial first isolation structure and the active region, so that in the finally formed dynamic random access memory, the size of the shielding layer positioned in the first isolation structure is further reduced, the coupling effect between word line layers at two sides of a channel region is reduced, meanwhile, the parasitic capacitance between adjacent word line layers in the first isolation structure is further reduced, and the device performance is further improved as a whole.

In another embodiment, the method for forming the initial shielding layer comprises the steps of forming a shielding material layer in the first groove, enabling the first face to expose the surface of the shielding material layer, forming a mask layer on the first face, enabling the mask layer to expose the surface of the shielding material layer in the initial first isolation structure, and etching the shielding material layer from the first face by taking the mask layer as a mask, so that the dimension of the initial shielding layer in the initial first isolation structure in the direction perpendicular to the surface of the substrate is reduced, and the initial shielding layer is formed.

With continued reference to fig. 13 on the basis of fig. 12, after the initial shielding layer 206 is formed, the protective layer 205 is removed to expose the initial second trench 204, and the initial second trench 204 is etched to increase the size of the initial second trench 204, thereby forming the second trench 209.

Referring to fig. 14 to 16, fig. 14 is a schematic top view of fig. 15 and 16 from a first side, fig. 15 is a schematic cross-sectional view along EE1 in fig. 14, fig. 16 is a schematic cross-sectional view along FF1 in fig. 15, and the word line gate structure is formed in the second trench 209.

The word line gate structure includes two word line layers located on sidewalls of each of the second trenches 209 and a second isolation structure 210 located between the two word line layers, and the second isolation structure 210 isolates the two word line layers from each other.

In this embodiment, the surface of the initial shielding layer 206 has a fifth distance from the second surface 200b, and the word line layer has a sixth distance from the second surface 200b, and the fifth distance is smaller than the sixth distance. The purpose of making the fifth distance smaller than the sixth distance is to avoid etching damage to the word line layer due to exposure of the word line layer when the initial shielding layer 206 is etched from the second surface 200b later.

In this embodiment, the word line layer includes a gate dielectric layer (not shown in the figure), a work function layer 211 located on a sidewall of the gate dielectric layer, and a gate electrode 212 located on a sidewall of the work function layer 211.

In this embodiment, the word line gate structure further includes a third insulating layer 213 between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench 209, and the top surface of the word line layer is lower than the surface of the first face 200 a.

In this embodiment, the word line gate structure further includes a fourth insulating layer 214 on the top surface of the word line layer.

In this embodiment, the method for forming the word line gate structure includes forming the third insulating layer 213 in the second trench 209, forming an initial word line layer (not shown) in the second trench 209 after forming the third insulating layer 213, the top surface of the initial word line layer being flush with the first surface 200a, etching a portion of the initial word line layer from the first surface 200a toward the second surface 200b, forming a plurality of fourth trenches (not shown) parallel to the second direction Y in the substrate 200, the fourth trenches penetrating the initial word line layer from the first surface 200a toward the second surface 200b, forming the two transition word line layers (not shown), forming the second isolation structure 210 in the fourth trenches, etching back the transition word line layer, forming the word line layer, and forming the fourth insulating layer 214 in the second trench 209 after forming the word line layer.

In the present embodiment, the fourth trench is formed by etching the initial word line layer from the first surface 200a toward the second surface 200 b. In another embodiment, the fourth trench may be formed by etching the active region and the initial word line layer from the second face toward the first face.

In this embodiment, the forming method of the initial word line layer and the word line layer includes forming a gate dielectric material layer (not shown) in the second trench 209 and on the first surface 200a, a work function material layer (not shown) on the gate dielectric material layer, and a gate material layer (not shown) on the work function material layer after forming the third insulating layer 213, planarizing the gate material layer, the work function material layer, and the gate dielectric material layer to form the initial word line layer, etching back the initial word line layer after the planarization process to form the word line layer, forming the gate dielectric layer with the gate dielectric material layer, forming the work function layer 211 with the work function material layer, and forming the gate 212 with the gate material layer.

In this embodiment, the material of the gate 212 is metal, and the metal includes copper, tungsten or gold.

Subsequently, after the word line gate structure and the initial shielding layer 206 are formed, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the initial first isolation structure 202 is exposed.

In this embodiment, after forming the word line gate structure and the initial shielding layer 206, and before the thinning process, please refer to fig. 17 to 18.

Referring to fig. 17 and 18, fig. 17 is a schematic structural view based on fig. 15, fig. 18 is a schematic structural view based on fig. 16, a plurality of first source-drain doped regions 215 are formed in the first surface 200a of each active region 201, and a plurality of capacitor structures 216 are formed on the first surface 200a after the plurality of first source-drain doped regions 215 are formed, wherein each capacitor structure 216 is electrically connected to one of the first source-drain doped regions 215.

In this embodiment, a capacitor plug 217 is further disposed between the capacitor structure 216 and the first source-drain doped region 215. In other embodiments, the capacitor structure 216 is directly connected to the first source-drain doped region 215 without a capacitor plug.

In this embodiment, the capacitor structures 216 and the capacitor plugs 217 are located in the second dielectric layer 218, and the forming method of the capacitor structures 216 and the capacitor plugs 217 includes forming a second dielectric layer 218 on the first surface 200a, forming first openings (not shown) in the second dielectric layer 218, where the first openings expose the surface of the first source-drain doped region 215, and forming the capacitor structures 216 and the capacitor plugs 217 in the first openings.

Referring to fig. 19 to 22, fig. 19 is a top view of the second surface 200b in fig. 20 to 22, fig. 20 is a schematic cross-sectional structure along the ee1 direction in fig. 19, fig. 21 is a schematic cross-sectional structure along the ff1 direction in fig. 19, and fig. 22 is a schematic cross-sectional structure along the dd1 direction in fig. 19, after the capacitor structure 216 is formed, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the initial first isolation structure 202 is exposed.

The thinning process includes a chemical mechanical polishing process.

It should be noted that, a fixed voltage is applied to the formed shielding layer to make the shielding layer play a shielding role, and for this reason, the circuit of the shielding layer may be led out from the first surface, or may be led out from the second surface.

In this embodiment, the circuitry of the shielding layer is subsequently led out from the second side 200b, and in another embodiment, the circuitry of the shielding layer is led out from the first side. That is, after forming the initial shield layer and before the thinning process, further comprising forming a shield extraction layer on the first face, the shield extraction layer being electrically interconnected with the initial shield layer. Specifically, a shield extraction layer may be formed on the first face after the capacitor structure is formed.

Referring to fig. 23 to 25, fig. 23 is a top view of the structure of fig. 24 to 25 from the second surface 200b, fig. 24 is a schematic view of a cross-sectional structure along the dd1 direction in fig. 23, fig. 25 is a schematic view of a cross-sectional structure along the ff1 direction in fig. 23, after the thinning process, the initial first isolation structure 202 and the initial shielding layer 206 are etched from the second surface 200b, so that the size of the initial shielding layer 206 in the initial first isolation structure 202 in the direction perpendicular to the surface of the substrate 200 is reduced, a shielding layer 219 is formed by the initial shielding layer 206, and a first isolation structure 220 is formed by the initial first isolation structure 202.

The size of the initial shielding layer 206 in the initial first isolation structure 202 in the direction perpendicular to the surface of the substrate 200 is reduced, so that the size of the shielding layer 219 in the first isolation structure 220 is smaller than the size of the shielding layer 219 in the active region 201, and the shielding layer 219 is designed to reduce parasitic capacitance between adjacent word line layers in the first isolation structure 220 and simultaneously to reduce coupling between word line layers at two sides of a channel region, thereby reducing word line impact effect and improving device performance as a whole.

In this embodiment, the word line layer has a sixth distance from the second surface 200b, and the shielding layer 219 in the first isolation structure 220 has a seventh distance from the second surface 200b, and the seventh distance is greater than the sixth distance. The purpose of making the seventh distance larger than the sixth distance is to reduce device leakage.

The material of the shielding layer 219 includes a conductor material including a metal. In this embodiment, the material of the shielding layer 219 is titanium nitride.

In this embodiment, the method for forming the shielding layer 219 further includes performing a first etching process on the initial first isolation structure 202 until the initial shielding layer 206 in the initial first isolation structure 202 is exposed, and performing a second etching process on the exposed initial shielding layer 206.

The first etch treatment process includes one or both of a dry etch process and a wet etch process. In this embodiment, the first etching process is a dry etching process.

The second etch treatment process includes one or both of a dry etch process and a wet etch process. In this embodiment, the second etching treatment process is a dry etching process.

In this embodiment, the initial first isolation structure 202 and the initial shielding layer 206 are etched, and a third trench 221 is formed in the substrate 200.

In this embodiment, after the shielding layer 219 is formed, please refer to fig. 26 to 29.

Referring to fig. 26 to 29, fig. 26 is a top view of the structure of fig. 28 to 29 from the second surface 200b, fig. 27 is a schematic cross-sectional structure of fig. 26 along ee1 direction, fig. 28 is a schematic cross-sectional structure of fig. 26 along ff1 direction, fig. 29 is a schematic cross-sectional structure of fig. 26 along dd1 direction, second source-drain doped regions 222 are formed in the second surface 200b of each of the active regions 201, and a plurality of bit lines 223 parallel to the second direction Y are formed on the second surface 200b, wherein each of the bit lines 223 is electrically connected with the second source-drain doped regions 222 in one of the active regions 201.

In this embodiment, after forming the shielding layer 219 and before forming the bit lines 223, forming a first dielectric layer 224 in the third trench 221 is further included.

In this embodiment, the bit line 223 is located in the third dielectric layer 225, and the forming method of the bit line 223 includes forming the third dielectric layer 225 on the first dielectric layer 224, forming a plurality of second openings (not shown) in the third dielectric layer 225, where the second openings expose the surface of the second source-drain doped region 222, and forming a plurality of bit lines 223 in the second openings.

With continued reference to fig. 30, after forming the bit lines 223, a metal interconnect layer 300 is formed on the second side 200b, the metal interconnect layer 300 is electrically interconnected with the bit lines 223, a logic wafer 400 is provided, the logic wafer 400 has a plurality of logic device layers 401 therein, and after forming the metal interconnect layer 300, the second side 200b is directed to the surface of the logic device layers 401, so that the substrate 200 and the logic wafer 400 are bonded to each other.

In this embodiment, after forming the shielding layer 219, forming a shielding extraction layer (not shown in the figure) that is electrically interconnected with the shielding layer 219 is further included. A fixed voltage is applied to the shield layer 219 through the shield lead-out layer to make the shield layer 219 play a shielding role.

In this embodiment, the shielding layer 219 is led out from the second surface 200 a. In another embodiment, the shielding layer is directed from the first face.

Accordingly, an embodiment of the present invention further provides a dram formed by the above method, as shown in fig. 26 to 30, which includes a substrate 200, the substrate 200 having a first surface 200a and a second surface 200b opposite to each other, the substrate 200 including a plurality of active regions 201 arranged along a first direction X and a first isolation structure 220 (as shown in fig. 23), the first isolation structure 220 being located between adjacent active regions 201, the plurality of active regions 201 being parallel to a second direction Y, the first direction X being perpendicular to the second direction Y, each of the active regions 201 including a plurality of channel regions I separated from each other and arranged along the second direction Y, and word line regions II located between the adjacent channel regions I, the word line regions II located in different active regions 201 being arranged along the first direction X; a number of first trenches 203 (as shown in fig. 8) and a number of second trenches 209 (as shown in fig. 8) within the substrate 200, the first trenches 203 and the second trenches 209 each extending through the active region 201 and the first isolation structure 220 in a second direction Y and extending from the first side 200a to the second side 200b, the first trenches 203 extending through the channel region I, the second trenches 209 extending through the word line region II, a shielding layer 219 within the first trenches 203, the shielding layer 219 within the first isolation structure 220 having a first dimension d1 in a direction perpendicular to the surface of the substrate 200, the shielding layer 219 within the active region 201 having a second dimension d2, the second dimension d2 being smaller than the first dimension d1, a word line gate structure located at a sidewall of the second trenches 209, the word line gate structure includes two word line layers located on sidewalls of each of the second trenches 209 and a second isolation structure 210 located between the two word line layers, and the second isolation structure 210 isolates the two word line layers from each other.

The shielding layer 219 located in the first trench 203 has a first size in a direction perpendicular to the surface of the substrate 200, the shielding layer 219 in the first isolation structure 220 has a second size, and the second size is larger than the first size, and the shielding layer 219 is designed to reduce parasitic capacitance between adjacent word line layers in the first isolation structure, and also to perform a shielding function, thereby reducing coupling between word line layers on both sides of the channel region, reducing word line impact effect, and improving device performance as a whole.

In this embodiment, the first surface 200a exposes the first isolation structure 220.

In this embodiment, the DRAM further includes a third recess 221 (as shown in FIG. 23) between adjacent active regions 201, the third recess 221 extending from the second surface 200b toward the first surface 200a, the bottom of the third recess 221 exposing the first isolation structure 220 and the shielding layer 219, and a first dielectric layer 224 within the third recess 221. That is, the third groove 221 in the second surface 200b exposes the first isolation structure 220. In another embodiment, the first and second faces each expose the first isolation structure.

In this embodiment, the surface of the shielding layer 219 in the first isolation structure 220 has a first distance from the second surface 200b, and the surface of the shielding layer 219 in the active region 201 has a second distance from the second surface 200b, and the first distance is greater than the second distance. In another embodiment, the shield layer surface within the first isolation structure has a third distance from the first face, the shield layer surface within the active region has a fourth distance from the first face, the third distance is greater than the fourth distance. In yet another embodiment, the first distance is greater than the second distance and the third distance is greater than the fourth distance.

In this embodiment, the DRAM further includes a first insulating layer 207, where the first insulating layer 207 is located between the shielding layer 219 and the sidewalls and bottom of the first trench 203, and a second insulating layer 208, where the second insulating layer 208 is located on the surface of the shielding layer 219.

The material of the first insulating layer 207 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first insulating layer 207 is silicon oxide.

The material of the second insulating layer 208 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second insulating layer 208 is silicon oxide.

In this embodiment, the word line gate structure further includes a third insulating layer 213 between the two word line layers and the bottom of the second isolation structure 210 and the bottom of the first trench 203, the top surface of the word line layer is lower than the surface of the first face 200a, and the word line gate structure further includes a fourth insulating layer 214 on the top surface of the word line layer.

In this embodiment, the DRAM further includes a shield extraction layer (not shown) on the second side 200b, the shield extraction layer being electrically interconnected with the shield layer 219. In another embodiment, a shield extraction layer is also included on the first side, the shield extraction layer being electrically interconnected with the shield layer.

In this embodiment, the dram further includes a plurality of first source-drain doped regions 215 disposed in the first side 200a of each of the active regions 201, and a plurality of capacitor structures 216 disposed on the first side 200a, each of the capacitor structures 216 being electrically connected to one of the first source-drain doped regions 215.

In this embodiment, the DRAM further includes a second source-drain doped region 222 located in the second side 200b of each active region 201, a plurality of bit lines 223 located on the second side 200b and parallel to the first direction X, each bit line 223 being electrically connected to the second source-drain doped region 222 in one of the active regions 201, a metal interconnection layer 300 located on the second side 200b, the metal interconnection layer 300 being electrically interconnected with the plurality of bit lines 223, and a logic wafer 400 bonded to the substrate 200 from the surface of the metal interconnection layer 300, wherein the logic wafer 400 has a plurality of logic devices 401 therein.

Fig. 31 to 41 are schematic structural views illustrating steps in a method for forming a dram according to another embodiment of the present invention.

The main difference between this embodiment and the previous embodiment is that the method of forming the shielding layer is different. In the above embodiment, the initial shielding layer is etched from the second face, so that the size of the initial shielding layer in the first isolation structure in the direction perpendicular to the surface of the substrate is reduced. In this embodiment, the initial shielding layer is etched from the first side, so that the size of the initial shielding layer in the first isolation structure in the direction perpendicular to the surface of the substrate is reduced.

Referring to fig. 31 to 33, fig. 31 is a schematic top view of fig. 32 and 33 from a first side 500a, fig. 32 is a schematic cross-sectional view along DD1 in fig. 31, fig. 33 is a schematic cross-sectional view along EE1 in fig. 31, a substrate 500 is provided, the substrate 500 has opposite first and second sides 500a and 500B, the substrate 500 includes a plurality of active regions 501 and first isolation structures 502 arranged along a first direction X, the first side 500a exposes the surface of the first isolation structures 502, the first isolation structures 502 are located between adjacent active regions 501, the plurality of active regions 501 are parallel to a second direction Y, the first direction X is perpendicular to the second direction Y, each active region 501 includes a plurality of channel regions a separated from each other and arranged along the second direction Y, and word line regions B located between adjacent channel regions a, and word line regions B located in different active regions 501 are arranged along the first direction X.

And forming a shielding layer in the first groove, wherein the surface of the shielding layer in the first isolation structure is at a third distance from the first surface, the surface of the shielding layer in the active region is at a fourth distance from the first surface, the third distance is larger than the fourth distance, and a word line grating structure is formed in the second groove and comprises two grid layers positioned on the side wall of the second groove and a second isolation structure positioned between the two word line layers, and the second isolation structure isolates the two word line layers from each other.

In this embodiment, please refer to fig. 34 to 37 for a method for forming the first trench, the second trench, the initial shielding layer and the word line gate structure.

Referring to fig. 34 to 37, fig. 34 is a schematic top view of fig. 35 to 37 from a first side 500a, fig. 35 is a schematic cross-sectional structure along DD1 in fig. 34, fig. 36 is a schematic cross-sectional structure along EE1 in fig. 34, fig. 37 is a schematic cross-sectional structure along FF1 in fig. 34, a plurality of initial trenches are formed in the substrate 500, wherein the initial trenches penetrating through the channel region a are the first trenches 503, and the initial trenches penetrating through the word line region B are initial second trenches (not shown), and a protection layer 505 is formed in the initial second trenches;

Referring to fig. 38 to 41, fig. 38 is a schematic top view of fig. 39 to 41 from a first surface 500a (the second insulating layer is omitted), fig. 39 is a schematic cross-sectional structure along DD1 in fig. 38, fig. 40 is a schematic cross-sectional structure along EE1 in fig. 38, fig. 41 is a schematic cross-sectional structure along FF1 in fig. 38, and after the protective layer 505 is formed, the shielding layer 506 is formed in the first trench 503.

In this embodiment, the method for forming the shielding layer 506 includes forming an initial shielding layer (not shown) in the first trench 503, where the first surface 500a exposes the initial shielding layer, forming a mask layer (not shown) on the first surface 500a, where the mask layer exposes the surface of the initial shielding layer in the first isolation structure 502, and etching the initial shielding layer with the mask layer as a mask to form the shielding layer 506.

In this embodiment, before the initial shielding layer is formed, a first insulating layer 507 is further formed on the sidewalls and bottom of the first trench 503.

In this embodiment, the top surface of the initial shielding layer is lower than the first face 500a.

Please refer to the description of the previous embodiment for the method for forming the initial shielding layer and the first insulating layer, which is not described herein.

In this embodiment, after the shielding layer 506 is formed, a second insulating layer 508 is further formed on the surface of the shielding layer 506.

Subsequently, after the shielding layer 506 is formed, the protection layer 505 is removed to expose the initial second trench 504, the initial second trench 504 is etched to increase the size of the initial second trench 504, the second trench is formed, and the word line gate structure is formed in the second trench.

The method for forming the second trench and the word line gate structure is described in the previous embodiment, and will not be described in detail herein.

In this embodiment, after the formation of the shielding layer and before the thinning process, a shielding extraction layer (not shown in the drawing) is further formed on the first face 500a, and the shielding extraction layer is electrically interconnected with the shielding layer.

In this embodiment, after the word line gate structure and the shielding layer are formed, the substrate 500 is thinned from the second surface 500b toward the first surface 500a until the first isolation structure 502 is exposed.

Accordingly, an embodiment of the present invention further provides a dram formed by the above method, please continue to refer to fig. 38 to 41.

The difference between the structure of this embodiment and the structure of the previous embodiment is that:

In the above embodiment, the surface of the shielding layer in the first isolation structure has a first distance from the second surface, the surface of the shielding layer in the active region has a second distance from the second surface, the first distance is greater than the second distance, the first surface exposes the first isolation structure, and the third groove in the second surface exposes the first isolation structure.

In this embodiment, the surface of the shielding layer in the first isolation structure has a third distance from the first surface, the surface of the shielding layer in the active region has a fourth distance from the first surface, the third distance is greater than the fourth distance, and the first surface and the second surface both expose the first isolation structure.

The design of the shielding layer 506 is beneficial to reducing parasitic capacitance between adjacent word line layers in the first isolation structure 502, and also plays a role in shielding, so that the coupling effect between the word line layers at two sides of the channel region A is reduced, the word line impact effect is reduced, and the device performance is improved as a whole.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A dynamic random access memory, comprising:

A substrate having opposite first and second sides, the substrate comprising a plurality of active regions arranged along a first direction and a first isolation structure, the first isolation structure being located between adjacent active regions, the plurality of active regions being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of channel regions separated from each other and arranged along the second direction, and word line regions located between adjacent channel regions, the word line regions located within different active regions being arranged along the first direction;

A plurality of first trenches and a plurality of second trenches within the substrate, each of the first trenches and the second trenches extending in a first direction through the active region and the first isolation structure and from the first face to the second face, the first trenches extending through the channel region, the second trenches extending through the word line region;

A shielding layer located within the first trench, the shielding layer within the first isolation structure having a first dimension in a direction perpendicular to the substrate surface, the shielding layer within the active region having a second dimension, the second dimension being greater than the first dimension;

And the word line grid structure is positioned on the side wall of the second groove and comprises two word line layers positioned on the side wall of each second groove and a second isolation structure positioned between the two word line layers, and the second isolation structure isolates the two word line layers from each other.

2. The dynamic random access memory of claim 1, wherein the first side and the second side each expose the first isolation structure.

3. The DRAM of claim 1 wherein the first side exposes the first isolation structure, the structure further comprising a third recess between adjacent active regions, the third recess extending from the second side toward the first side, the third recess bottom exposing the first isolation structure and the shield layer, and a first dielectric layer within the third recess.

4. The dynamic random access memory of claim 1, wherein the shield surface within the first isolation structure has a first distance from the second side, the shield surface within the active region has a second distance from the second side, the first distance is greater than the second distance, or the shield surface within the first isolation structure has a third distance from the first side, the shield surface within the active region has a fourth distance from the first side, the third distance is greater than the fourth distance, or the first distance is greater than the second distance, and the third distance is greater than the fourth distance.

5. The DRAM of claim 1 further comprising a first insulating layer between the shield layer and the first trench sidewall and bottom, a second insulating layer on the shield layer surface, wherein the material of the first insulating layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride, and wherein the material of the second insulating layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, and silicon oxycarbonitride.

6. The dynamic random access memory of claim 1, wherein the word line gate structure further comprises a third insulating layer between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench, wherein the top surface of the word line layer is lower than the first face surface, and wherein the word line gate structure further comprises a fourth insulating layer at the top surface of the word line layer.

7. The DRAM of claim 1, further comprising a shield extraction layer on the first side, wherein the shield extraction layer is electrically interconnected with the shield layer.

8. The DRAM of claim 1, further comprising a shield extraction layer on the second side, wherein the shield extraction layer is electrically interconnected with the shield layer.

9. The dynamic random access memory of claim 1, wherein the material of the shielding layer comprises a conductive material, and wherein the conductive material comprises a metal.

10. The DRAM of claim 1 further comprising a plurality of first source-drain doped regions in a first side of each of said active regions, and a plurality of capacitor structures on said first side, each of said capacitor structures being electrically connected to one of said first source-drain doped regions.

11. The DRAM of claim 1 further comprising a second source drain doped region in a second side of each of said active regions, a plurality of bit lines on said second side parallel to said second direction, each of said bit lines electrically connected to said second source drain doped region in one of said active regions, a metal interconnect layer on said second side, said metal interconnect layer electrically interconnected with a plurality of said bit lines, and a logic wafer bonded to said substrate from a surface of said metal interconnect layer, said logic wafer having a plurality of logic devices therein.

12. A method for forming a dynamic random access memory, comprising:

Providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and an initial first isolation structure, the active areas are arranged along a first direction, the first surface exposes the surface of the initial first isolation structure, the initial first isolation structure is positioned between adjacent active areas, the active areas are parallel to a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of channel areas which are mutually separated and are arranged along the second direction, word line areas are positioned between the adjacent channel areas, and the word line areas positioned in different active areas are arranged along the first direction;

Forming a plurality of first trenches and a plurality of second trenches within the substrate, each of the first trenches and the second trenches extending in a first direction through the active region and the initial first isolation structure and from the first face to the second face, the first trenches extending through the channel region, the second trenches extending through the word line region;

forming an initial shielding layer in the first groove;

Forming a word line grid structure in the second grooves, wherein the word line grid structure comprises two word line layers positioned on the side walls of each second groove and a second isolation structure positioned between the two word line layers, and the second isolation structure isolates the two word line layers from each other;

after the word line grating structure and the initial shielding layer are formed, thinning the substrate from the second surface to the first surface until the initial first isolation structure is exposed;

After the thinning treatment is performed, the initial first isolation structure and the initial shielding layer are etched from the second face, so that the size of the initial shielding layer in the initial first isolation structure in the direction perpendicular to the surface of the substrate is reduced, a shielding layer is formed by the initial shielding layer, and a first isolation structure is formed by the initial first isolation structure.

13. The method of claim 12, further comprising performing a first etching process on the initial first isolation structure until the initial shield layer within the initial first isolation structure is exposed, and performing a second etching process on the exposed initial shield layer.

14. The method of claim 13, wherein the first etching process comprises one or both of a dry etching process and a wet etching process, and wherein the second etching process comprises one or both of a dry etching process and a wet etching process.

15. The method of claim 13, further comprising forming a second source-drain doped region in a second side of each of said active regions after forming said shielding layer, and forming a plurality of bit lines on said second side parallel to said second direction, each of said bit lines being electrically connected to said second source-drain doped region in one of said active regions.

16. The method of claim 15, further comprising etching the initial first isolation structure and the initial shield layer to form a third trench in the substrate, and forming a first dielectric layer in the third trench.

17. The method of forming a DRAM of claim 16 further comprising forming a first insulating layer on the first trench sidewall and bottom prior to forming the initial shield layer.

18. The method of forming a DRAM of claim 17 wherein said first insulating layer and said initial shield layer are formed by forming a first insulating material layer and a shield material layer on a surface of said first insulating material layer within said first trench and on said first side surface, planarizing said first insulating material layer and said shield material layer until said first side surface is exposed, forming said first insulating layer with said first insulating material layer, and forming said initial shield layer with said shield material layer.

19. The method of claim 18, wherein a top surface of the initial shield layer is lower than the first surface, wherein the method further comprises etching back the shield material layer after the planarization process, and wherein forming a second insulating layer on the surface of the initial shield layer within the first trench after the initial shield layer is formed.

20. The method of forming a DRAM of claim 19 further comprising forming a metal interconnect layer on said second side after forming a plurality of said bit lines, said metal interconnect layer electrically interconnecting a plurality of said bit lines, providing a logic wafer having a plurality of logic device layers therein, and bonding said substrate and said logic wafer to each other after forming said metal interconnect layer with said second side facing a surface of said logic device layers.

21. The method of claim 12, wherein the initial shield layer surface in the initial first isolation structure has a third distance from the first surface, the initial shield layer surface in the active region has a fourth distance from the first surface, the third distance is greater than the fourth distance, the method of forming the initial shield layer comprises forming a shield material layer in the first trench, the first surface exposing the shield material layer surface, forming a mask layer on the first surface, the mask layer exposing the shield material layer surface in the initial first isolation structure, and etching the shield material layer from the first surface with the mask layer as a mask to reduce a dimension of the initial shield layer in the initial first isolation structure in a direction perpendicular to the substrate surface to form the initial shield layer.

22. The method of claim 12, wherein the word line gate structure further comprises a third insulating layer between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench, wherein the top surface of the word line layer is lower than the first surface, and wherein the word line gate structure further comprises a fourth insulating layer on the top surface of the word line layer.

23. The method of claim 22, wherein the forming the word line gate structure comprises forming the third insulating layer in the second trench, forming an initial word line layer in the second trench after forming the third insulating layer, the top surface of the initial word line layer being flush with the first surface, etching a portion of the initial word line layer from the first surface toward the second surface, forming a plurality of fourth trenches in the substrate parallel to the second direction, the fourth trenches penetrating the initial word line layer from the first surface toward the second surface, forming two transition word line layers, forming the second isolation structure in the fourth trench, etching back the transition word line layer, forming the word line layer, and forming the fourth insulating layer in the second trench after forming the word line layer.

24. The method of claim 12, further comprising forming a plurality of first source drain doped regions in a first side of each of the active regions after forming the word line gate structure and the initial shield layer and before the thinning process, and forming a plurality of capacitor structures on the first side after forming the plurality of first source drain doped regions, each of the capacitor structures being electrically connected to one of the first source drain doped regions.

25. The method of forming a DRAM of claim 12 further comprising forming a shield extraction layer after forming said shield layer, said shield extraction layer being electrically interconnected with said shield layer.

26. The method of forming a DRAM of claim 12 wherein after forming said initial shield layer and before said thinning, further comprising forming a shield extraction layer on said first side, said shield extraction layer being electrically interconnected with said initial shield layer.

27. The method of claim 12, wherein the forming the initial shield layer and then the word line gate structure, the forming the first trenches, the second trenches, the initial shield layer, and the word line gate structure comprises forming a plurality of initial trenches in the substrate, wherein the initial trenches penetrating the channel region are the first trenches, the initial trenches penetrating the word line region are the initial second trenches, forming a protective layer in the initial second trenches, forming the initial shield layer in the first trenches after forming the protective layer, removing the protective layer after forming the initial shield layer, exposing the initial second trenches, etching the initial second trenches to increase the size of the initial second trenches, forming the second trenches, and forming the word line gate structure in the second trenches.

28. The method of claim 12, wherein the material of the shielding layer comprises a conductive material, and wherein the conductive material comprises a metal.

29. The method of forming a dynamic random access memory of claim 12, wherein the initial shield layer surface has a fifth distance from the second side, the wordline layer has a sixth distance from the second side, and the fifth distance is less than the sixth distance.

30. A method for forming a dynamic random access memory, comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and a first isolation structure, the active areas are arranged along a first direction, the first surface is exposed out of the surface of the first isolation structure, the first isolation structure is positioned between adjacent active areas, the plurality of active areas are parallel to a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of channel areas which are mutually separated and are arranged along the second direction, word line areas are positioned between the adjacent channel areas, and the word line areas positioned in different active areas are arranged along the first direction;

forming a plurality of first trenches and a plurality of second trenches in the substrate, wherein the first trenches and the second trenches penetrate through the active region and the first isolation structure along a first direction and extend from the first surface to the second surface, the first trenches penetrate through the channel region, and the second trenches penetrate through the word line region;

Forming a shielding layer in the first groove, wherein the surface of the shielding layer in the first isolation structure is at a third distance from the first surface, the surface of the shielding layer in the active region is at a fourth distance from the first surface, and the third distance is larger than the fourth distance;

Forming a word line grating structure in the second groove, wherein the word line grating structure comprises two word line layers positioned on the side wall of the second groove and a second isolation structure positioned between the two word line layers, and the second isolation structure isolates the two word line layers from each other;

After the word line gate structure and the shielding layer are formed, the substrate is thinned from the second surface to the first surface until the first isolation structure is exposed.

31. The method of claim 30, wherein forming the shielding layer comprises forming an initial shielding layer in the first trench, wherein the first surface exposes the initial shielding layer, forming a mask layer on the first surface, wherein the mask layer exposes the surface of the initial shielding layer in the first isolation structure, and etching the initial shielding layer with the mask layer as a mask to form the shielding layer.

32. The method of claim 30, further comprising forming a shield extraction layer on the first side after forming the shield layer and before the thinning, the shield extraction layer being electrically interconnected with the shield layer.