CN116192120A - Level conversion circuit and driving circuit - Google Patents

Abstract

The application discloses a level shift circuit and a driving circuit. The level conversion circuit comprises a pulse generator, a switching unit, a conduction identification unit, a common mode processing unit and a trigger unit. The common mode processing unit is used for processing a common mode interference signal of the first identification signal and the second identification signal output by the conduction identification unit; the common mode processing unit comprises a first latch and a second latch, wherein the input end of the first latch is connected with a first identification signal end of the conduction identification unit, the enabling end of the first latch is connected with a second identification signal end of the common mode processing unit, the output end of the first latch is connected with the trigger unit, the input end of the second latch is connected with a second identification signal end of the conduction identification unit, the enabling end of the second latch is connected with the first identification signal end of the conduction identification unit, and the output end of the second latch is connected with the trigger unit. According to the method and the device, the common mode processing unit is additionally arranged, so that the common mode interference signal cannot be transmitted to the next stage, and the influence of the common mode interference is restrained.

Description

Level shifting circuit and driving circuit

technical field

The present application relates to the field of communication technology, and in particular to a level conversion circuit and a driving circuit.

Background technique

With the popularity of electricity, there are more and more application scenarios for power tubes. With the increase of power supply application scenarios, the demand for power tube control is increasing day by day. In order to make the power tube have better performance (switching speed, reliability, etc.), the gate-level driver chip used to drive the power tube is becoming more and more important. The gate-level driver chip converts a low-voltage logic signal into a logic signal whose voltage can float to high voltage, and controls the on and off of the peripheral high-voltage power transistor.

Since there is parasitic capacitance between the drain terminal of the conduction identification unit and the ground in the conventional level conversion circuit, the device connected to the drain terminal of the conduction identification unit needs to charge the drain terminal of the conduction identification unit. When the charging speed cannot make up for the rising speed of the power supply of the floating well, the drain terminal of the conduction identification unit will appear abnormally low level, that is, common mode interference will appear, which will affect the level conversion efficiency of the level conversion circuit . How to solve the influence of common-mode interference in the level conversion circuit on the circuit is a technical problem that needs to be solved urgently.

Contents of the invention

In view of this, the present invention aims to solve one of the problems in the related art at least to a certain extent. Therefore, the purpose of the present application is to provide a level conversion circuit and a driving circuit.

A level conversion circuit according to an embodiment of the present application. The level conversion circuit includes a pulse generator, a switch unit, a conduction identification unit, a common mode processing unit and a trigger unit. The pulse generator is used to generate the first pulse signal and the second pulse signal according to the level of the control signal to realize on-off control; the switch unit is connected to the pulse generator, and the switch unit is used for The first pulse signal and the second pulse signal are turned on and off; the conduction identification unit is connected to the switch unit, and the conduction identification unit is used to output the first identification according to the conduction state of the switch unit signal and a second identification signal; the common mode processing unit is connected to the conduction identification unit, and the common mode processing unit is used to process the common mode interference signal of the first identification signal and the second identification signal; The trigger unit is connected to the common-mode processing unit, and the trigger unit generates an output signal according to the first identification signal and the second identification signal processed by the common-mode processing unit; wherein, the common-mode processing unit Including a latch subunit, the latch subunit includes a first latch and a second latch, the input end of the first latch is connected to the first identification signal end of the conduction identification unit , the enable end of the first latch is connected to the second identification signal end of the conduction identification unit, the output end of the first latch is connected to the trigger unit, and the output end of the second latch is The input end is connected to the second identification signal end of the conduction identification unit, the enabling end of the second latch is connected to the first identification signal end of the conduction identification unit, and the output of the second latch is terminal connected to the trigger unit.

In some embodiments, the switch unit includes a first load, a first switch transistor, a second load, and a second switch transistor; wherein, the gate of the first switch transistor is connected to the first switch of the pulse generator. A pulse signal terminal, the first pole of the first switching transistor is connected to the first terminal of the first load, the second pole of the first switching transistor is connected to the second power supply, and the gate of the second switching transistor is connected to The second pulse signal terminal of the pulse generator, the first pole of the second switching transistor is connected to the first terminal of the second load, and the second pole of the second switching transistor is connected to the second power supply; The second end of the first load is connected to the first power supply, and the second end of the second load is connected to the first power supply.

In some embodiments, the conduction identification unit includes a first identification subunit and a second identification subunit, and the first identification subunit is connected to the first pole of the first switching transistor and the first load The first identification subunit is used to output the first identification signal according to the conduction state of the first switch transistor, and the second identification subunit is connected to the first terminal of the second switch transistor. pole and the first terminal of the second load, the second identification subunit outputs the second identification signal according to the conduction state of the second switching transistor.

In some embodiments, the first identification subunit includes a first P-type transistor and a first N-type transistor, and the gate of the first P-type transistor is connected to the gate of the first N-type transistor. The first pole of the first switching transistor and the first end of the first load, the first pole of the first P-type transistor is connected to the third power supply, and the second pole of the first P-type transistor is connected to the Turn on the first identification signal end of the identification unit, the first pole of the first N-type transistor is connected to the first identification signal end of the conduction identification unit, and the second pole of the first N-type transistor is connected to the fourth power supply.

In some embodiments, the second identification subunit includes a second P-type transistor and a second N-type transistor, and the gate of the second P-type transistor is connected to the gate of the second N-type transistor. The first pole of the second switching transistor and the first terminal of the second load, the first pole of the second P-type transistor is connected to the third power supply, and the second pole of the second P-type transistor is connected to the Turn on the second identification signal end of the identification unit, the first pole of the second N-type transistor is connected to the second identification signal end of the conduction identification unit, and the second pole of the second N-type transistor is connected to the fourth power supply.

In some embodiments, the trigger unit includes an RS flip-flop, the reset end of the RS flip-flop is used to receive the first identification signal, and the set end of the RS flip-flop is used to receive the second identification signal. identification signal, the output terminal of the RS flip-flop generates the output signal.

In some implementations, the level conversion circuit includes a filtering subunit, the filtering subunit is connected to the common mode processing unit and the triggering unit, and the filtering subunit is used to filter the first identification signal performing filtering processing with the second identification signal.

In some implementations, the filtering subunit includes a first filtering subunit and a second filtering subunit, and the output end of the first latch is connected to the RS flip-flop through the first filtering subunit. A reset terminal, the output terminal of the second latch is connected to the set terminal of the RS flip-flop through the second filter subunit.

In some embodiments, the first filtering subunit includes a first resistor and a first capacitor, and the first resistor is connected to the output terminal of the first latch and the reset terminal of the RS flip-flop, so The first capacitor is connected to the reset terminal of the RS flip-flop and ground; the second filtering subunit includes a second resistor and a second capacitor, and the second resistor is connected to the output terminal of the second latch and the The set end of the RS flip-flop, the second capacitor is connected to the set end of the RS flip-flop and ground.

The embodiments of the present application also provide a driving circuit. The driving circuit includes a power transistor and the level shifting circuit described in any one of the above implementation manners; the gate of the power transistor is connected to the output signal terminal of the trigger unit.

The level conversion circuit and the driving circuit of the present application add a common-mode processing unit, so that the common-mode interference signal will not be transmitted to the next stage, effectively suppressing the influence of the common-mode interference on the circuit.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

Figure 1 is a schematic diagram of the current traditional topological structure of driving high-voltage devices using floating wells;

Figure 2 is a schematic diagram of signals currently generating common-mode interference;

FIG. 3 is a schematic diagram of driving waveforms generated by driving high-voltage devices in the current floating well mode;

FIG. 4 is a schematic diagram of a level conversion circuit in some embodiments of the present application;

5 is a schematic structural diagram of the first identification subunit or the second identification subunit in the conduction identification unit in the level conversion circuit in some embodiments of the present application;

FIG. 6 is a schematic diagram of a driving circuit in some embodiments of the present application.

Detailed ways

Embodiments of the present application are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary, are only for explaining the present application, and should not be construed as limiting the present application.

In the description of the present application, it should be understood that the terms "first" and "second" are used for description purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise clearly and specifically defined.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or indirectly connected through an intermediary, may be internal communication between two components or interaction between two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

The following disclosure provides many different implementations or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and arrangements of specific examples are described below. Of course, they are examples only and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or reference letters in various instances, such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed.

Embodiments of the present application are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary, are only for explaining the present application, and should not be construed as limiting the present application.

The working principle of the gate-level driver chip is to convert the low-voltage logic control signal into a high-voltage logic control signal to control the power transistor. In the process of converting from low-voltage logic signals to high-voltage logic signals, its power is required to be as low as possible. On the one hand, low power represents high conversion efficiency. On the other hand, this high-voltage conversion is generally a conversion between a low voltage and a floating well, and the power supply of the floating well is generally generated by bootstrap. Generate your own power without the need for an external power source. This bootstrapping occurs by continually refreshing the stored finite charge of the matter.

The traditional topological structure of driving a high-voltage device by means of a floating well is shown in Fig. 1 . The circuit in the dotted frame is the circuit of the floating well. VB is the power supply of the floating well, and VS is the ground of the floating well. GND is the ground of the low voltage part. The overall circuit includes: a pulse generator for generating pulses on the rising and falling edges of the input signal HIN, and sends out SET and RST signals, as shown in Figure 2. The SET port drives a high-voltage device HVMOS for the low-voltage region and the floating well, and the signal passes through the resistor connected to the high-voltage well power supply (of course, it can also be other loads, such as current sources, etc.). The HVMOS conduction identification unit judges whether the HVMOS is conduction or not based on the difference in voltage or current at the access terminal caused by the conduction of the HVMOS, and passes the signal to the RS flip-flop after filtering. When the SET terminal HVMOS is turned on, the set terminal of the RS flip-flop is valid, and the RS flip-flop outputs a valid potential, so that the HO port outputs a valid potential; when the RST terminal HVMOS is turned on, the reset terminal of the RS flip-flop is valid, and the RS flip-flop Turn off the effective potential, so that the HO port output is turned off. In this way, the input signal of HIN can be accurately transmitted to the high voltage output HO through the short conduction of HVMOS. The advantage of this approach is to save power consumption. An example of the waveform is shown in Figure 3.

When the HO port outputs a high level and the peripheral power transistor is turned on, the VS voltage will be raised to several hundred volts (for example, 400V). At this time, VB will also be raised to a higher voltage due to the capacitance between VS (for example, 415V), at this time, the drain terminals of the two HVMOS are raised to a higher voltage. The HVMOS drain is raised from the initial lower voltage (3V or 15V) to a higher voltage (such as 403V or 415V). At this time, because there is a parasitic capacitance Cds between the HVMOS drain and the ground, it is connected to the HVMOS drain. A device connected to the terminal needs to charge the drain terminal of the HVMOS. When the charging speed cannot make up for the rising speed of VB, there will be an abnormally low level at the drain end of the HVMOS corresponding to RST, which is called common mode interference. as shown in picture 2. Wherein, the SET_HVD to VS signal is the drain terminal voltage of the HVMOS corresponding to SET, minus the ground signal VS in the floating well. Similarly, RST_HVDto VS is the waveform corresponding to RST.

In view of this, referring to FIG. 4 , the present application provides a level conversion circuit 100 . The level conversion circuit 100 includes a pulse generator 110 , a switch unit 120 , a conduction identification unit 130 , a common-mode processing unit 140 and a trigger unit 150 .

The pulse generator 110 is used for generating a first pulse signal and a second pulse signal according to the level of the control signal. The control signal is a low voltage logic control signal. The control signal is the low-voltage logic control signal HIN, the first pulse signal is the SET signal, and the second pulse signal is the RST signal.

The switch unit 120 is connected to the pulse generator 110, and the switch unit 120 is used to realize on-off control under the action of the first pulse signal and the second pulse signal. Wherein, the switch unit 120 includes a first switch transistor SET and a second switch transistor RST.

The conduction identification unit 130 is connected to the switch unit 120 . The conduction identification unit 130 is configured to output a first identification signal A1 and a second identification signal A2 according to the conduction state of the switch unit 120 . The conduction identification unit 130 may be, for example, an HVMOS conduction identification unit.

The common-mode processing unit 140 is connected to the conduction identification unit 130, and the common-mode processing unit 140 is configured to process common-mode interference signals of the first identification signal A1 and the second identification signal A2.

The common mode processing unit 140 includes a latch subunit 141 , and the latch subunit 141 includes a first latch 1411 and a second latch 1412 . The input terminal of the first latch 1411 is connected to the first identification signal terminal 131 of the conduction identification unit 130, the enabling terminal of the first latch 1411 is connected to the second identification signal terminal 132 of the conduction identification unit 130, and the first lock The output terminal of the register 1411 is connected to the trigger unit 150, the input terminal of the second latch 1412 is connected to the second identification signal terminal 132 of the conduction identification unit 130, and the enable terminal of the second latch 1412 is connected to the conduction identification unit 130 The first identification signal end 131 of the second latch 1412 is connected to the trigger unit 150 .

The trigger unit 150 is connected to the common-mode processing unit 140 , and the trigger unit 150 generates an output signal according to the first identification signal A1 and the second identification signal A2 processed by the common-mode processing unit 140 .

It can be understood that the working principle of the common-mode processing unit 140 of the level conversion circuit 100 of the present application is that when the effective signal of the first switching transistor SET is transmitted, the RST transmission line is latched by means of a latch. signal; when the effective signal of the second switching transistor RST is transmitted, the signal of the SET transmission line is latched by means of a latch. In this way, even if common-mode interference occurs, the common-mode interference signal will not be passed to the next stage. Among them, latching refers to temporarily storing a signal to maintain a certain level state.

Among them, the characteristics of the latch of the present application are: the A1 signal of the SET transfer line is the input A1 of the SET transfer line latch, and is also the latch enable signal CLK2 of the RST transfer line latch; the RST transfer line The A2 signal is the input A2 of the RST transfer line latch, and is also the latch enable signal CLK1 of the SET transfer line latch. Assuming that A1 which represents SET is valid is high level, then the CLK of the second latch 1412 is also high level, and at this time the output Y of the second latch 2 remains; when A1 is low level, the second latch 1412 CLK is also low level, at this time the output of the latch 142 is Y2=A2.

In this way, the level conversion circuit 100 of the present application adds a common-mode processing unit 140, and through the function of the latch in the common-mode processing unit 140, the common-mode interference signal will not be transmitted to the next stage, effectively suppressing the common-mode interference signal. The effect of mode interference on this level shifting circuit.

More specifically, referring to FIG. 4 , the switch unit 120 includes a first load R1 , a first switch transistor SET, a second load R2 and a second switch transistor RST. Wherein, the gate of the first switching transistor SET is connected to the first pulse signal terminal 111 of the pulse generator 110, the first pole of the first switching transistor SET is connected to the first end of the first load R1, and the second terminal of the first switching transistor SET The pole is connected to the second power supply GND, the gate of the second switching transistor RST is connected to the second pulse signal terminal of the pulse generator 110, the first pole of the second switching transistor RST is connected to the first end of the second load R2, and the second switching transistor RST The second pole of RST is connected to the second power supply GND. The second terminal of the first load R1 is connected to the first power supply VB, and the second terminal of the second load is connected to the first power supply VB.

The conduction identifying unit 130 includes a first identifying subunit 1311 and a second identifying subunit 1312 . The first identifying subunit 1311 is connected to the first pole of the first switching transistor SET and the first pole of the first load R1. The first identification subunit 1311 is configured to output a first identification signal A1 according to the conduction state of the first switching transistor SET. The second identification subunit 1312 is connected to the first pole of the second switch transistor RST and the first pole of the second load R2, and the second identification subunit 1312 outputs a second identification signal A2 according to the conduction state of the second switch transistor RST.

Please refer to FIG. 5 , the first identifying subunit 1311 includes a first P-type transistor MP1 and a first N-type transistor MN1 . The gate of the first P-type transistor and the gate of the first N-type transistor are connected to the first pole of the first switching transistor SET and the first pole of the first load R1. The first pole of the first P-type transistor MP1 is connected to the third power supply VB1, the second pole of the first P-type transistor MP1 is connected to the first identification signal terminal 131 of the conduction identification unit 130, and the first pole of the first N-type transistor MN1 It is connected to the first identification signal terminal 131 of the conduction identification unit 130 , and the second pole of the first N-type transistor MN1 is connected to the fourth power supply VB2 .

Similarly, the second identification subunit 1312 also includes a second P-type transistor MP2 and a second N-type transistor MN2, the gate of the second P-type transistor MP2 and the gate of the second N-type transistor MN2 are connected to the second switch transistor RST The first pole of the second load R2 is connected to the first pole of the second P-type transistor MP2, the first pole of the second P-type transistor MP2 is connected to the third power supply VB1, and the second pole of the second P-type transistor MN2 is connected to the second identification of the conduction identification unit 130 Signal terminal 132 , the first terminal of the second N-type transistor MN2 is connected to the second identification signal terminal 132 of the conduction identification unit 130 , and the second terminal of the second N-type transistor MN2 is connected to the fourth power supply VB2 .

The trigger unit 150 includes an RS flip-flop. The reset terminal of the RS flip-flop is used to receive the first identification signal A1, the set terminal of the RS flip-flop is used to receive the second identification signal A2, and the output terminal of the RS flip-flop generates an output signal. It can be understood that when common-mode interference occurs, the false effective signal that appears on the RST transmission line enters the RS flip-flop, and the transmission of this common-mode interference can be weakened by RC filtering.

In addition, please refer to FIG. 4 again, the common-mode processing unit 140 further includes a filtering sub-unit 142 . The filter subunit 142 is connected to the latch subunit 141 and the trigger unit 150 . The filtering subunit 142 is used for filtering the first identification signal A1 and the second identification signal A2. It can be understood that the first identification signal A1 and the second identification signal A2 processed by the filtering subunit 142 at this time are identification signals without common-mode interference signals after common-mode processing by the latch.

The filtering subunit 142 includes a first filtering subunit 1421 and a second filtering subunit 1422 . The output terminal of the first latch 1411 is connected to the reset terminal of the RS flip-flop through the first filter subunit, and the output terminal of the second latch 1412 is connected to the set terminal of the RS flip-flop through the second filter subunit 1422 . Understandably, when common-mode interference occurs, an erroneous effective signal will appear on the RST transmission line and enter the RS flip-flop, and the transmission of this common-mode interference can be weakened by RC filtering.

More specifically, the first filtering subunit 1421 includes a first resistor R3 and a first capacitor C1. The first resistor R3 is connected to the output terminal of the first latch 1411 and the reset terminal of the RS flip-flop, and the first capacitor C1 is connected to the reset terminal of the RS flip-flop and ground.

The second filtering subunit 1422 includes a second resistor R4 and a second capacitor C2. The second resistor R4 is connected to the output terminal of the second latch 1412 and the set terminal of the RS flip-flop, and the second capacitor C2 is connected to the set terminal of the RS flip-flop and ground.

Referring to FIG. 6 , the present application also provides a driving circuit 1000 . The driving circuit 1000 includes the level conversion circuit 100 and the power transistor 200 described in the above embodiments. The gate PMG of the power transistor 200 is connected to the output signal terminal of the trigger unit 150 . Wherein, the structure of the level shifting circuit 100 is as described above, and will not be repeated here.

The structure of the power tube 200 is shown in FIG. 6 . The voltage of the PMD terminal and the PMS terminal may be below 0V, or may reach the withstand voltage value of the high-power tube, such as 600V or 1200V. The switching function of the power transistor 200 is realized by controlling the voltage difference between its gate PMG and source PMS. Wherein, as shown in FIG. 6 , the voltage VPMG output by the level conversion circuit 100 controls the voltage of the gate PMG, and the voltage VPMS output by the level conversion circuit 100 controls the voltage of the source PMS. When the VPMG-VPMS voltage output by the level conversion circuit 100 is equal to 0V, the power transistor is turned off; when the VPMG-VPMS voltage output by the level conversion circuit 100 is equal to 15V, the power transistor 200 is turned on.

The characteristics of the drive circuit 1000 are: the VS voltage can float within a relatively large range, such as 0-600V, wherein VS is the source voltage, but the VGS voltage is within a small range, such as 0-20V, VGS is the gate-to-source voltage. The drive circuit 1000 converts a low-voltage logic signal into a logic signal whose voltage can float to a high voltage, and controls the on and off of the peripheral high-voltage power transistor.

The level conversion circuit 100 in the driving circuit 1000 of the present application adds a common-mode processing unit 140, and through the function of the latch in the common-mode processing unit 140, the common-mode interference signal will not be transmitted to the next stage, effectively The impact of common mode interference on the drive circuit is suppressed.

The above examples only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims (10)

1. A level conversion circuit, characterized in that, comprising: a pulse generator, configured to generate a first pulse signal and a second pulse signal according to the level of the control signal; A switch unit, the switch unit is connected to the pulse generator, and the switch unit is used to realize on-off control under the action of the first pulse signal and the second pulse signal; A conduction identification unit, the conduction identification unit is connected to the switch unit, and the conduction identification unit is used to output a first identification signal and a second identification signal according to the conduction state of the switch unit; A common-mode processing unit, the common-mode processing unit is connected to the conduction identification unit, and the common-mode processing unit is used to process common-mode interference signals of the first identification signal and the second identification signal; a trigger unit, the trigger unit is connected to the common-mode processing unit, and the trigger unit generates an output signal according to the first identification signal and the second identification signal processed by the common-mode processing unit; Wherein, the common mode processing unit includes a latch subunit, the latch subunit includes a first latch and a second latch, and the input end of the first latch is connected to the conduction The first identification signal terminal of the identification unit, the enabling terminal of the first latch is connected to the second identification signal terminal of the conduction identification unit, and the output terminal of the first latch is connected to the trigger unit, The input end of the second latch is connected to the second identification signal end of the conduction identification unit, and the enabling end of the second latch is connected to the first identification signal end of the conduction identification unit, so The output end of the second latch is connected to the trigger unit. 2. The level conversion circuit according to claim 1, wherein the switch unit comprises a first load, a first switch transistor, a second load, and a second switch transistor; Wherein, the gate of the first switch transistor is connected to the first pulse signal terminal of the pulse generator, the first pole of the first switch transistor is connected to the first end of the first load, and the first switch The second pole of the transistor is connected to the second power supply, the gate of the second switching transistor is connected to the second pulse signal terminal of the pulse generator, and the first pole of the second switching transistor is connected to the first terminal of the second load. At one end, the second pole of the second switching transistor is connected to the second power supply; The second end of the first load is connected to the first power supply, and the second end of the second load is connected to the first power supply. 3. The level conversion circuit according to claim 2, wherein the conduction identification unit comprises a first identification subunit and a second identification subunit, and the first identification subunit is connected to the first switch The first pole of the transistor and the first end of the first load, the first identification subunit is used to output the first identification signal according to the conduction state of the first switching transistor, and the second identification subunit The unit is connected to the first pole of the second switch transistor and the first end of the second load, and the second identification subunit outputs the second identification signal according to the conduction state of the second switch transistor. 4. The level conversion circuit according to claim 2, wherein the first identification subunit comprises a first P-type transistor and a first N-type transistor, and the gate of the first P-type transistor is connected to the first N-type transistor. The gate of the first N-type transistor is connected to the first pole of the first switch transistor and the first end of the first load, the first pole of the first P-type transistor is connected to a third power supply, and the first The second pole of a P-type transistor is connected to the first identification signal end of the conduction identification unit, the first pole of the first N-type transistor is connected to the first identification signal end of the conduction identification unit, and the first The second pole of an N-type transistor is connected to the fourth power supply. 5. The level conversion circuit according to claim 2, wherein the second identification subunit comprises a second P-type transistor and a second N-type transistor, and the gate of the second P-type transistor is connected to the second N-type transistor. The gate of the second N-type transistor is connected to the first pole of the second switch transistor and the first end of the second load, the first pole of the second P-type transistor is connected to a third power supply, and the first The second poles of the two P-type transistors are connected to the second identification signal terminal of the conduction identification unit, and the first poles of the second N-type transistor are connected to the second identification signal end of the conduction identification unit. The second poles of the two N-type transistors are connected to the fourth power supply. 6. The level conversion circuit according to claim 1, wherein the trigger unit comprises an RS flip-flop, a reset terminal of the RS flip-flop is used to receive the first identification signal, and the RS flip-flop The setting terminal of the RS flip-flop is used to receive the second identification signal, and the output terminal of the RS flip-flop generates the output signal. 7. The level conversion circuit according to claim 6, wherein the common-mode processing unit includes a filtering subunit, and the filtering subunit is connected to the latch subunit and the trigger unit, the The filtering subunit is configured to filter the first identification signal and the second identification signal. 8. The level conversion circuit according to claim 7, wherein the filtering subunit comprises a first filtering subunit and a second filtering subunit, and the output terminal of the first latch passes through the first filtering subunit A filter subunit is connected to the reset terminal of the RS flip-flop, and the output terminal of the second latch is connected to the set terminal of the RS flip-flop through the second filter subunit. 9. The level conversion circuit according to claim 8, wherein the first filter subunit comprises a first resistor and a first capacitor, and the first resistor is connected to the output terminal of the first latch and the reset terminal of the RS flip-flop, the first capacitor is connected to the reset terminal of the RS flip-flop and ground; The second filter subunit includes a second resistor and a second capacitor, the second resistor is connected to the output terminal of the second latch and the set terminal of the RS flip-flop, and the second capacitor is connected to the The setting terminal and ground of the above-mentioned RS flip-flop. 10. A driving circuit, characterized in that, comprising: The level conversion circuit according to any one of claims 1-9; A power tube, the gate of the power tube is connected to the output signal terminal of the trigger unit.

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