CN116192063B - A predistortion extended model and a method and apparatus for implementing predistortion therein. - Google Patents
A predistortion extended model and a method and apparatus for implementing predistortion therein.Info
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- CN116192063B CN116192063B CN202111428943.0A CN202111428943A CN116192063B CN 116192063 B CN116192063 B CN 116192063B CN 202111428943 A CN202111428943 A CN 202111428943A CN 116192063 B CN116192063 B CN 116192063B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
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- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The embodiment of the application provides a predistortion expansion model, a predistortion implementation method and a predistortion implementation device, which are used for improving the linearity of a PA and reducing the power consumption of a base station system under the condition of limited sampling rate. The method comprises the steps of determining an input estimated signal and an output estimated signal corresponding to any one of two adjacent sampling time intervals of a power amplifier in a linear interpolation mode, expanding a Generalized Memory Polynomial (GMP) model by taking the input estimated signal and the output estimated signal as the input signal and the output signal of the GMP model to obtain an expanded GMP model, inquiring a first lookup table (LUT) value corresponding to a first input signal through the original GMP model, inquiring a second LUT value corresponding to the first input signal through the expanded model, and generating the predistortion signal according to the first LUT value and the second LUT value.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a predistortion extension model, and a method and apparatus for implementing predistortion.
Background
Aiming at the problem of high energy consumption of a fifth generation mobile communication system (5G), a high-efficiency radio frequency Power Amplifier (PA) adopting a gallium nitride technology is widely applied to base station products, but the problem of poor linearity of the high-efficiency PA is inevitable, on the premise of ensuring the PA efficiency, the further improvement of the linearity of the PA is particularly important, and the digital predistortion technology (DIGITAL PRE-display, DPD) has the advantages of excellent linearization performance, convenience for hardware realization and the like, and is widely applied to the improvement of the linearity of a Power Amplifier (called Power Amplifier for short) of the base station products.
At present, due to the ultra-high rate transmission performance of 5G communication, the transmission bandwidth is increased, for example, the sub-6G maximum continuous bandwidth can even reach 200MHz, and for DPD, in order to ensure the modeling accuracy of the power amplification model, the bandwidth of the feedback link is generally required to be 5 times of the transmission bandwidth, the bandwidth of the feedback link reaches the GHz level at maximum (i.e., the sampling speed of the feedback link Analog-to-digital converter (Analog-Digital Converter, ADC) reaches the GHz level), which has higher requirements on the ADC and the digital signal Processor (DIGITAL SIGNAL Processor, DSP) in the feedback link, so that the cost of the base station product is greatly increased, and when the digital predistortion processing is performed at a higher sampling rate, the power consumption of the programmable logic array (Field Programmable GATE ARRAY, FPGA) is also increased, which affects the heat dissipation of the base station.
Disclosure of Invention
The embodiment of the application provides a predistortion expansion model, a predistortion implementation method and a predistortion implementation device, which are used for improving the linearity of a PA and reducing the power consumption of a base station system under the condition of limited sampling rate.
In a first aspect, a predistortion extension model and a method for implementing predistortion thereof are provided, the method comprising:
determining an input estimated signal and an output estimated signal corresponding to any one of two adjacent sampling time intervals of the power amplifier in a linear interpolation mode;
The input estimated signal and the output estimated signal are used as input signals and output signals of a generalized memory polynomial model (GMP) to expand the GMP model to obtain an expanded GMP model, wherein the expanded GMP model comprises an original GMP model and an expanded GMP model, the expanded GMP model is used for generating a predistortion signal according to the input estimated signal, the input estimated signal is in a proportional relation with a first input signal, and the first input signal is an input signal acquired at any sampling moment of the two adjacent sampling moments;
Querying a first lookup table LUT value corresponding to the first input signal through the original GMP model, and querying a second LUT value corresponding to the first input signal through the extended model;
The predistortion signal is generated from the first LUT value and the second LUT value.
Optionally, the obtaining, by a linear interpolation manner, the input estimated signal and the output estimated signal corresponding to any one of the adjacent moments includes:
acquiring a first input signal and a first output signal corresponding to a first moment, and acquiring a second input signal and a second output signal corresponding to a second moment, wherein the first moment and the second moment are moments corresponding to the two adjacent sampling moments respectively;
and determining the input estimated signal according to the first input signal and the second input signal and determining the output estimated signal according to the first output signal and the second output signal by a linear interpolation mode.
Optionally, the generating a predistortion signal according to the LUT value includes:
Multiplying the first LUT value and the second LUT value with the first input signal respectively to obtain a first product and a second product;
The predistortion signal is derived based on the first product and the second product.
Optionally, the querying, by the original GMP model, the LUT value of the first lookup table corresponding to the first input signal includes:
determining a first amplitude index corresponding to the first input signal through the original GMP model;
and inquiring the first LUT value according to the first amplitude index.
Optionally, the querying, by the extended model, the second LUT value corresponding to the first input signal includes:
determining a second amplitude index corresponding to the first input signal through the expansion model;
Querying the third LUT value according to the second amplitude index;
Inquiring a fourth LUT value according to the signal sampling time and the signal amplitude corresponding to the first input signal through the expansion model;
and obtaining a second LUT value based on the third LUT value and the fourth LUT value.
In a second aspect, there is provided a predistortion extension model and an apparatus for implementing predistortion, the apparatus comprising:
The processing module is used for determining an input estimated signal and an output estimated signal corresponding to any moment in the interval between two adjacent sampling moments of the power amplifier in a linear interpolation mode;
The model expansion module is used for expanding the GMP model by taking the input estimated signal and the output estimated signal as the input signal and the output signal of a generalized memory polynomial model GMP to obtain an expanded GMP model, wherein the expanded GMP model comprises an original GMP model and an expanded model, the expanded GMP model is used for generating a predistortion signal according to the input estimated signal, the input estimated signal is in a proportional relation with a first input signal, and the first input signal is an input signal acquired at any sampling moment of the two adjacent sampling moments;
The processing module is further configured to query, by using the original GMP model, a first LUT value corresponding to the first input signal, and query, by using the extended model, a second LUT value corresponding to the first input signal;
The processing module is further configured to generate the predistortion signal according to the first LUT value and the second LUT value.
Optionally, the processing module is specifically configured to:
acquiring a first input signal and a first output signal corresponding to a first moment, and acquiring a second input signal and a second output signal corresponding to a second moment, wherein the first moment and the second moment are moments corresponding to the two adjacent sampling moments respectively;
and determining the input estimated signal according to the first input signal and the second input signal and determining the output estimated signal according to the first output signal and the second output signal by a linear interpolation mode.
Optionally, the processing module is specifically configured to:
Multiplying the first LUT value and the second LUT value with the first input signal respectively to obtain a first product and a second product;
The predistortion signal is derived based on the first product and the second product.
Optionally, the processing module is further configured to:
determining a first amplitude index corresponding to the first input signal through the original GMP model;
and inquiring the first LUT value according to the first amplitude index.
Optionally, the processing module is specifically configured to:
determining a second amplitude index corresponding to the first input signal through the expansion model;
Querying the third LUT value according to the second amplitude index;
Inquiring a fourth LUT value according to the signal sampling time and the signal amplitude corresponding to the first input signal through the expansion model;
and obtaining a second LUT value based on the third LUT value and the fourth LUT value.
In a third aspect, an electronic device is provided, the electronic device comprising:
A memory for storing program instructions;
And a processor, configured to call the program instructions stored in the memory, and execute the steps included in the method according to any one of the first aspect according to the obtained program instructions.
In a fourth aspect, there is provided a computer readable storage medium storing computer executable instructions for causing a computer to perform the steps comprised by the method of any one of the first aspects.
In a fifth aspect, a computer program product comprising instructions is provided which, when run on a computer, causes the computer to perform the predistortion extension model described in the various possible implementations described above and a method of implementing predistortion.
In the embodiment of the application, the sampling signals (namely the input estimated signals and the output estimated signals) are estimated in a linear interpolation mode, the estimated sampling signals are used as the input and output signals of the GMP model, the extended GMP model is obtained by deduction, the predistortion of the input estimated signals (namely the predistortion signals are generated according to the input estimated signals) can be realized by the extended GMP model through the LUT, thus, the input and output signals of the ultra-wide bandwidth power amplifier can be modeled with high precision under the condition of lower feedback sampling rate, the linearity of the power amplifier is improved, the power consumption of a base station system can be effectively reduced because the high sampling rate is not needed, and the cost of a base station product can be effectively controlled because the ADC and the DSP in a feedback link do not need to use the ADC and the DSP with higher requirements.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application.
Fig. 1 is a flowchart of predistortion signal generation corresponding to a conventional GMP model according to an embodiment of the present application;
FIG. 2 is a flowchart of a predistortion extension model and a method for implementing predistortion according to an embodiment of the present application;
Fig. 3 is a flowchart of predistortion signal generation corresponding to an extended model in an extended GMP model according to an embodiment of the present application;
Fig. 4 is a block diagram of a predistortion extension model and a device for implementing predistortion according to an embodiment of the present application;
Fig. 5 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. Embodiments of the application and features of the embodiments may be combined with one another arbitrarily without conflict. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.
The terms first and second in the description and claims of the application and in the above-mentioned figures are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the term "include" and any variations thereof is intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The term "plurality" in the present application may mean at least two, for example, two, three or more, and embodiments of the present application are not limited.
In addition, the term "and/or" is merely an association relation describing the association object, and means that three kinds of relations may exist, for example, a and/or B, and that three kinds of cases where a exists alone, while a and B exist alone, exist alone. The character "/" herein generally indicates that the associated object is an "or" relationship unless otherwise specified.
For easy understanding, the technical background of the embodiments of the present invention will be described first.
As described above, the DPD technology has the advantages of excellent linearization performance, convenience for hardware implementation and the like, and is widely applied to the improvement of the power amplification degree of a base station product, wherein the DPD technology is used for obtaining output data containing the power amplification distortion characteristic by coupling at the power amplification output end, modeling the power amplification characteristic by using the power amplification input and output data, solving an inverse model of the power amplification characteristic in a medium frequency digital domain, and complementing the inverse model and the power amplification cascade, thereby achieving the purpose of improving the power amplification degree. Therefore, the key of the DPD technology is to obtain an accurate power amplifier model.
The Volterra series model is a nonlinear device and a common behavior modeling model of a nonlinear system, a power amplifier is used as the most important nonlinear device in a base station product, the Volterra series model is also suitable for behavior modeling of the power amplifier, but the Volterra series model has the advantages of complex model, more coefficients, no benefit to engineering realization, and a plurality of simplified models such as a memory polynomial model (Memory Polynomial, MP), an envelope memory polynomial model (Envelope Memory Polynomial, EMP), a generalized memory polynomial model (Generalized Memory Polynomial, GMP) and the like based on the Volterra series are sequentially proposed, and the GMP model has the advantages of high cost performance (high modeling precision, lower model complexity, convenience for Field Programmable Gate Array (FPGA) table lookup realization) and the like, and is widely applied to engineering.
The conventional GMP (i.e., raw GMP) model formula is shown in formula (1):
Wherein y (n) and x (n) are respectively an output signal and an input signal of the power amplifier after being subjected to digital processing, i is the memory depth of a vector term, j is the memory depth of a module value term, k is a nonlinear order, and b is a model coefficient, and as can be known from the formula (1), the power amplifier output signal y (n) can be obtained by multiplying x (n) and the k-th power of the module value term.
As mentioned above, the technology is mostly implemented by using a table look-up method, that is, the modulus term of the same i, j value is multiplied by the corresponding coefficient b ijk, and the amplitude of the input signal is quantized according to a certain rule to obtain an amplitude table and a corresponding LUT table. Therefore, before looking up the table according to the GMP model, a corresponding amplitude index needs to be generated, and the corresponding LUT value is queried according to the amplitude index. For example, the amplitude index corresponding to the formula (1) is as follows:
The flow of generating the predistortion signal corresponding to the conventional GMP model is shown in fig. 1, where the input signal x (n) is i-delayed to obtain Z -i, j-delayed to obtain Z -j, modulo Z -j to obtain an amplitude index shown in formula (2), and then querying the LUT value corresponding to the amplitude index shown in formula (2) in the LUT table, and multiplying the result obtained by the query with Z -i to obtain the i-j-delayed predistortion signal (i.e., u ij (n)).
However, the traditional GMP model can only realize predistortion by looking up a table of the collected input signals, however, in the fifth generation mobile communication system, the sampling rate of the feedback link ADC reaches the GHz level, so that the cost of a base station product is greatly increased, and when the digital predistortion processing is performed at a higher sampling rate, the power consumption of an FPGA is increased, and the heat dissipation of the base station is affected.
In view of this, the embodiment of the application provides a predistortion extension model and a predistortion implementation method thereof, which determine an input estimated signal and an output estimated signal corresponding to any one of two adjacent sampling time intervals of a power amplifier in a linear interpolation manner, use the input estimated signal and the output estimated signal as the input signal and the output signal of a GMP model, extend the GMP model to obtain an extended GMP model, and implement predistortion on the input estimated signal by looking up a table of the extended GMP model.
The predistortion expansion model and the predistortion implementation method thereof provided by the embodiment of the application are described below with reference to the attached drawings. Referring to fig. 2, a predistortion extension model and a method for implementing predistortion according to an embodiment of the present application are described as follows:
step 201, determining an input estimated signal and an output estimated signal corresponding to any one of two adjacent sampling time intervals of a power amplifier in a linear interpolation mode;
In the embodiment of the application, a first input signal and a first output signal corresponding to a first moment in two adjacent sampling moments are acquired, and a second input signal and a second output signal corresponding to a second moment in two adjacent sampling moments are acquired, wherein an earlier moment in the two adjacent sampling moments can be the first moment or the second moment.
After the input signals and the output signals corresponding to the two adjacent sampling moments are acquired, the input predicted signals and the output predicted signals corresponding to any one moment of the two adjacent sampling moments are determined through a linear interpolation mode according to the acquired input signals and the acquired output signals, specifically, the input predicted signals are determined according to the first output signals and the second input signals, the output predicted signals are determined according to the first output signals and the second output signals, for example, the first input signals, the first output signals, the second input signals and the second output signals can be respectively represented in the form of coordinate points, the input signals and the output signals corresponding to the same moment are one coordinate point (a first input signal a and a second output signal b), and the coordinates of any point on a straight line can be determined because the two points determine a straight line. Therefore, under the condition of not increasing the sampling rate, the estimated signals among the sampling signals can be obtained through a linear interpolation mode, the effect of increasing the sampling rate is achieved, the anti-aliasing capability of the model is further improved, and the modeling precision is improved.
Step 202, using the input estimated signal and the output estimated signal as the input signal and the output signal of the GMP model to expand the GMP model, and obtaining an expanded GMP model;
the extended GMP model may generate a corresponding predistortion signal according to an input pre-estimated signal, that is, the extended GMP model queries a Look-Up Table (LUT) value corresponding to the input pre-estimated signal by a Table Look-Up method, so as to generate the corresponding predistortion signal, where when the extended GMP model queries the LUT value corresponding to the input pre-estimated signal, the extended GMP model needs to query through a first input signal, and at this time, since the input pre-estimated signal obtained by a linear interpolation method and the first input signal are in a proportional relationship, after the input pre-estimated signal is obtained according to the first input signal and the second input signal, the input pre-estimated signal may be represented by the first input signal, where the first input signal is an input signal acquired at any sampling moment of two adjacent sampling moments, for example, the input signal acquired at the first moment in step 201, or the input signal acquired at the second moment in step 201.
In the embodiment of the application, the input estimated signal and the output estimated signal are used as the input signal and the output signal of the GMP model, and the GMP model is derived to obtain the extended GMP model, wherein the GMP model is a mathematical model, so that the process of extending the GMP model is a process of deriving the polynomial corresponding to GMP, the number of polynomial terms included in the obtained extended GMP model after the model is extended is more than that before the model is extended, and therefore, the LUT value inquired through the extended GMP model is more than that inquired through the GMP model (namely the original GMP model) before the extension, so that the linearity of the PA can be effectively improved.
Step 203, inquiring a first LUT value corresponding to a first input signal through an original GMP model;
In an embodiment of the present application, a first amplitude index corresponding to the first input signal is determined by the original GMP model described in step 202, and the first LUT value is queried according to the first amplitude index.
Step 204, inquiring a second LUT value corresponding to the first input signal through the expansion model;
In the embodiment of the present application, the second amplitude index corresponding to the first input signal is determined by the extended model in step 202, the third LUT value is queried according to the second amplitude index, the fourth LUT value is queried by the extended model according to the signal sampling time and the signal amplitude corresponding to the first input signal, and the third LUT value and the fourth LUT are multiplied to obtain the second LUT value. Wherein, since the fourth LUT value is related to only the sampling time and the signal amplitude of the signal, the lookup table corresponding to the fourth LUT value can be shared. Therefore, the random access memory (Random Access Memory, RAM) resources needed by the model realization can be reduced, and the implementation is realized by selecting smaller resource FPGA, thereby being beneficial to the cost control of the base station product.
Step 205, generating a predistortion signal according to the first LUT value and the second LUT value.
In the embodiment of the present application, after the first LUT value and the second LUT value are queried in step 203 and step 204, the first LUT value and the second LUT value are multiplied by the first input signal to obtain a first product and a second product, and the first product and the second product are added to obtain a predistortion signal corresponding to the input estimation signal.
In order to better understand the technical scheme of the present application, the predistortion extension model and the method for implementing predistortion provided by the present application will be explained below with reference to specific embodiments.
Examples
Before expanding the GMP model, firstly, determining an input estimated signal and an output estimated signal corresponding to any time in two adjacent sampling time intervals of a power amplifier in a linear interpolation mode, wherein the process of acquiring the input estimated signal and the output estimated signal in the linear interpolation mode is described as follows:
Assuming that (x 1,y1) and (x 2,y2) are the power amplifier input signal and the power amplifier output signal at two adjacent sampling moments, and the two points determine a straight line, the coordinates (x, y) of any point on the straight line can be determined according to (x 1,y1) and (x 2,y2), and the reference formula is as follows:
When the arbitrary point is located in the middle of the two points (i.e., when the arbitrary point is the middle point between the first point and the second point), x= (x 1+x2)/2,y＝(y1+y2)/2 can be obtained.
At this time, for the power amplifier sampling points at the first time and the second time, the input estimated signal x (n ') and the output estimated signal y (n') corresponding to the intermediate point between the two points are obtained by linear interpolation, where:
substituting x (n ') and y (n') into formula (1) to obtain:
Substituting formulas (4) and (5) into formula (6), developing by polynomial, and deriving GMP expansion term (i.e. the expansion model) after linear value insertion AndIn order to facilitate the implementation of the FPGA look-up table, when k 2 of the extension term is 1, the extended GMP model after linear interpolation may be represented by the following formula (7):
the amplitude index corresponding to the original model is shown in formula (2), and the amplitude index corresponding to the extended model is shown as follows:
And (3) making:
LUTs=|AMP(n)| (10)
Then:
LUTC＝LUTm×LUTs(n-m±1) (11)
the LUT C is a second LUT value, the LUT m is a third LUT value, and the LUT s is a fourth LUT value.
In combination with equations (2), (7) and (11), after signal interpolation, the table look-up implementation of the extended GMP model can be expressed as:
Wherein, the The flow of the corresponding predistortion signal generation is shown in figure 1,The corresponding predistortion signal generation flow is shown in figure 3, and the input signal is delayed by m 1 to obtainAnd is opposite toTaking out the mould to obtain the productThe amplitude index shown, then look up the corresponding LUT value (third LUT value) in the LUT0 table based on the amplitude index, and associate the third LUT value withMultiplying to obtain a first result, andFurther time-delay is carried out to obtainAnd is opposite toAnd taking a modulus to obtain an amplitude index shown as LUT s (n-m+/-1) I, inquiring a corresponding LUT value (namely a fourth LUT value) in the LUT_S table according to the amplitude index, and multiplying the third LUT value by the first result to obtain a predistortion signal corresponding to m 1 delay. Or multiplying the third LUT value and the fourth LUT value to obtain a second LUT value, and then comparing the second LUT value with the fourth LUT valueMultiplication results in a predistortion signal corresponding to the m 1 delay (the process corresponding to the method is not shown in fig. 3).
And adding the predistortion signals corresponding to the delays to obtain predistortion signals (X DA _DPD (n)) corresponding to the extension, and finally adding the predistortion signals corresponding to the extension to the predistortion signals corresponding to the original GMP model (namely, the signals output in the process shown in the figure 1) (the process is not shown in the figure 3, and the figure 3 only shows the generation process of the predistortion signals corresponding to the expansibility) to obtain predistortion signals aiming at the input estimated signals.
Based on the same inventive concept, the embodiment of the application provides a predistortion extension model and a predistortion implementation device thereof, wherein the predistortion extension model and the predistortion implementation device thereof can realize functions corresponding to the predistortion extension model and the predistortion implementation method thereof. The predistortion extension model and the device for realizing predistortion can be a hardware structure, a software module or a hardware structure plus a software module. The predistortion expansion model and the predistortion implementation device thereof can be implemented by a chip system, and the chip system can be formed by a chip or can contain the chip and other discrete devices. Referring to fig. 4, the predistortion extension model and the apparatus for implementing predistortion include a processing module 401 and a model extension module 402. Wherein:
The processing module 401 is configured to determine, by using a linear interpolation manner, an input estimated signal and an output estimated signal corresponding to any one of two adjacent sampling time intervals of the power amplifier;
The model expansion module 402 is configured to expand the GMP model by using the input estimated signal and the output estimated signal as an input signal and an output signal of a generalized memory polynomial model GMP to obtain an expanded GMP model, where the expanded GMP model includes an original GMP model and an expanded model, and the expanded GMP model is configured to generate a predistortion signal according to the input estimated signal, where the input estimated signal is shown in a proportional relationship with a first input signal, and the first input signal is an input signal acquired at any sampling time of the two adjacent sampling times;
The processing module 401 is further configured to query, by using the original GMP model, a first LUT value corresponding to the first input signal, and query, by using the extended model, a second LUT value corresponding to the first input signal;
The processing module 401 is further configured to generate the predistortion signal according to the first LUT value and the second LUT value.
Optionally, the processing module 401 is specifically configured to:
acquiring a first input signal and a first output signal corresponding to a first moment, and acquiring a second input signal and a second output signal corresponding to a second moment, wherein the first moment and the second moment are moments corresponding to the two adjacent sampling moments respectively;
and determining the input estimated signal according to the first input signal and the second input signal and determining the output estimated signal according to the first output signal and the second output signal by a linear interpolation mode.
Optionally, the processing module 401 is specifically configured to:
Multiplying the first LUT value and the second LUT value with the first input signal respectively to obtain a first product and a second product;
The predistortion signal is derived based on the first product and the second product.
Optionally, the processing module 401 is further configured to:
determining a first amplitude index corresponding to the first input signal through the original GMP model;
and inquiring the first LUT value according to the first amplitude index.
Optionally, the processing module 401 is specifically configured to:
determining a second amplitude index corresponding to the first input signal through the expansion model;
Querying the third LUT value according to the second amplitude index;
Inquiring a fourth LUT value according to the signal sampling time and the signal amplitude corresponding to the first input signal through the expansion model;
and obtaining a second LUT value based on the third LUT value and the fourth LUT value.
All relevant contents of each step related to the foregoing predistortion extension model and the embodiment of the predistortion implementation method thereof can be cited to the functional description of the functional module corresponding to the predistortion extension model and the predistortion implementation device in the embodiment of the present application, and are not repeated here.
The division of the modules in the embodiments of the present application is schematically only one logic function division, and there may be another division manner in actual implementation, and in addition, each functional module in each embodiment of the present application may be integrated in one processor, or may exist separately and physically, or two or more modules may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules.
Based on the same inventive concept, the embodiment of the application provides electronic equipment. Referring to fig. 5, the electronic device includes at least one processor 501 and a memory 502 connected to the at least one processor, and in the embodiment of the present application, a specific connection medium between the processor 501 and the memory 502 is not limited, and in fig. 5, the connection between the processor 501 and the memory 502 through a bus 500 is taken as an example, and the bus 500 is shown in a bold line in fig. 5, and a connection manner between other components is only illustrative and not limited. Bus 500 may be divided into an address bus, a data bus, a control bus, etc., and is represented by only one thick line in fig. 5 for ease of illustration, but does not represent only one bus or one type of bus.
In the embodiment of the present application, the memory 502 stores instructions executable by the at least one processor 501, and the at least one processor 501 may execute the steps included in the predistortion extension model and the method for implementing predistortion described above by executing the instructions stored in the memory 502.
The processor 501 is a control center of the electronic device, and may use various interfaces and lines to connect various parts of the entire electronic device, and by executing or executing instructions stored in the memory 502 and invoking data stored in the memory 502, various functions of the electronic device and processing data, thereby performing overall monitoring of the electronic device. Alternatively, the processor 501 may include one or more processing units, and the processor 501 may integrate an application processor and a modem processor, wherein the application processor primarily processes an operating system and application programs, etc., and the modem processor primarily processes wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 501. In some embodiments, processor 501 and memory 502 may be implemented on the same chip, or they may be implemented separately on separate chips in some embodiments.
The processor 501 may be a general purpose processor such as a Central Processing Unit (CPU), digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, and may implement or perform the methods, steps and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The predistortion extension model and the method for implementing predistortion disclosed in connection with the embodiment of the application can be directly embodied as a hardware processor for execution or a combination of hardware and software modules in the processor for execution.
The memory 502, as a non-volatile computer readable storage medium, may be used to store non-volatile software programs, non-volatile computer executable programs, and modules. The Memory 502 may include at least one type of storage medium, and may include, for example, flash Memory, hard disk, multimedia card, card Memory, random access Memory (Random Access Memory, RAM), static random access Memory (Static Random Access Memory, SRAM), programmable Read-Only Memory (Programmable Read Only Memory, PROM), read-Only Memory (ROM), charged erasable programmable Read-Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only Memory, EEPROM), magnetic Memory, magnetic disk, optical disk, and the like. Memory 502 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 502 in embodiments of the present application may also be circuitry or any other device capable of performing storage functions for storing program instructions and/or data.
By programming the processor 501, the code corresponding to the predistortion extension model and the predistortion implementation method described in the foregoing embodiment may be cured into the chip, so that the chip can execute the steps of the predistortion extension model and the predistortion implementation method when running, and how to program the processor 501 is a technology known to those skilled in the art will not be described herein.
Based on the same inventive concept, embodiments of the present application also provide a computer readable storage medium storing computer instructions that, when run on a computer, cause the computer to perform the steps of the predistortion extension model and the method of implementing predistortion as described above.
In some possible embodiments, the predistortion extension model and the method for implementing predistortion provided by the present application may also be implemented as a form of a program product, which includes program code for causing a detection device to execute the steps in the predistortion extension model and the method for implementing predistortion according to various exemplary embodiments of the present application described in the present specification when the program product is run on an electronic device.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (12)
1. A predistortion extension model and a method for implementing predistortion, wherein the method comprises:
determining an input estimated signal and an output estimated signal corresponding to any one of two adjacent sampling time intervals of the power amplifier in a linear interpolation mode;
The input estimated signal and the output estimated signal are used as input signals and output signals of a Generalized Memory Polynomial (GMP) model, the GMP model is expanded to obtain an expanded GMP model, the expanded GMP model comprises the GMP model and an expanded model, the GMP model is used for inquiring a first LUT value corresponding to a first input signal, the expanded model is used for inquiring a second LUT value corresponding to the first input signal, the first input signal is the input signal acquired at any sampling moment of the two adjacent sampling moments, the first input signal is in proportional relation with the input estimated signal, and the LUT is a lookup table;
generating a predistortion signal from the first LUT value and the second LUT value;
Wherein the extended model satisfies the following relationship:
Wherein, the For the first input signal to be present,In order for the time to be delayed,In order to be non-linear in order,Is a model coefficient.
2. The method of claim 1, wherein the obtaining, by linear interpolation, the input predicted signal and the output predicted signal corresponding to any one of the adjacent time instants comprises:
acquiring a first input signal and a first output signal corresponding to a first moment, and acquiring a second input signal and a second output signal corresponding to a second moment, wherein the first moment and the second moment are moments corresponding to the two adjacent sampling moments respectively;
and determining the input estimated signal according to the first input signal and the second input signal and determining the output estimated signal according to the first output signal and the second output signal by a linear interpolation mode.
3. The method of claim 1, wherein the generating a predistortion signal from the first LUT value and the second LUT value comprises:
Multiplying the first LUT value and the second LUT value with the first input signal respectively to obtain a first product and a second product;
The predistortion signal is derived based on the first product and the second product.
4. The method of claim 1, wherein querying a first look-up table LUT value corresponding to the first input signal comprises:
determining a first amplitude index corresponding to the first input signal;
and inquiring the first LUT value according to the first amplitude index.
5. The method of claim 1, wherein querying a second LUT value corresponding to the first input signal comprises:
determining a second amplitude index corresponding to the first input signal;
querying a third LUT value according to the second amplitude index;
inquiring a fourth LUT value according to the signal sampling time and the signal amplitude corresponding to the first input signal;
and obtaining a second LUT value based on the third LUT value and the fourth LUT value.
6. A predistortion extension model and a device for realizing predistortion, wherein the device comprises:
The processing module is used for determining an input estimated signal and an output estimated signal corresponding to any moment in the interval between two adjacent sampling moments of the power amplifier in a linear interpolation mode;
The model expansion module is used for expanding the GMP model by taking the input estimated signal and the output estimated signal as the input signal and the output signal of the Generalized Memory Polynomial (GMP) model to obtain an expanded GMP model, wherein the expanded GMP model comprises the GMP model and an expanded model, the GMP model is used for inquiring a first LUT value corresponding to a first input signal, the expanded model is used for inquiring a second LUT value corresponding to the first input signal, the first input signal is the input signal acquired at any sampling moment of the two adjacent sampling moments, the first input signal is in proportional relation with the input estimated signal, and the LUT is a lookup table;
the processing module is further configured to generate a predistortion signal according to the first LUT value and the second LUT value;
Wherein the extended model satisfies the following relationship:
Wherein, the For the first input signal to be present,In order for the time to be delayed,In order to be non-linear in order,Is a model coefficient.
7. The apparatus of claim 6, wherein the processing module determining the input predicted signal and the output predicted signal corresponding to any one of two adjacent sampling time intervals of the power amplifier by linear interpolation comprises:
acquiring a first input signal and a first output signal corresponding to a first moment, and acquiring a second input signal and a second output signal corresponding to a second moment, wherein the first moment and the second moment are moments corresponding to the two adjacent sampling moments respectively;
and determining the input estimated signal according to the first input signal and the second input signal and determining the output estimated signal according to the first output signal and the second output signal by a linear interpolation mode.
8. The apparatus of claim 6, wherein the processing module to generate the predistortion signal from the first LUT value and the second LUT value comprises:
Multiplying the first LUT value and the second LUT value with the first input signal respectively to obtain a first product and a second product;
The predistortion signal is derived based on the first product and the second product.
9. The apparatus of claim 6, wherein the processing module querying a first LUT value corresponding to a first input signal comprises:
determining a first amplitude index corresponding to the first input signal;
and inquiring the first LUT value according to the first amplitude index.
10. The apparatus of claim 6, wherein the processing module querying a second LUT value corresponding to the first input signal comprises:
determining a second amplitude index corresponding to the first input signal;
querying a third LUT value according to the second amplitude index;
inquiring a fourth LUT value according to the signal sampling time and the signal amplitude corresponding to the first input signal;
and obtaining a second LUT value based on the third LUT value and the fourth LUT value.
11. An electronic device, comprising:
A memory for storing program instructions;
a processor for invoking program instructions stored in said memory and for performing the steps comprised in the method according to any of claims 1-5 in accordance with the obtained program instructions.
12. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method of any of claims 1-5.
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| CN110336541A (en) * | 2019-07-10 | 2019-10-15 | 电子科技大学 | Digital predistortion processing method based on memory and cross memory polynomial model |
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| US20140333376A1 (en) * | 2013-05-09 | 2014-11-13 | King Fahd University Of Petroleum And Minerals | Scalable digital predistortion system |
| CN103685111B (en) * | 2013-12-26 | 2017-01-11 | 大唐移动通信设备有限公司 | Calculating method of digital pre-distortion parameters and pre-distortion system |
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| CN102014090A (en) * | 2010-12-13 | 2011-04-13 | 中兴通讯股份有限公司 | Digital predistortion method and device |
| CN110336541A (en) * | 2019-07-10 | 2019-10-15 | 电子科技大学 | Digital predistortion processing method based on memory and cross memory polynomial model |
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