CN116190346A - Power supply structure for integrated chip system - Google Patents

Abstract

The present invention relates to the field of semiconductor technology, in particular to a power supply structure for integrated chip systems, including a power management system, an intermediary layer and an integrated chip system, the intermediary layer includes a substrate layer, an RDL layer, and can vertically penetrate through the intermediary The vertical connection structure of the layer, the upper and lower ends of the vertical connection structure are respectively provided with interconnectors, the power management system is connected to the upper end of the vertical connection structure through the interconnectors, and the integrated chip system is connected through The interconnector is connected to the lower end of the vertical connection structure. This structure can realize the high-density interconnection between the power management system and the integrated chip system through the 2.5D interposer technology, which meets the demand of the integrated chip system for the power supply voltage, and can achieve the effect of small package size and high quality of electrical signal transmission .

Description

A Power Supply Structure Oriented to Integrated Chip System

technical field

The invention relates to the technical field of semiconductors, in particular to a power supply structure oriented to an integrated chip system.

Background technique

At present, with the continuous improvement of artificial intelligence's requirements for computing speed, integrated chips have become an effective solution to improve chip computing power. In the chip process, the maximum area (Reticlesize) that an advanced lithography machine can support for a single exposure is 3.3cm×2.6cm, so that one maximum area exposure will form at least one device design (Die). A chip with an area larger than 3.3cm×2.6cm contains multiple Dies, so such a chip is called an integrated chip. The integrated chip can realize the functions of multiple Dies at the same time, and reduce the limitation of communication bandwidth between Dies, so as to obtain bandwidth improvement.

A chip set composed of a plurality of logic chips packaged on the same substrate has a similar structure and function to the above-mentioned integrated chip, so the present invention refers to these two structures as an integrated chip system, as shown in Figure 1; in order to express For convenience, the present invention refers to the repetitive unit of the integrated chip system as Tile. For an integrated chip, a Die in the chip is a Tile; for a chip collection, a chip in the collection is a Tile.

References Designing a 2048-Chiplet, 14336-Core Waferscale ProcesSor, the integrated chip system mainly has two power supply schemes: horizontal power supply and vertical power supply. Among them, the horizontal power supply scheme uses a DC-DC step-down converter as the power management module, and sets it at the horizontal adjacent position of the integrated chip system. The electrical signal enters through the power pins around the integrated chip system, and then passes through the on-chip power supply. The wires are transmitted to each Tile on the chip system; the vertical power supply scheme selects a power management module based on an LDO circuit and sets it on the integrated chip system, and the electrical signal directly vertically enters the power pins of each Tile. Advantages of the vertical power delivery method over the horizontal power delivery method include:

(1) Avoid using large-area off-chip devices in the DC-DC step-down converter, such as inductors and capacitors, which saves the package area;

(2) The PDN impedance generated by the on-chip power supply wiring will cause a large difference in IR-Drop between the Tile at the edge of the chip system and the Tile at the center, which may cause timing problems and signal integrity problems in the multi-Tile system. Vertical power supply This can be avoided. Therefore, using an on-chip LDO chip to provide vertical power supply for an integrated chip system has become a mainstream power supply solution.

As shown in FIG. 2 , using a through silicon via (TSV) technology (Through Silicon Via, TSV) to complete multiple LDO chips to supply power to the integrated chip system is one of the options. However, the manufacturing process of TSV is complicated, which will greatly increase the process cost of chip packaging. Interposer technology in 2.5DIC design can avoid TSV. As shown in FIG. 3 , the interposer technology places the LDO chips 102 , 103 , 104 side by side horizontally on the top of the interposer 109 , and the integrated chip 105 is located at the bottom of the interposer. Each LDO chip is interconnected with the integrated chip 105 through the vertical structure 107 in the interposer 109 , so as to supply power to each Tile in the integrated chip. The interposer can be made of materials other than silicon, so the use of TSVs can be avoided and the cost can be significantly reduced.

At present, the difficulty in completing the PDN design of an integrated chip with the help of interposer technology is mainly reflected in the design complexity of the LDO chip. As shown in FIG. 3 , the interposer 109 includes a redistribution layer (RDL layer), and the RDL layer is used to transmit the voltage and ground signals provided by the DC power supply to each LDO chip from both sides of the interposer to form a global PDN of the structure. The lengths of metal wires of each LDO chip in the global PDN are different, so different wire voltage drops are generated, resulting in differences in input voltages of each LDO chip. However, the homogeneous integrated chip scenario requires that each tile has the same voltage input, and each LDO chip needs to output the same voltage when the input voltage differs greatly, which increases the difficulty of LDO design. On this basis, how to design and control the global PDN so as to reduce the design complexity of the LDO chip has become the key to the PDN design of the integrated chip system.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned problems in the prior art and provide a power supply structure for integrated chip systems. The same voltage drop of each power management module in the power management system, thereby reducing the design complexity of the power management system.

Above-mentioned purpose is to realize through following technical scheme:

A power supply structure oriented to an integrated chip system, including a power management system, an intermediary layer and an integrated chip system, the intermediary layer including a substrate layer, an RDL layer and a vertical connection structure that can vertically penetrate through the intermediary layer, the vertical The upper and lower ends of the connection structure are respectively provided with interconnectors, the power management system is connected to the upper end of the vertical connection structure through the interconnectors, and the integrated chip system is connected to the vertical Connect the lower end of the structure.

Further, the RDL layer is formed by successively laying multiple layers of metal layers and insulating dielectric layers between adjacent metal layers, forming a typical capacitor structure of "metal-dielectric-metal"; setting on the metal layer There are metal traces, and conductive vias are provided in the insulating medium layer, and the conductive vias are connected to the metal traces on adjacent metal layers;

The substrate layer is arranged under the RDL layer, and is used for carrying the RDL layer and realizing the connection between the RDL layer and the integrated chip system.

Further, the circuit performing voltage conversion in the power management system is an LDO circuit, and the LDO circuit can provide a stable voltage output;

The power management system is a distributed power management chip composed of multiple LDO circuits, or a chip set composed of multiple distributed power management chips.

Further, it also includes a global power supply that can provide a DC power supply, and the global power supply inputs the DC power supply along the edge of the interposer layer; the metal traces and the conductive vias in the RDL layer connect the global power supply The voltage and ground signal of the power supply are connected to the power management system to form the global PDN of this structure; the output voltage of the power management system is transmitted to the integrated chip through the vertical connectors in the interposer respectively system to form a local PDN.

Further, a plurality of conductive pads are disposed on the metal layer on the top of the RDL layer, and the conductive pads are used to carry the interconnection element disposed under the power management system and form an electrical connection.

Further, the interconnection is a micro-bump, and the micro-bump is a combination of one or more of copper pillars, solder balls, and controllable collapse chip connection structures.

Further, the integrated chip system refers to a logic chip with a size larger than 3.3cm×2.6cm, or a chip assembly composed of multiple logic chips packaged on the same substrate.

Further, the substrate layer is a glass substrate, or a ceramic substrate, or an insulating composite layer.

Further, the number of the metal layer in the RDL layer is at least two, the number of the insulating medium layer is at least one, and the top and bottom of the RDL layer must be the metal layer.

Further, the material of the insulating medium includes but not limited to polyimide and silicon dioxide.

Beneficial effect

The power supply structure oriented to the integrated chip system provided by the present invention can realize the high-density interconnection between the power management system and the integrated chip system through the 2.5D interposer technology, and meets the demand of the integrated chip system for the power supply voltage. In addition, the effects of small packaging volume and high electrical signal transmission quality can be achieved.

Description of drawings

Fig. 1 is a system schematic diagram of a power supply structure oriented to an integrated chip system according to the present invention, wherein (a) is an integrated chip; (b) is a chip set;

FIG. 2 is a schematic diagram of a power supply structure of a stacked chip provided by the related art;

3 is a schematic diagram of a first packaging structure of a power supply structure oriented to an integrated chip system according to the present invention;

4 is a schematic diagram of a second package structure of a power supply structure oriented to an integrated chip system according to the present invention;

5 is a schematic diagram of a third package structure of a power supply structure oriented to an integrated chip system according to the present invention;

6 is a schematic diagram of a fourth package structure of a power supply structure oriented to an integrated chip system according to the present invention;

7 is a top view corresponding to the first packaging structure of a power supply structure oriented to an integrated chip system according to the present invention;

8 is a schematic diagram of a first structure of an intermediary layer in a power supply structure oriented to an integrated chip system according to the present invention;

FIG. 9 is a schematic diagram of a second structure of an intermediary layer in a power supply structure oriented to an integrated chip system according to the present invention.

Icon mark description

101-first package structure, 102-first power management chip, 103-second power management chip, 104-third power management chip, 105 integrated chip, 106-first micro bump, 107-vertical connection structure , 108-second microbump, 109-intermediate layer, 110-RDL layer, 111-first wiring structure, 112-second wiring structure, 113-third wiring structure, 121-conductive pad, 123 - Conductive vias, 124 - Substrate layer, 201 - Second packaging structure, 202 - Distributed power chip, 301 - Third packaging structure, 302 - Logic chip, 401 - Fourth packaging structure.

Detailed ways

The present invention will be described in further detail below according to the drawings and embodiments. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in Figures 3 to 6, a power supply structure for an integrated chip system includes a power management system, an interposer 109, and an integrated chip system. The interposer 109 includes a substrate layer 124, an RDL layer 110, and a The vertical connection structure 107 of the intermediary layer 109, the upper and lower ends of the vertical connection structure 107 are respectively provided with interconnectors, the power management system is connected to the upper end of the vertical connection structure 107 through the interconnectors, The integrated chip system is connected to the lower end of the vertical connection structure 107 through the interconnection.

Wherein, the RDL layer 110 is formed by sequentially laying multiple metal layers and insulating dielectric layers between adjacent metal layers, forming a typical capacitor structure of "metal-dielectric-metal"; There are metal traces, and conductive vias 123 are provided in the insulating medium layer, and the conductive vias 123 are connected to the metal traces on adjacent metal layers;

The substrate layer 124 is disposed under the RDL layer 110 for carrying the RDL layer 110 and realizing the connection between the RDL layer 110 and the integrated chip system.

The interconnection is a micro-bump, and the micro-bump is a combination of one or more of copper pillars, solder balls, and controllable collapse chip connection structures.

The circuit performing voltage conversion in the power management system is a low drop-out linear voltage converter (Low Drop-Out Voltage Regulator, LDO), and the LDO circuit can provide a stable voltage output;

The power management chip system refers to a distributed power management chip composed of multiple LDO circuits, or a chip set composed of multiple power management chips; for the convenience of expression, the present invention refers to the repetitive unit of the power management system as for the module. For a distributed power management chip, an LDO circuit in the chip is a module; for a chip set, a chip in the set is a module.

The global power supply of this power supply structure is input from the edge of the intermediary layer; the metal traces and through holes in the RDL layer connect the voltage supplied by the DC power supply and the ground signal to each module in the power management system, forming the structure of this structure Global PDN: the output voltage of each module in the power management system is transmitted to each Tile in the integrated chip system through the vertical connectors in the interposer, forming a local PDN of each Tile.

Specifically, as shown in FIG. 3 , this example provides a first package structure 101, wherein the integrated chip system is a single integrated chip 105, and the power management system is three power management chips, including the first power management chip 102 , a chip set composed of the second power management chip 103 and the third power management chip 104 . The first power management chip 102 , the second power management chip 103 , and the third power management chip 104 are horizontally arranged on the upper surface of the interposer 109 , and the integrated chip 105 is arranged on the lower surface of the interposer 109 as a power supply load chip. The first power management chip 102, the second power management chip 103, and the third power management chip 104 are respectively connected to the interposer 109 via the first micro-bump 106; 108 is connected to the interposer 109 . FIG. 7 is a top view of the first package structure 101 .

In this example, the integrated chip 105 is set as an isomorphic multi-Tile system, that is, the integrated chip 105 includes three identical tiles. The first power management chip 102, the second power management chip 103, and the third power management chip 104 are modules of the power management system, and the three modules of the power management system in this structure supply the three tiles of the integrated chip respectively. same voltage.

Each power management chip mentioned in the present invention refers to a chip capable of converting a source voltage into a voltage required by a target chip. The main circuit of the power management chip is the DC-DC conversion circuit, among which LDO and DC-DC step-down converter are the most common DC-DC converters. Compared with the DC-DC step-down converter, the LDO can avoid excessive occupation of the area by peripheral components, so the first power management chip 102, the second power management chip 103, and the third power management chip 103 in the first package structure 101 of the example of the present invention The power management chip 104 is exactly a power management chip based on an LDO type circuit.

In a specific embodiment, as shown in FIG. 4 , in the second package structure 201 , the power management system is not a collection of multiple LDO chips, but a single distributed power chip 202 composed of multiple LDO circuits. Each LDO circuit structure in the distributed power supply chip 202 is called a module of the power management system. Similar to the first packaging structure 101 , each module in the power management system supplies the same voltage to each Tile of the integrated chip respectively.

In a specific embodiment, as shown in FIG. 5, in the third package structure 301, the integrated chip system is not a single integrated chip, but a chip set composed of multiple logic chips 302 packaged on the same substrate. . The logic chip 302 is a Tile of the integrated chip system, and the first power management chip 102 , the second power management chip 103 , and the third power management chip 104 in the power management system respectively supply the same voltage to each Tile.

In a specific embodiment, as shown in FIG. 6, in the fourth packaging structure 401, the integrated chip is a chip set composed of multiple logic chips 302 packaged on the same substrate, and the power management system is composed of multiple A single distributed power supply chip 202 composed of LDO circuits. The logic chip 302 is a Tile of the integrated chip system, and each LDO circuit structure in the power chip 202 is each module of the power management system, and each module supplies the same voltage to each Tile.

It should be understood that the present invention does not limit the number of tiles in the integrated chip system and the number of modules in the power management system. If the process can be achieved and the physical constraints and basic functions are satisfied, the integrated chip system in the present invention The number of tiles and the number of modules in the power management system can be any reasonable number greater than one.

The present invention will describe the structure 101 shown in FIG. 3 in detail. In the figure, some pins of the first power management chip 102, the second power management chip 103, and the third power management chip 104 pass through the vertical connection structure 107 in the intermediary layer 109 and the first micro-bump 106 and the second micro-bump 108 It is connected with the integrated chip 105 to form an electrical path for each of the power management chips to supply voltage to each Tile in the integrated chip 105 , that is, the local PDN of this structure.

The power supply from the global power supply to the first power management chip 102, the second power management chip 103, and the third power management chip 104 is completed through the RDL layer 110 in the intermediary layer 109, so the conductive structure in the RDL layer 110 is It is called global PDN.

As shown in FIG. 7, the conductive structure in the RDL layer 110 includes a first wiring structure 111, a second wiring structure 112, a third wiring structure 113 and related conductive vias, wherein the first wiring structure 111, the second wiring structure The second wiring structure 112 and the third wiring structure 113 are respectively connected to power management chips (the first power management chip 102 , the second power management chip 103 , and the third power management chip 104 ). The first wiring structure 111, the second wiring structure 112, and the third wiring structure 113 each include a plurality of metal wirings, and the metal wirings transmit voltage or ground signals from the DC power supply to each of the power chips .

It should be understood that the number and wiring situation of each trace in the figure is only for demonstration, indicating the connection relationship, and does not represent the actual trace.

Above, the first package structure 101 proposed in the example of the present invention provides the PDN for the integrated chip 105 by means of 2.5D interposer technology and RDL technology: each of the first power management chip 102 and the second power management chip 103. After the third power management chip 104 obtains the source voltage signal from the global power supply through the first wiring structure 111, the second wiring structure 112, and the third wiring structure 113 in the RDL layer 110, output the same stable voltage, And the voltage is transmitted to each Tile in the target integrated chip 105 through the vertical connection structure 107 in the interposer 109 .

As shown in FIG. 8 , a detailed schematic diagram of the interposer of the first packaging structure 101 is shown.

In this example, the RDL layer 110 includes two metal layers ML1 and ML2, and an insulating medium is filled between the two metal layers to form an insulating medium layer DL. The metal traces etched on the metal layers ML1 and ML2 constitute the first trace structure 111, the second trace structure 112, and the third trace structure 113, so the metal layer ML1 and the metal layer ML2 can also be referred to as The first wiring layer and the second wiring layer. The vertical connection between the wiring layers is completed by the conductive via 123 in the insulating dielectric layer DL. The top of the second wiring layer ML2 is provided with a plurality of conductive pads 121, and the conductive pads 121 are used to carry the first micro-bumps 106 of each power management chip, and realize the connection between the first micro-bumps 106 and the first micro-bumps 106. The electrical connection of the wiring structure in the second wiring layer ML2. A substrate layer 124 is disposed at the bottom of the second wiring layer ML2 , and the second micro-bump 108 is disposed between the substrate layer 124 and the integrated chip 105 .

As shown in Figures 3, 7 and 8, the wiring structure 111 transmits the voltage and the ground signal provided by the DC power supply to a certain conductive pad 121, and the conductive pad 121 is connected to a certain first micro-bump 106, so The first micro-bump 106 is connected to a power supply pin of the power management chip 102, thus forming a PDN for supplying power to the power management chip 102; The vertical connection structure 107 and the second micro-bump 108 transmit the voltage signal to the integrated chip 105 , thus realizing the PDN for supplying power to the integrated chip 105 . The rest of the power management chips are the same.

It should be understood that the present invention is not limited to the stacked structure of the RDL layers as long as adjacent metal layers are separated by an insulating medium. For example, in some examples, the RDL layer 110 of the present invention may consist of four metal layers and three insulating dielectric layers, as shown in FIG. 9 .

In this embodiment, each of the power management chips is packaged by flip chip (FlipChip) technology, but in some possible embodiments, it may also be packaged by wire bonding or other equivalent technology. At the same time, the interconnection structure between each chip and the interposer is not limited. For example, the first micro-bump 106 and the second micro-bump 108 can be changed to one of copper pillars, solder balls, and controllable collapse chip connection structures. or a combination of several.

In the selection of structural materials, the present invention uses glass substrates, ceramic substrates or similar composite layers as the substrate layer; the RDL layer 110, the constituent materials of the conductive structure include but not limited to copper and gold, and the materials of the insulating medium include but Not limited to polyimide, silica.

The present invention utilizes 2.5D interposer technology and RDL technology to realize the high-density interconnection between the power management system and the integrated chip system, which meets the demand of the integrated chip system for the power supply voltage, and has small packaging volume, high electrical signal The advantage of high transmission quality.

The above description is only to illustrate the implementation of the present invention, and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (10)

1. A power supply structure for an integrated system-on-a-chip, characterized in that it includes a power management system, an interposer and an integrated system-on-a-chip, and the interposer includes a substrate layer, an RDL layer, and a vertical layer that can vertically penetrate through the intermediary layer connection structure, the upper and lower ends of the vertical connection structure are respectively provided with interconnectors, the power management system is connected to the upper end of the vertical connection structure through the interconnectors, and the integrated chip system is connected to the upper end of the vertical connection structure through the interconnection The connecting piece is connected with the lower end of the vertical connection structure. 2. The power supply structure for integrated chip systems according to claim 1, wherein the RDL layer is formed by sequentially laying multiple layers of metal layers and insulating dielectric layers between adjacent metal layers , constituting a typical capacitor structure of "metal-dielectric-metal"; metal traces are arranged on the metal layer, conductive vias are provided in the insulating dielectric layer, and the conductive vias are connected to adjacent metal layers The metal traces of the The substrate layer is arranged under the RDL layer, and is used for carrying the RDL layer and realizing the connection between the RDL layer and the integrated chip system. 3. The power supply structure for an integrated chip system according to claim 1, wherein the circuit performing voltage conversion in the power management system is an LDO circuit, and the LDO circuit can provide a stable voltage output; The power management system is a distributed power management chip composed of multiple LDO circuits, or a chip set composed of multiple distributed power management chips. 4. The power supply structure for an integrated chip system according to claim 2, further comprising a global power supply capable of providing DC power, and the global power supply inputs DC power along the edge of the intermediary layer; The metal traces and the conductive vias in the RDL layer connect the voltage and ground signal supplied by the global power supply to the power management system to form the global PDN of this structure; the output of the power management system The voltages are respectively transmitted to the integrated chip system through the vertical connections in the interposer to form a local PDN. 5. The power supply structure for an integrated chip system according to claim 4, wherein a plurality of conductive pads are arranged on the metal layer on the top of the RDL layer, and the conductive pads are used for Carrying the interconnection element disposed under the power management system and forming an electrical connection. 6. The power supply structure for an integrated chip system according to claim 1, wherein the interconnection is a micro-bump, and the micro-bump is a copper column, a solder ball, a controllable collapse chip One or more combinations of connection structures. 7. A power supply structure oriented to an integrated chip system according to claim 1, characterized in that, the integrated chip system refers to a logic chip with a size greater than 3.3cm×2.6cm, or a plurality of chips packaged in the same A chip assembly composed of the logic chips on the substrate. 8 . The power supply structure for an integrated chip system according to claim 1 , wherein the substrate layer is a glass substrate, or a ceramic substrate, or an insulating composite layer. 9. The power supply structure for an integrated chip system according to claim 1, wherein the metal layer in the RDL layer has at least two layers, and the insulating medium layer has two layers. At least one layer, and the top and bottom of the RDL layer must be the metal layer. 10 . The power supply structure for an integrated chip system according to claim 9 , wherein the material of the insulating medium includes but not limited to polyimide and silicon dioxide. 11 .

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