CN116185498A - Storage and calculation integrated chip, calculation method and device thereof - Google Patents

Abstract

The invention discloses a memory and calculation integrated chip, a calculation method and a calculation device thereof, wherein the chip comprises a RISCV processor, at least one storage array and a calculation module; the RISCV processor comprises a processor core module and a data memory; the processor core module is used for receiving an external instruction, determining whether the external instruction is a RISCV instruction or an expansion instruction, if the external instruction is the expansion instruction, determining weight data and data to be processed according to the external instruction, writing the weight data into the storage array, and sending the data to be processed to the data memory; and the calculation module obtains a calculation result according to the weight data of the storage array and the data to be processed of the data storage. The invention can reduce data transmission and improve calculation efficiency.

Description

Storage and calculation integrated chip, calculation method and device thereof

technical field

The present invention relates to the field of chip technology, in particular to a memory-computing integrated chip, a calculation method and a device thereof.

Background technique

This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section.

In recent years, in order to solve the challenges of device size reduction and the bottleneck of von Neumann computing architecture, storage and computing integration (or also called in-memory computing, memory computing, etc.) technology has attracted widespread attention. The basic idea is to integrate storage and computing. On the same chip, the memory is directly used for calculation, reducing power consumption while improving performance.

The integration of storage and computing technology is currently considered to be one of the efficient hardware solutions for real-time intelligent processing of big data in the post-Moore era, and it is also one of the current efficient implementation solutions for deep learning neural networks. For deep learning neural network applications, the most frequent operation is Multiply Accumulate (MAC for short). The MAC operation can be efficiently realized through the integration of storage and calculation, thereby greatly improving performance while reducing power consumption. When facing complex neural network application scenarios, considering peripheral interaction and computing requirements other than MAC operations, it is often difficult for a single memory-computing integrated chip to meet the design requirements. Therefore, it is necessary to add an additional processor (CPU). The control unit and the calculation module implement complex calculation tasks. At present, the design of external control unit, computing module and integrated memory and calculation chip mostly adopts a discrete form, that is, the CPU and integrated storage and calculation chip only transmit data through the bus, and a large number of data transmission processes limit the calculation efficiency of the neural network system. .

Contents of the invention

An object of the present invention is to provide a memory-computing integrated chip, which reduces data transmission and improves computing efficiency. Another object of the present invention is to provide a calculation method for an integrated storage and calculation chip. Another object of the present invention is to provide a neural network computing device. Another object of the present invention is to provide a computer device. Another object of the present invention is to provide a computer-readable medium.

In order to achieve the above purpose, the present invention discloses a memory-computing integrated chip on the one hand, including a RISCV processor, at least one storage array, and a computing module;

The RISCV processor includes a processor core module and a data memory;

The processor core module is used to receive an external instruction, determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, and write the weight data into the The storage array, sending the data to be processed to the data storage;

The calculation module obtains a calculation result according to the weight data of the storage array and the data to be processed in the data storage.

Preferably, it further includes a local instruction memory, a bus and an external memory;

The processor core module is connected to the external memory through the bus;

The processor core module is further configured to store the external instruction in the local instruction memory after receiving the external instruction.

Preferably, the data storage includes a local data storage module and a storage-computing integrated cache module;

The local data storage module is used for storing calculation data required for processing the RISCV instruction;

The storage-computing integrated cache module is used to store the data to be processed.

Preferably, it further includes a write module and a read module corresponding to the storage array;

The writing module includes a row decoder and a column decoder corresponding to the memory array;

The reading module includes a reading decoder.

Preferably, the calculation module includes an addition tree and an accumulator;

The processor core module is used to determine a bit selection signal according to the external instruction, select one bit of data from the data to be processed in the data memory according to the bit selection signal, and send the one bit of data to the addition tree so that the addition tree multiplies the weight data and the one-bit data to obtain a multiplication result and sends it to the accumulator;

The accumulator is used to add the multiplication results corresponding to all the bit data of the data to be processed to obtain the calculation result.

Preferably, the processor core module includes an instruction fetch module, a decoding module, an execution module, and a memory access and write-back module connected in sequence, and also includes a memory-computing integrated control unit;

The instruction fetching module includes a program counter for obtaining external instructions from the local instruction memory;

The decoding module includes a judging unit and a register file, the judging unit is used to determine whether the external instruction is a RISCV instruction or an extended instruction, and if it is an extended instruction, the external instruction is sent to the integrated storage and calculation control unit, If it is a RISCV instruction, sending the RISCV instruction to the register file;

The execution module is used to execute the RISCV instruction to obtain RISCV calculation data;

The memory access and write-back module includes a memory access unit, which receives and stores the RISCV calculation data, and transmits it to the register file;

The integrated storage and calculation control unit is used to determine the weight data and the data to be processed according to the external instruction, write the weight data into the storage array, send the data to be processed to the data memory, and control the The calculation module obtains the calculation result based on the weight data and the data to be processed.

The present invention also discloses a computing method for a memory-computing integrated chip. The memory-computing integrated chip includes at least one storage array, a computing module, and a data memory;

The methods include:

Receive external instructions;

Determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, write the weight data into the storage array, and send the data to be processed to said data storage;

A calculation result is obtained by the calculation module according to the weight data of the storage array and the data to be processed in the data memory.

The invention also discloses a neural network computing device, which includes the storage-computing integrated chip as described above.

The present invention also discloses a computer device, which includes a memory, a processor, and a computer program stored in the memory and operable on the processor, and the processor implements the above-mentioned method when executing the computer program.

The present invention also discloses a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the above method is realized.

The storage and calculation integrated chip of the present invention includes a RISCV processor, at least one storage array and a calculation module. The RISCV processor includes a processor core module and a data memory. The processor core module is used to receive an external instruction, determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, and write the weight data into the the storage array, and send the data to be processed to the data storage. The calculation module obtains a calculation result according to the weight data of the storage array and the data to be processed in the data storage. Therefore, the present invention integrates the RISCV processor and the integrated function of storage and calculation into one chip, which reduces the data transmission process during data storage and calculation, and improves the efficiency of data calculation.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work. In the attached picture:

Fig. 1 is a schematic diagram of a specific embodiment of an integrated storage and calculation chip of the present invention;

FIG. 2 is a schematic diagram of a RISCV processor of a specific embodiment of an integrated chip for storage and calculation according to the present invention;

Fig. 3 is a schematic diagram of an integrated storage and calculation calculation unit of a specific embodiment of the integrated storage and calculation chip of the present invention;

Fig. 4 is a schematic diagram of a data memory of a specific embodiment of an integrated storage and calculation chip according to the present invention;

Fig. 5 is a schematic diagram of a computing module of a specific embodiment of the integrated storage and computing chip of the present invention;

Fig. 6 is a flow chart of implementing vector multiplication of a specific embodiment of the integrated storage and calculation chip of the present invention;

Fig. 7 is a schematic diagram of a processor core module of a specific embodiment of an integrated storage and calculation chip according to the present invention;

Fig. 8 is a working schematic diagram of a decoding module of a specific embodiment of an integrated storage and calculation chip according to the present invention;

Fig. 9 is a flowchart of a specific embodiment of the calculation method of the integrated storage and calculation chip of the present invention;

10 is a schematic diagram of a specific embodiment of the neural network computing device of the present invention;

FIG. 11 shows a schematic structural diagram of a computer device suitable for implementing an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

It should be noted that, in one or more embodiments of the present application, RISCV is an open source instruction set architecture (ISA) based on the reduced instruction set (RISC) principle.

According to one aspect of the present invention, this embodiment discloses an integrated storage and calculation chip. As shown in FIG. 1 , the chip includes a RISCV processor, at least one storage array, and a computing module.

Wherein, the RISCV processor includes a processor core module and a data memory.

The processor core module is used to receive an external instruction, determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, and write the weight data into the the storage array, and send the data to be processed to the data storage.

The calculation module obtains a calculation result according to the weight data of the storage array and the data to be processed in the data storage.

The storage and calculation integrated chip of the present invention includes a RISCV processor, at least one storage array and a calculation module. The RISCV processor includes a processor core module and a data memory. The processor core module is used to receive an external instruction, determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, and write the weight data into the the storage array, and send the data to be processed to the data storage. The calculation module obtains a calculation result according to the weight data of the storage array and the data to be processed in the data storage. Therefore, after receiving the external instruction, the present invention judges whether the external instruction is a conventional RISCV instruction or an extended instruction, and if it is an extended instruction, then determines the weight data and the data to be processed, sends the weight data to the storage array for storage, and stores the data to be processed Sending to the data memory, the calculation module can obtain the data to be processed from the data memory and perform calculation with the weight data in the storage array to obtain the calculation result. The invention integrates the RISCV processor and the storage and calculation functions into one chip, reduces the data transmission process during data storage and calculation, and improves the data calculation efficiency.

In a preferred embodiment, the chip further includes a local instruction memory, a bus, and an external memory, and the processor core module is connected to the external memory through the bus.

It can be understood that, in order to realize the processing of basic RISCV instructions, the chip needs to be provided with a local instruction memory, a bus and an external memory. The processor core module, local instruction memory, bus, external memory and data memory form a complete RISCV processor, as shown in Figure 2.

Wherein, the local instruction memory can be used to store RISCV instructions and extension instructions to be executed, and the processor core module is further used to store the external instruction into the local instruction memory after receiving the external instruction. The external memory can expand the storage capacity of the chip, and the processor core module exchanges data with the external memory through the bus, and stores part of the data in the external memory to realize the expansion of the chip's storage capacity.

At least one storage array, computing module, and data storage can form a complete storage-computing integrated computing unit to realize the storage-computing integrated function, as shown in Figure 3. Wherein, the storage array is used to store weight data with a high multiplexing rate, and the data to be processed can be temporarily stored in the data memory. Therefore, the calculation module can take out the data to be processed from the data memory, and calculate the weight data and the data to be processed to obtain a calculation result. Among them, it should be noted that the extended instruction is usually a data operation instruction. When multiple data and the same data are calculated separately, the multiplexing rate of the same data is higher than that of other data, and the data with a high multiplexing rate can be used as The weight data is written into the storage array, and multiple data are temporarily stored in the data memory as data to be processed.

In a preferred embodiment, the data storage includes a local data storage module and a storage-computing integrated cache module.

Wherein, the local data storage module is used for storing calculation data required for processing the RISCV instruction. The storage-computing integrated cache module is used to store the data to be processed.

Specifically, it can be understood that, in this preferred embodiment, a part of the storage space in the existing RISCV processor is set as a local data storage module for storing calculation data required by the processor core module to process RISCV instructions. At the same time, another part of the storage space is also set up as an integrated cache module for storage and calculation, which is used to store the pending data of the extended instructions. In a specific example, the data memory is formed by a static random-access memory (Static Random-Access Memory, SRAM) array, and the storage array of the local data storage module and the storage array of the storage-computing integrated cache module are located in the same SRAM array, which can be physically The two are divided on the address. The integrated storage and calculation cache module of the data memory further includes an operational amplifier and a readout circuit to output data to be processed in parallel.

In the prior art, the local data memory is usually separated from the storage-computing integrated input buffer, and data transmission between the two needs to be carried out through the bus. When the demand for data transmission between the two is large, it will undoubtedly increase the additional cost of the system. burden. In this preferred embodiment, as shown in Figure 4, the local data storage module and the storage-computing integrated cache module are integrated into one, which saves the data transmission process and simplifies the RISCV processor and the storage-computing integrated computing unit The data transmission between them not only saves power consumption but also reduces delay.

In a preferred embodiment, the RISCV processor further includes a write module and a read module corresponding to the storage array. The writing module includes a row decoder and a column decoder corresponding to the storage array; the reading module includes a reading decoder.

It can be understood that a memory array generally includes a plurality of memory cells arranged in an array, and the memory cells may include control switches and magnetic tunnel junctions. Wherein, the magnetic tunnel junction can be used to store data, and the control switch can be turned on or off based on an external control command, so as to write or not write data into the magnetic tunnel junction.

In a specific example, after determining the weight data, the processor core module can determine the write address of the storage unit where the weight data is written and the weight data to be written, and then respectively pass the row decoder and the column decoder to the weight Data is written to the storage array.

It can be understood that when the calculation result is obtained according to the weight data of the storage array and the data to be processed in the data memory, a column selection signal can be sent to the storage array through the read decoder to select a column in the storage array, Multiply with one bit of data in the data to be processed and then add to obtain the multiplication result, and add all the multiplication results of the data to be processed to complete the multiplication and accumulation operation.

In a preferred implementation manner, as shown in FIG. 5 , the calculation module includes an addition tree and an accumulator.

Wherein, the processor core module is configured to determine a bit selection signal according to the external instruction, select one bit of data from the data to be processed in the data memory according to the bit selection signal, and send the one bit of data to the The addition tree causes the addition tree to multiply the weight data and the one-bit data to obtain a multiplication result and send it to the accumulator;

The accumulator is used to add the multiplication results corresponding to all the bit data of the data to be processed to obtain the calculation result.

Specifically, it can be understood that, as shown in Figure 6, when performing MAC calculations, the processor core module can send a bit selection signal to the data memory to select one bit of data to be processed, and select the data from the storage array according to the column selection signal A column of data is selected and input into the addition tree in parallel, and bit data included in all the data to be processed in the data memory is input in parallel into the addition tree according to the bit selection signal, and the two are multiplied in the addition tree and added in parallel. The accumulator accumulates the calculation results of multiple cycles to obtain the calculation results. The above process realizes vector multiplication, and the vector multiplication can be extended to vector matrix multiplication through parallel processing of multiple vector multiplications.

In a preferred embodiment, as shown in FIG. 7 , the processor core module includes an instruction fetch module, a decoding module, an execution module, and a memory access and write-back module connected in sequence, and also includes a memory-computing integrated control unit.

Wherein, the instruction fetching module includes a program counter for obtaining external instructions from the local instruction memory.

The decoding module includes a judging unit and a register file, the judging unit is used to determine whether the external instruction is a RISCV instruction or an extended instruction, and if it is an extended instruction, the external instruction is sent to the integrated storage and calculation control unit, The storage-computing integrated control unit determines the weight data and the data to be processed according to the external instruction, writes the weight data into the storage array, sends the data to be processed to the data memory, and controls the calculation module according to the The calculation result is obtained from the weight data of the storage array and the data to be processed in the data memory; if it is a RISCV instruction, the RISCV instruction is sent to the register file, as shown in FIG. 8 .

The execution module is used to execute the RISCV instruction to obtain RISCV calculation data.

The memory access and write-back module includes a memory access unit, which receives and stores the RISCV calculation data, and transmits it to the register file.

Specifically, after importing the external instruction into the local instruction memory, the processor core module can read the external instruction and send it into the pipeline. The traditional five-stage pipeline includes value fetching, decoding, execution, memory access, and write-back, which are respectively implemented by an instruction fetch module, a decode module, an execution module, and a memory access and write-back module. On this basis, this embodiment improves the pipeline and adds a judging unit in the decoding module. When the extended instruction is read, the judgment unit sends the instruction to the integrated storage and calculation control unit, and the integrated storage and calculation control unit completes the control of the integrated storage and calculation; when the RISCV instruction is read, continue to execute the above Five-stage pipeline to execute instruction functions.

Based on the same principle, an embodiment of the present invention also provides a calculation method for an integrated storage and calculation chip. The integrated storage and calculation chip includes at least one storage array, computing module and data memory;

As shown in Figure 9, the method includes:

S100: Receive an external command.

S200: Determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, write the weight data into the storage array, and write the data to be processed sent to the data store.

S300: Obtain a calculation result by the calculation module according to the weight data of the storage array and the data to be processed in the data memory.

Since the problem-solving principle of this chip is similar to the above method, the implementation of this chip can refer to the implementation of the method, and will not be repeated here.

Based on the same principle, an embodiment of the present invention also provides a neural network computing device. The neural network computing device includes the storage-computing integrated chip of this embodiment.

Specifically, in the field of neural network computing, the memory-computing integrated computing function of the memory-computing integrated chip can complete the MAC operations required for the fully connected layer and the convolutional layer, and the RISCV processor completes operations such as activation and pooling. There is no need for additional data transmission between layers. Here, the calculation of the fully connected layer is taken as an example. As shown in Figure 10, the input data to be processed is stored in the local data storage module, and the weight data is stored in the storage-computing integrated storage array. The two complete the MAC calculation through the storage array and the computing module in the storage-computing integrated chip, and the calculation results Returns to the local datastore module for the datastore. The processor core module fetches calculation results from the local data memory and executes the activation function to complete the complete fully connected layer calculation. Since the calculation results are directly stored in the local data storage, the next layer of calculations can be read directly, reducing the need for data transmission.

Since the problem-solving principle of the device is similar to that of the chip above, the implementation of the device can refer to the implementation of the chip, and will not be repeated here.

An embodiment of the present invention also provides a computer device, including a memory, a processor, and a computer program stored on the memory and operable on the processor, and the above method is implemented when the processor executes the computer program.

An embodiment of the present invention also provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the foregoing method is implemented.

Those skilled in the art should understand that the embodiments of the present invention may provide the systems, devices, modules or units described in the above embodiments as methods, systems, or computer programs, and specifically may be implemented by computer chips or entities, or by A product with a certain function to achieve. A typical implementing device is a computer device. Specifically, the computer device can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, Game consoles, tablets, wearables, or a combination of any of these devices.

In a typical example, the computer device specifically includes a memory, a processor, and a computer program stored on the memory and operable on the processor. When the processor executes the program, the above-mentioned method executed by the client is implemented. Or, when the processor executes the program, the above-mentioned method executed by the server is implemented.

Referring now to FIG. 11 , it shows a schematic structural diagram of a computer device 600 suitable for implementing the embodiment of the present application.

As shown in FIG. 11 , a computer device 600 includes a central processing unit (CPU) 601 that can be programmed according to a program stored in a read-only memory (ROM) 602 or loaded from a storage section 608 into a random-access memory (RAM) 603 program to perform various appropriate tasks and processes. In RAM603, various programs and data required for the operation of the system 600 are also stored. The CPU 601 , ROM 602 , and RAM 603 are connected to each other via a bus 604 . An input/output (I/O) interface 605 is also connected to the bus 604 .

The following components are connected to the I/O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal feedback device (LCD), etc., and a speaker; a storage section including a hard disk, etc. 608; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I/O interface 606 as needed. A removable medium 611 such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc. is mounted on the drive 610 as necessary so that a computer program read therefrom is installed as the storage section 608 as necessary.

In particular, according to an embodiment of the present invention, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program comprising program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via communication portion 609 and/or installed from removable media 611 .

Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can be implemented by any method or technology for storage of information. Information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory or other memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridge, tape magnetic disk storage or other magnetic storage device or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media excludes transitory computer-readable media, such as modulated data signals and carrier waves.

For the convenience of description, when describing the above devices, functions are divided into various units and described separately. Of course, when implementing the present application, the functions of each unit can be implemented in one or more pieces of software and/or hardware.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

It should also be noted that the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes Other elements not expressly listed, or elements inherent in the process, method, commodity, or apparatus are also included. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems or computer program products. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

This application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including storage devices.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment.

The above descriptions are only examples of the present application, and are not intended to limit the present application. For those skilled in the art, various modifications and changes may occur in this application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims (10)

1. A memory-computing integrated chip, characterized in that it includes a RISCV processor, at least one storage array and a computing module; The RISCV processor includes a processor core module and a data memory; The processor core module is used to receive an external instruction, determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, and write the weight data into the The storage array, sending the data to be processed to the data storage; The calculation module obtains a calculation result according to the weight data of the storage array and the data to be processed in the data storage. 2. The integrated storage and calculation chip according to claim 1, further comprising a local instruction memory, a bus and an external memory; The processor core module is connected to the external memory through the bus; The processor core module is further configured to store the external instruction in the local instruction memory after receiving the external instruction. 3. The storage-computing integrated chip according to claim 1, wherein the data memory includes a local data storage module and a storage-computing integrated cache module; The local data storage module is used for storing calculation data required for processing the RISCV instruction; The storage-computing integrated cache module is used to store the data to be processed. 4. The integrated storage and calculation chip according to claim 1, further comprising a write module and a read module corresponding to the storage array; The writing module includes a row decoder and a column decoder corresponding to the storage array; The reading module includes a reading decoder. 5. The storage and calculation integrated chip according to claim 1, wherein the calculation module comprises an addition tree and an accumulator; The processor core module is used to determine a bit selection signal according to the external instruction, select one bit of data from the data to be processed in the data memory according to the bit selection signal, and send the one bit of data to the addition tree so that the addition tree multiplies the weight data and the one-bit data to obtain a multiplication result and sends it to the accumulator; The accumulator is used to add the multiplication results corresponding to all the bit data of the data to be processed to obtain the calculation result. 6. The memory-computing integrated chip according to claim 1, wherein the processor core module includes an instruction fetch module, a decoding module, an execution module, and a memory access and write-back module connected in sequence, and also includes a memory-computing integrated chip control unit; The instruction fetching module includes a program counter for obtaining external instructions from the local instruction memory; The decoding module includes a judging unit and a register file, the judging unit is used to determine whether the external instruction is a RISCV instruction or an extended instruction, and if it is an extended instruction, the external instruction is sent to the integrated storage and calculation control unit, If it is a RISCV instruction, sending the RISCV instruction to the register file; The execution module is used to execute the RISCV instruction to obtain RISCV calculation data; The memory access and write-back module includes a memory access unit, which receives and stores the RISCV calculation data, and transmits it to the register file; The integrated storage and calculation control unit is used to determine the weight data and the data to be processed according to the external instruction, write the weight data into the storage array, send the data to be processed to the data memory, and control the The calculation module obtains the calculation result based on the weight data and the data to be processed. 7. A calculation method for an integrated storage and calculation chip, characterized in that, the integrated storage and calculation chip includes at least one storage array, a computing module, and a data memory; The methods include: Receive external instructions; Determine whether the external instruction is a RISCV instruction or an extended instruction, if it is an extended instruction, determine weight data and data to be processed according to the external instruction, write the weight data into the storage array, and send the data to be processed to said data storage; A calculation result is obtained by the calculation module according to the weight data of the storage array and the data to be processed in the data memory. 8. A neural network computing device, characterized in that it comprises the memory-computing integrated chip according to any one of claims 1-6. 9. A computer device, comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein the method according to claim 7 is implemented when the processor executes the computer program. 10. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to claim 7 is implemented.

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