CN116156872A - Memory array structure with contact enhancement side wall spacer and preparation method thereof - Google Patents

Abstract

The present disclosure provides a DRAM array structure with contact enhanced sidewall spacers and a method of fabricating the same. The memory array structure includes a semiconductor substrate, an isolation structure and a contact enhancing sidewall spacer. The semiconductor substrate has a trench defining a laterally separated active region, and the active region is formed by a surface area of the semiconductor substrate. A top surface of a first set of active regions is recessed relative to a top surface of a second set of active regions. The isolation structure fills in the trench and laterally contacts a bottom portion of the active region. The contact enhancement sidewall spacers laterally surround a top portion of the active region, respectively.

Description

Memory array structure with contact-enhanced sidewall spacers and fabrication method thereof

cross reference

This application claims priority to and the benefit of U.S. Patent Application Nos. 17/528,490 and 17/528,799 (priority date "November 17, 2021"), the contents of which are incorporated by reference in their entirety way incorporated into this article.

technical field

The disclosure provides a memory array structure and a manufacturing method thereof, in particular to a dynamic random access memory (DRAM) array with contact-enhanced sidewall spacers and a manufacturing method thereof.

Background technique

In recent decades, as electronics have continued to improve, so has the need for storage capacity. In order to increase the storage capacity of a memory element (eg, a DRAM element), more memory cells are arranged in the memory element, and the size of each memory cell in the memory element becomes smaller. The memory cells are respectively fabricated on an active area, which may be a part of the semiconductor substrate. Scaling of the active area is an option to reduce the size of each memory cell.

Each DRAM cell may include a storage capacitor disposed on the active area and connected to the active area through a capacitor contact. A reduction in the active area may lead to a reduction in the landing area for the capacitor contacts. Therefore, the contact resistance between the capacitor contacts and the active region may increase due to semiconductor lithography overlay issues. In other words, pursuing high storage density by minimizing the active area may compromise the performance of DRAM components. There is a need in the art for a method of increasing the landing area of a capacitor contact without enlarging the layout pattern of the active area.

The above "prior art" description only provides background technology, does not acknowledge that the above "prior art" description discloses the subject matter of the present disclosure, does not set the prior art of the present disclosure, and the above "prior art" Any description should not be taken as any part of this disclosure.

Contents of the invention

In an embodiment of the present disclosure, a memory array structure is provided, including: a semiconductor substrate, a trench defining an active region laterally separated by a surface region of the semiconductor substrate, wherein a first active region of the active region A top surface of the group of active regions is recessed relative to a top surface of a second group of active regions; an isolation structure is filled in the trench and is in lateral contact with a bottom portion of the active region; and a contact-enhancing sidewall The spacers respectively laterally surround a top of the active area.

In one embodiment of the present disclosure, a memory array structure is provided, including: an active area formed by a laterally separated surface portion of a semiconductor substrate, wherein a top surface of a first group of active areas is opposite to a A top surface of the second group of active regions is recessed; an isolation structure extends between the active regions and is in contact with a bottom portion of the active regions; and a contact-enhancing capping layer covers a top of the active regions, respectively. .

In yet another embodiment of the present disclosure, a method for fabricating a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines an active laterally separated by a surface region of the semiconductor substrate. region; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active region; recessing a first group of active regions from a top surface of the first group of active regions and covering a top surface of a second group of active regions at the same time; and forming a contact-enhancing sidewall spacer to laterally surround a top of the active region.

The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the following detailed description of the disclosure can be better understood. Other technical features and advantages that set the subject of the disclosed claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure defined by the disclosed claims.

Description of drawings

A more complete understanding of the disclosure of the present disclosure can be obtained when considering the accompanying drawings with reference to the embodiments and the disclosed claims, in which like reference numbers refer to like elements.

FIG. 1A is a circuit diagram illustrating memory cells in a memory array structure of some embodiments of the present disclosure.

FIG. 1B is a structural diagram illustrating a memory array structure including a plurality of memory cells according to some embodiments of the present disclosure.

Figure 2A is a plan view illustrating a partial layout of a memory array of some embodiments of the present disclosure.

2B is a cross-sectional view illustrating edge portions of two adjacent active areas and a portion of an isolation structure extending between the adjacent active areas of some embodiments of the present disclosure.

Figure 3 is a flow diagram illustrating a method of making the structure shown in Figure 2B of some embodiments of the present disclosure.

4A to 4K are plan views illustrating structures in intermediate stages of the manufacturing method shown in FIG. 3 of some embodiments of the present disclosure.

5A to 5K are cross-sectional views illustrating structures in intermediate stages of the manufacturing method shown in FIG. 3 of some embodiments of the present disclosure.

6 is a cross-sectional view illustrating edge portions of two adjacent active regions and a portion of an isolation structure extending between the adjacent active regions of some other embodiments of the present disclosure.

Explanation of reference signs:

10: Memory array structure

100: storage cell

200: Semiconductor substrate

202: Isolation structure

204: Contact Enhanced Sidewall Spacers

204-1: Contact Enhanced Sidewall Spacers

204-2: Contact Enhanced Sidewall Spacers

206: Self-Assembled Monolayer (SAM)

206-1: Self-Assembled Monolayers

206-2: Self-Assembled Monolayers

300: first insulating layer

302: second insulating layer

304: mask layer

304a: Stripe pattern

304b: island pattern

306: mask layer

604: Contact Enhanced Cover

604-1: Contact Enhanced Cover

604-2: Contact Enhanced Cover

604a: Contact enhancement layer

604b: Contact Enhanced Sidewall Spacers

AA: active area

AA': initial active area

A-A': line

AA1: Active Area

AA2: Active Area

AT: access transistor

BB': line

BL: bit line

CC: capacitor contact

CC1: Capacitor contact

CC2: Capacitor contact

D1: Direction

D2: direction

H1: Height

H2: Height

H202: Height

H204-1: Height

H204-2: Height

H604-1: Height

H604-2: Height

S11: Step

S13: Step

S15: step

S17: step

S19: Step

S21: Step

S23: Step

S25: Step

S27: Step

S29: Step

S31: Step

S33: step

SC: storage capacitor

SW1: side wall

SW2: side wall

TR: Groove

TR': initial trench

TS1: top surface

TS2: top surface

TS202: top surface

WL: word line

Detailed ways

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the dimensions of an element are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired properties of the element. In addition, in the following description, a first feature is formed "over" a second feature or "on" a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which the first feature An embodiment in which an additional feature may be formed between a feature and a second feature such that the first feature may not be in direct contact with the second feature. For simplicity and clarity, some features may be arbitrarily drawn at different scales. In the drawings, some layers/features may be omitted for simplicity.

In addition, for ease of description, for example, "beneath", "below", "lower", "above", "upper" and the like may be used herein Spatially relative terms are used to describe the relationship of one element or feature to another (other) element or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The described elements may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may also be translated accordingly.

FIG. 1A is a circuit diagram illustrating a memory cell 100 in a memory array structure according to some embodiments of the present disclosure. Referring to FIG. 1A, the memory array structure may be a dynamic random access memory (DRAM) array structure. Each memory cell 100 in the memory array structure may include an access transistor AT and a storage capacitor SC. The access transistor AT may be a field effect transistor (FET). One terminal of storage capacitor SC is coupled to the source and/or drain terminal of access transistor AT, while the other terminal of storage capacitor SC may be coupled to a reference voltage (eg, ground as depicted in FIG. 1A ). When the access transistor AT is turned on, the storage capacitor SC can be accessed. On the other hand, when the access transistor AT is in an off state, the storage capacitor SC cannot be accessed.

During a write operation, the access transistor AT is turned on by establishing that the word line WL is coupled to a gate terminal of the access transistor AT, and a voltage applied to the bit line BL (with one of the The voltage on the source and/or drain terminal coupled) can be transferred to the storage capacitor SC (coupled to the other source and/or drain terminal of the access transistor AT). Accordingly, the storage capacitor SC may be charged or discharged, and a logic state "1" or a logic state "0" may be stored in the storage capacitor SC. During a read operation, the access transistor AT is also turned on, and the pre-charged bit line BL can be pulled high or low according to the state of charge of the storage capacitor SC. By comparing the voltage of the bit line BL with the precharge voltage, the charge state of the storage capacitor SC can be sensed, and the logic state of the memory cell 100 can be recognized.

FIG. 1B is a structural diagram illustrating a memory array structure 10 including a plurality of memory cells 100 according to some embodiments of the present disclosure. Referring to FIG. 1B , the memory array structure 10 has columns (rows) and rows (columns). The memory cells 100 of each column may be arranged along a first direction, and the memory cells 100 of each row may be arranged along a second direction intersecting with the first direction. A plurality of bit lines BL may be respectively coupled to a column of memory cells 100 . On the other hand, a plurality of word lines WL may be respectively coupled to one row of the memory cells 100 . In some embodiments, during a write operation, the word line WL coupled to the selected memory cell 100 is established, and by providing a voltage to the bit line coupled to the selected memory cell 100, the selected The storage capacitor SC in the memory cell 100 is programmed. In addition, during the read operation, all the bit lines BL are precharged, and the word line WL coupled to the selected memory cell 100 is established, and then also through the storage capacitors coupled to the established word line WL, respectively. SC to pull the precharged bit line BL high or low. By detecting the voltage change of the bit line BL coupled to the selected memory cell 100, the logic state of the selected memory cell 100 can be identified. As a result of pulling high and/or low the precharge bit line BL, the stored charge in the storage capacitor SC of the memory cell 100 coupled to the asserted word line WL is changed. In order to restore the logic state of these memory cells 100 , a write operation may be performed after the read operation, so as to program the previous logic state to these memory cells 100 , and this write operation may also be called a refresh operation.

FIG. 2A is a plan view illustrating a partial layout of a memory array structure 10 of some embodiments of the present disclosure.

Referring to FIGS. 1B and 2A , the memory array structure 10 may be built on a semiconductor substrate 200 . The semiconductor substrate 200 may be, for example, a semiconductor wafer (wafer) or a semiconductor-on-insulator (SOI) wafer. The semiconductor substrate 200 has surface portions laterally separated from each other, referred to as active areas (active areas) AA. The isolation structure 202 extending in the semiconductor substrate 200 may laterally surround each active area AA to physically and electrically isolate the active areas AA from each other. In other words, the active area AA is defined by the isolation structure 202 .

According to some embodiments, the active areas AA may be arranged in an array having a plurality of rows and columns. The word lines WL may be formed in the semiconductor substrate 200, and each word line penetrates a row of the active area AA laterally. On the other hand, the bit lines BL may be formed on the semiconductor substrate 200 and each intersect with a column of the active area AA.

The access transistor AT in each memory cell 100 of the memory array structure 10 is defined near the intersection of the active area AA with the word line WL passing through and the bit line BL intersecting. The word line WL serves as the gate terminal of the access transistor AT, and the portions of the active area AA on opposite sides of the word line WL serve as the source/drain terminal of the access transistor AT. Bit line BL is coupled to one of the source and/or drain terminals. In addition, another source and/or drain terminal may be coupled with one of the storage capacitors SC formed over the semiconductor substrate 200 . It should be understood that depicting the storage capacitor SC as a separate pattern represents a separate bottom electrode of the storage capacitor SC. Although not shown, the storage capacitors SC may actually have a common top electrode.

In some embodiments, the word lines WL extend along a first direction. In addition, the bit line BL can extend along a second direction substantially perpendicular to the first direction. Optionally, each bit line BL may form a curve along its extending direction (eg, the second direction). In addition, the active areas AA may each extend along a third direction intersecting the first direction and the second direction.

In some embodiments, each active area AA is shared by two access transistors AT with a common source and/or drain terminal. In these embodiments, each active area AA is penetrated by two word lines WL and intersects with one of the bit lines BL. In addition, each active area AA may overlap two storage capacitors SC. The bit line BL overlaps and is electrically connected to a part of the active area AA straddling between the two word lines WL, and this part of the active area AA can be used as a common source/source of the two access transistors AT. or drain terminal. Other parts of the active area AA located on opposite sides of the two word lines WL can serve as separate source and/or drain terminals of the two access transistors AT, and can overlap and electrically connect to the two overlying storage capacitors SC respectively. sexual connection.

2B is a cross-sectional view illustrating edge portions of two adjacent active areas AA and a portion of an isolation structure 202 extending between adjacent active areas AA of some embodiments of the present disclosure.

Referring to FIG. 2B , an isolation structure 202 is formed in a trench TR of a semiconductor substrate 200 extending from a top surface of the semiconductor substrate 200 into the semiconductor substrate 200 and laterally separating the active area AA. In addition, some active areas AA may be recessed relative to other active areas AA, and the top surface of the semiconductor substrate 200 in some areas of those recessed active areas AA may be lower than other areas of the non-recessed active areas AA. . As illustrated in FIG. 2B , one of the active areas AA (also referred to as active area AA1 ) is recessed relative to an adjacent active area AA (also referred to as active area AA2 ). Therefore, the height H1 of the active area AA1 (measured from the depth level with the bottom end of the isolation structure 202 to the top surface TS1 of the active area AA1) is smaller than the height H2 of the active area AA2 (measured from the depth level with the bottom end of the isolation structure 202). The depth is measured to the top surface TS2) of the active area AA2).

Since the active areas AA1, AA2 have different heights, the trench TR extending between the active areas AA1, AA2 may have an asymmetric shape. As illustrated in FIG. 2B , where the active area AA1 is recessed relative to the active area AA2, the sidewalls SW1 of the trench TR defining the boundary of the active area AA1 may be lower than the sidewalls of the trench TR defining the boundary of the active area AA2. SW2. The heights of the side walls SW1, SW2 are substantially equal to the heights of H1, H2, respectively. To avoid redundancy, the ratios and ranges of heights H1, H2 are not repeated.

According to some embodiments, the top surface _TS202 of the isolation structure 202 filled in the trench TR is lower than the top surface TS1 of the active area AA1 and lower than the top surface TS2 of the active area AA2. In these embodiments, the height H ₂₀₂ of the isolation structure 202 (measured from the bottom of the isolation structure 202 to the top surface TS 202 of the isolation structure ₂₀₂ ) is less than the height H1 of the active area AA1 and less than the height H2 of the active area AA2 . Since the isolation structure 202 will not fill up the trench TR, the tops of the sidewalls SW1 , SW2 of the trench TR will not be covered by the isolation structure 202 . Since sidewall SW2 is taller than sidewall SW1 , the top of sidewall SW2 spanning over isolation structure 202 may be larger (higher) than the top of sidewall SW1 spanning over isolation structure 202 .

In some embodiments, the top of each active area AA is laterally surrounded by contact enhancing sidewall spacers 204 , while the rest of each active area AA is laterally surrounded by isolation structures 202 . The contact-enhancing sidewall spacers 204 are semiconducting or conducting, and can serve as an additional part of the active area AA. By having such an extra portion, the active area AA can provide a larger landing area for the capacitor contact CC connecting the active area AA and the upper storage capacitor SC, as shown in FIG. 2A . Therefore, the tolerance for setting tolerances of the capacitor contacts CC can be increased and a good electrical contact between the capacitor contacts CC and the active area AA can be ensured. For example, the contact-enhanced sidewall spacers 204 include silicon fabricated using an epitaxy process.

Since the protruding degree of the active area AA1 relative to the isolation structure 202 is smaller than that of the active area AA2, the height H _204-1 of the contact-enhancing sidewall spacer 204-1 laterally surrounding the top of the active area AA1 may be shorter than that of the top laterally surrounding the active area AA2. The height H _204-2 of the contact enhancing sidewall spacer 204-2. The height _{H 204 - 1} is measured from the bottom end of the contact enhanced sidewall spacer 204 - 1 , which may be flush with the top surface TS ₂₀₂ of the isolation structure 202 , to the top end of the contact enhanced sidewall spacer 204 - 1 . Likewise, the height H _{204 - 2} is measured from the bottom end of the contact enhanced sidewall spacer 204 - 2 , which may be flush with the top surface TS ₂₀₂ of the isolation structure 202 , to the top end of the contact enhanced sidewall spacer 204 - 2 . Since the contact-enhanced sidewall spacers 204-1, 204-2 extend to different heights from the top surface TS ₂₀₂ of the isolation structure 202, the top angles of the contact-enhanced sidewall spacers 204-1, 204-2 may have a considerable Lateral thicknesses (not shown), may be spaced vertically. Therefore, the contact-enhancing sidewall spacers 204-1, 204-2 can be prevented from merging, especially when the width of the trench TR between the active regions AA1, AA2 is more reduced. Accordingly, interference between memory cells 100 formed on adjacent active areas AA can be avoided.

In some embodiments, the top surface of each active area AA is covered by a self-assembly monolayer (SAM) 206 . The self-assembled monolayer 206 may be selectively formed on the top surface of each active area AA, and may not extend to the sidewall of each active area AA. That is, the top of the sidewall of each active area AA spanning above the isolation structure 202 will not be covered by the SAM 206 . Accordingly, the contact-enhancing sidewall spacers 204 formed after the SAM 206 may be disposed on top of the sidewalls of the active area AA. According to some embodiments, the contact enhancing sidewall spacers 204 may also extend to the sidewalls of the SAM 206 . In these embodiments, the top ends of the contact enhancing sidewall spacers 204 may be substantially flush with the top surface of the SAM 206 .

Since the active area AA1 is concave relative to the active area AA2 , the top surface TS1 of the active area AA1 is lower than the top surface TS2 of the active area AA2 . Therefore, the SAM 206 (also referred to as SAM 206 - 1 ) covering the top surface TS1 of the active area AA1 is lower than the SAM 206 (also referred to as SAM 206 - 2 ) covering the top surface TS2 of the active area AA2 .

Self-assembled monolayers (SAMs) are well known techniques in the art. For example, see "Reactive Monolayers in Directed Additive Manufacturing-Area Selective Atomic Layer Deposition" Rudy J. Wojtecki et al., Journal of Photopolymer Science and Technology, 2018 Volume 31 Issue 3 Pages 431-436, which is hereby incorporated by reference. In some embodiments, SAMs 206 include organic molecules. According to some embodiments, SAMs 206 include a plurality of molecules having a chemical formula selected from X-R1-SH, X-R1-SS-R2-Y, R1-S-R2, and combinations thereof, wherein R1 and R2 are independent carbon chains Or a carbon chain interrupted by at least one heteroatom, where H is hydrogen, where S is sulfur, and where X and Y are chemical groups that are substantially non-chemically reactive with the copper surface. In some embodiments, at least one of R1 and R2 is a chain of n carbon atoms, where n is an integer from 1 to 30. In some embodiments, the chemical formula of SAMs206 is SH(CH ₂ ) ₉ CH ₃ .

In some embodiments, the SAM is fabricated by self-assembled monolayers of polymerizable compounds. The thickness of the monolayer corresponds to the length of one molecule of the compound in the close-packed structure of the monolayer. The close-packed structure is assisted by functional groups of the compound that bind to surface groups of the substrate through electrostatic interactions and/or one or more covalent bonds. The portion of the compound that binds to the surface of the substrate is referred to herein as the "head" of the compound. The rest of the compound is called the "tail". The tail extends from the head of the compound to the atmosphere interface on the top surface of the SAM. The tail has a non-polar peripheral end group at the atmosphere interface. Therefore, a good SAM has few defects in its close-packed structure and can display high contact angles.

The head of the SAM-forming compound can be selectively bound to a portion of the top surface of a substrate that includes regions of different composition, leaving other portions of the top surface of the substrate free or substantially free of the SAM-forming compound disposed thereon. In this case, the patterned nascent SAM can be formed in one step by dipping the substrate into a given solution of SAM-forming compound in a suitable solvent. In some embodiments, the ultraviolet radiation may have a wavelength from about 4 nanometers (nm) to 450 nanometers. Deep ultraviolet (DUV) radiation can have a wavelength from 124 nanometers to 300 nanometers. The wavelength of extreme ultraviolet (EUV) radiation can range from about 4 nanometers to less than 124 nanometers.

In those embodiments where each active area AA is covered by a SAM 206, a capacitor contact CC disposed on the active area AA may penetrate the SAM 206 to establish electrical contact with the active area AA. Likewise, other contacts (eg, bit line contacts (not shown)) may pass through SAM 206 to reach active area AA. Furthermore, in some embodiments, the capacitor contact CC extending to the lower active area AA may be higher than the capacitor contact CC extending to the upper active area AA. As illustrated in FIG. 2B , capacitive contact CC (also referred to as capacitive contact CC1 ) extending to active area AA1 may be taller than capacitive contact CC (also referred to as capacitive contact CC2 ) extending to active area AA2 .

As mentioned above, the active area AA of the memory cell 100 in the memory array structure 10 has additional portions (ie, contact enhancing sidewall spacers 204 ) at its corners. By having these additional portions, active area AA can provide a larger landing area for capacitor contact CC standing on active area AA. Therefore, the electrical contact between the capacitor contact CC and the active area AA may be less affected by process variations (eg, lithographic overlay issues) in which the capacitor contact CC is disposed. In other words, the electrical contact between the capacitor contact CC and the active area AA can be improved. In addition, adjacent active areas AA are designed to have different heights, and the top surface of one active area AA may be concave relative to the top surface of the adjacent active area AA. Therefore, additional portions adjacent to the active area AA, ie, portions formed at the corners of the active area AA, may also be spaced apart in the vertical direction. Accordingly, adjacent active areas AA may be prevented from merging together, and thus interference between memory cells 100 formed on adjacent active areas AA may be avoided.

Figure 3 is a flow diagram illustrating a method of making the structure shown in Figure 2B of some embodiments of the present disclosure. 4A to 4K are plan views illustrating structures in intermediate stages of the manufacturing method shown in FIG. 3 of some embodiments of the present disclosure. 5A to 5K are cross-sectional views illustrating structures in intermediate stages of the manufacturing method shown in FIG. 3 of some embodiments of the present disclosure. In particular, FIG. 5B is a cross-sectional view illustrating the structure taken along the AA' line shown in FIG. 4B, and FIGS. 5C to 5K are cross-sectional views illustrating the structure taken along the BB' line shown in FIGS. 4C to 4K .

Referring to FIG. 3 , FIG. 4A and FIG. 5A , step S11 is performed, and a first insulating layer 300 , a second insulating layer 302 and a mask layer 304 are sequentially formed on the semiconductor substrate 200 . According to some embodiments, the fabrication technology of the first insulating layer 300 is silicon oxide, and the fabrication technique of the second insulating layer 302 is silicon nitride. In these embodiments, the fabrication technique of the first insulating layer 300 may be a thermal oxidation process or a deposition process (for example, a chemical vapor deposition (CVD) process), and the fabrication technique of the second insulating layer 302 may be a deposition process (for example, CVD process). Additionally, in some embodiments, the mask layer 304 is a photoresist layer and may be coated on the semiconductor substrate 200 . In another embodiment, the mask layer 304 is a hard mask layer, which can be fabricated by a deposition process (such as a CVD process).

Referring to FIG. 3 , FIG. 4B and FIG. 5B , step S13 is performed, and the mask layer 304 is patterned to form a stripe pattern 304 a. The stripe pattern 304a may extend along a direction D1, and the direction D1 may be consistent with the extending direction of each row of active regions AA shown in FIG. 2A. By partially removing the mask layer 304 to form the stripe pattern 304a, portions of the second insulating layer 302 between the stripes 304a may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the mask layer 304 into the stripe pattern 304a may include a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the mask layer 304 into the stripe pattern 304a may include a photolithography process and an etching process.

Referring to FIG. 3 , FIG. 4C and FIG. 5C , step S15 is performed, and the stripe pattern 304 a is also patterned to form an array of island-shaped patterns 304 b. The island patterns 304b of each row may be arranged along a direction D1, while the island patterns 304b of each row may be arranged along a direction D2 intersecting with the direction D1. The island pattern 304b will serve as a shadow mask when forming the initial trench TR′ in subsequent steps. The island patterns 304b of each column are part of the same stripe pattern 304a and may be laterally spaced apart from each other along the direction D1. By partially removing the stripe patterns 304a to form the island patterns 304b, portions of the second insulating layer 302 between the island patterns 304b may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the stripe pattern 304 a into the island pattern 304 b includes a photolithography process and an etching process.

As mentioned above, in some embodiments, two patterning steps are used to form the island pattern 304b. In another embodiment, a single patterning process may be used to pattern the mask layer 304 shown in FIGS. 4A and 5A into the island pattern 304b shown in FIGS. 4C and 5C .

Referring to FIG. 3 , FIG. 4D and FIG. 5D , step S17 is performed, and an initial trench TR′ is formed in the semiconductor substrate 200 . The initial trench TR′ may penetrate a portion of the first and second insulating layers 300 , 302 , span between the island patterns 304 b , and also extend into the semiconductor substrate 200 . By forming the initial trench TR', surface portions of the semiconductor substrate 200 are laterally separated from each other, and are referred to as an initial active area AA'. Top surfaces of the initial active area AA' may be substantially coplanar with each other. According to some embodiments, an etching process is used to form the initial trench TR'. In the etching process, the island pattern 304b can be used as a shadow mask. In addition, after the etching process, the island pattern 304b can be removed, and the underlying second insulating layer 302 can be exposed.

Referring to FIG. 3 , FIG. 4E and FIG. 5E , step S19 is performed to remove the first and second insulating layers 300 , 302 . Therefore, the top surface of the initial active area AA' may be exposed. In some embodiments, the method of removing the first and second insulating layers 300, 302 includes an etching process.

Referring to FIG. 3 , FIG. 4F and FIG. 5F , step S21 is performed to form an isolation structure 202 in the initial trench TR′. In some embodiments, the method of fabricating the isolation structure 202 includes providing an insulating material on the structure as shown in FIGS. 4E and 5E . The insulating material may fill up the initial trench TR' and cover the top surface of the initial active area AA'. Subsequently, a portion of the insulating material spanning the top surface of the active area AA may be removed by a planarization process, such as a polishing process and an etching process, or a combination thereof. In addition, a portion of the insulating material filled in the preliminary trench TR′ may be recessed relative to the top surface of the preliminary active region AA′, and the remaining insulating material may form the isolation structure 202 . For example, the recessing method of the portion of the insulating material in the initial trench TR′ may include an etching process.

Referring to FIG. 3 , FIG. 4G and FIG. 5G , step S23 is performed to selectively form a mask layer 306 on some initial active areas AA'. Therefore, as shown in FIG. 5G, one of the adjacent initial active areas AA' is covered by the mask layer 306, while the other can remain exposed. According to some embodiments, the initial active areas AA' of each column cover alternately along the column direction (eg, direction D1 ). In these embodiments, the mask layer 306 is periodically arranged along a column direction (eg, direction D1 ). For example, the preparation method of the mask layer 306 may include forming a material layer spanning the entire area, and performing patterning on the material layer through a photolithography process and an etching process to form the mask layer 306 . The fabrication technique of the mask layer 306 is a material with sufficient etch selectivity relative to the semiconductor substrate 200 .

Referring to FIG. 3 , FIG. 4H and FIG. 5H , step S25 is performed, and the uncovered initial active area AA′ is recessed relative to the initial active area AA′ covered by the mask layer 306 . Accordingly, the initial active area AA' is selectively recessed, and the active area AA as described with reference to FIG. 2B is formed. As shown in FIG. 5H , the active area AA1 is one of the recessed active areas AA, and the active area AA2 is one of the non-recessed active areas AA. Furthermore, in the recessing step, the initial trench TR' is shaped to have a trench TR with one sidewall higher than the other sidewall, as shown in FIG. 2B . In some embodiments, the method of selectively recessing the initial active area AA' includes an etching process. In these embodiments, the masking layer 306 and the isolation structures 202 have sufficient etch selectivity with respect to the semiconductor substrate 200 , so the masking layer 306 and the isolation structures 202 can be hardly consumed during the etching process for the semiconductor substrate 200 .

Referring to FIG. 3 , FIG. 4I and FIG. 5I , step S27 is performed to remove the mask layer 306 . With the mask layer 306 removed, the previously covered active area AA may now be exposed. For example, as shown in FIG. 5I, the active areas AA1, AA2 may be simultaneously exposed in the current step. According to some embodiments, the manufacturing method of the mask layer 306 includes an etching process. Since the mask layer 306 has sufficient etching selectivity with respect to the isolation structure 202 and the semiconductor substrate 200 , the isolation structure 202 and the active area AA can hardly be recessed during the etching process.

Referring to FIG. 3 , FIG. 4J and FIG. 5J , step S29 is performed to form SAMs 206 on the top surface of the active area AA. According to some embodiments, the SAMs 206 are selectively adsorbed on the top surface of the active region AA, while the top of the sidewalls of the trench TR' may remain uncovered.

In some embodiments, the SAM-forming compound can be dissolved or dispersed in a solvent. The composition of the solvent is suitable for forming the SAM layer (including the SAM-forming compound). Solvents include, but are not limited to, for example, Toluene, xylene, dichloromethane (DCM), chloroform, carbon tetrachloride, ethyl acetate, butyl acetate Butyl acetate, amyl acetate, propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), ethoxy ethyl propionate, anisole ), ethyl lactate, diethyl ether, dioxane, tetrahydrofuran (THF), acetonitrile, acetic acid, amyl acetate, acetic acid n-butyl acetate, gamma-butyrolactone (GBL), acetone, methyl isobutylketone, 2-heptanone, cyclohexanone, methanol , ethanol, ethylene glycol ether (2-ethoxyethanol), 2-butoxyethanol (2-butoxyethanol), isopropanol, n-butanol (n-butanol), N,N-dimethylformamide (DMF) , N,N-dimethylacetamide (N,N-dimethylacetamide), pyridine (pyridine), and dimethylsulfoxide (DMSO). These solvents may be used alone or in combination.

In some embodiments, the solution may be applied to the top surface of the substrate using any suitable coating technique (eg, dip coating, spin coating), followed by removal of the solvent, thus forming the initial SAM layer. The initial SAM layer has a top surface in contact with the atmosphere, and a bottom surface in contact with a selected surface of the substrate (the surface for which the SAM-forming compound has a preferential affinity). Generally, the thickness of the SAM is about 0.5 to about 20 nm, especially about 0.5 nm to about 10 nm, even about 0.5 nm to about 2 nm.

Referring to FIG. 3 , FIG. 4K and FIG. 5K , step S31 is executed to form contact-enhanced sidewall spacers 204 . According to some embodiments, the fabrication technique of the contact enhanced sidewall spacers 204 is by an epitaxial process. In an epitaxial process, the material of the contact-enhanced sidewall spacers 204 may be grown from the exposed portion of the active area AA, which is the top of the sidewalls of the active area AA, extending between the SAM 206 and the isolation structure 202 . In some cases, contact enhancing sidewall spacers 204 may also extend to the sidewalls of SAM 206 . By forming contact enhancing sidewall spacers 204, the top of the active area AA is laterally surrounded, as described with reference to FIG. 2A, with an additional portion.

Referring to FIG. 3 and FIG. 2B , step S33 is performed to form a capacitor contact CC on the active area AA. Although not shown, several process steps may be performed prior to forming capacitor contact CC. For example, before forming the capacitor contact CC, a dielectric layer (not shown) may be fully formed on the active area AA and the isolation structure 202 . In addition, through holes may be formed in the dielectric layer by photolithography and etching processes to define the location of the capacitor contact CC. Subsequently, the conductive material may be filled into the via hole by a deposition process, an electroplating process, or a combination thereof, and the excess conductive material on the dielectric layer may be partially removed by a planarization process. The remainder of the conductive material in the via may form the capacitor contact CC.

So far, the structure shown in FIG. 2B has been formed. Although not shown, additional process steps may be performed to form other elements of memory array structure 10 (as described with reference to FIGS. 1B and 2A ), including word lines WL, bit lines BL, and storage capacitors SC. These additional process steps may be performed during and after the process steps described with reference to FIGS. 3 , 4A-4K , 5A-5K and 2B.

FIG. 6 is a cross-sectional view illustrating edge portions of two adjacent active areas AA and a portion of an isolation structure 202 extending between these adjacent active areas AA of some other embodiments of the present disclosure.

Referring to FIG. 6, in some embodiments, the SAMs 206 described with reference to FIG. 2B are omitted. In these embodiments, the top of each active area AA is covered by a contact enhancing capping layer 604 . Contact-enhancing capping layer 604 is similar in material selection and function to contact-enhancing sidewall spacers 204 (as described with reference to FIG. 2B ). In other words, the contact-enhancing capping layer 604 is semi-conductive or conductive, and can be used as an additional part of the active area AA for improving the electrical contact between the active area AA and the capacitor contact CC standing on the active area AA. In some embodiments, the contact enhancement capping layer 604 includes a contact enhancement layer 604a on the top surface of the active area AA, and includes contact enhancement sidewall spacers 604b laterally surrounding the top of the active area AA. The contact enhancement sidewall spacers 604b may extend from the contact enhancement layer 604a along the sidewalls of the active area AA to the top surface of the isolation structure 202 and provide an additional landing area for the capacitor contact CC provided on the active area AA. In some embodiments, the capacitor contact CC penetrates the contact enhancement layer 604a to establish electrical contact with the active area AA.

As described above, some active areas AA (eg, active area AA1 ) protrude less than other active areas AA (eg, active area AA2 ) relative to the isolation structure 202 . Therefore, the contact-enhanced capping layer 604 (referred to as contact-enhanced capping layer 604-1) covering the less protruding active area AA is lower than the contact-enhancing capping layer 604 (referred to as contact-enhancing capping layer 604-1) covering the more protruding active area AA. -2). In other words, the contact enhancement layer 604a of the contact enhancement cap layer 604-1 may extend on a lower plane than the plane in which the contact enhancement layer 604a of the contact enhancement cap layer 604-2 extends. In addition, the contact-enhanced sidewall spacers 604b of the contact-enhanced cap layer 604-1 may have a height H _604-1 that is shorter than the height H 604-2 of the contact-enhanced sidewall spacers 604b of the contact-enhanced cap layer _604-2 . The height H _604-1 is measured from the bottom end of the contact enhancement sidewall spacer 604b of the contact enhancement cap layer 604-1 (which may be flush with the top surface TS ₂₀₂ of the isolation structure 202) to the contact enhancement sidewall spacer 604b. top. Likewise, the height H _604-2 is measured from the bottom end of the contact enhancement sidewall spacer 604b of the contact enhancement cap layer 604-2 (which may be flush with the top surface TS ₂₀₂ of the isolation structure 202) to the contact enhancement sidewall spacer Top of 604b. Since the contact-enhanced capping layer 604-1 is lower than the contact-enhanced capping layer 604-2, the top corners of the contact-enhanced capping layers 604-1, 604-2 can be more spaced apart in the vertical direction. Therefore, when adjacent active regions AA When the width of the trench TR is greatly reduced, the merging of the contact enhancement capping layers 604-1 and 604-2 can be prevented. Accordingly, interference between memory cells 100 formed on adjacent active areas AA can be avoided.

In the preparation of the structure as shown in FIG. 6, the step of forming SAM 206 (as described with reference to FIGS. 4J and 5J) may be omitted. In addition, after the active area AA1 is recessed and the mask layer 306 is removed (as described with reference to FIGS. 4H-4I and 5H-5I ), a contact-enhancing capping layer 604 is formed on the active area AA by, for example, an epitaxial process. In addition, a capacitor contact CC may be formed on the active area AA.

As mentioned above, the active regions of the memory cells in the memory array structure have extra portions (ie, contact enhancing sidewall spacers) at their corners. By having these extra parts, the active area can provide a larger landing area for the capacitor contacts standing on the active area. Accordingly, the electrical contact between the capacitor contact and the active region may be less affected by process variations in placing the capacitor contact. In other words, the electrical contact between the capacitor contacts and the active area can be improved. In addition, adjacent active regions are designed to have different heights, and the top surface of one active region may be concave relative to the top surface of the adjacent active region. Accordingly, additional portions of adjacent active regions may be more spaced apart in the vertical direction. Accordingly, adjacent active regions can be prevented from merging together, thus avoiding interference between memory cells formed on adjacent active regions.

In an embodiment of the present disclosure, a memory array structure is provided, including: a semiconductor substrate, a trench defining an active region laterally separated by a surface region of the semiconductor substrate, wherein a first active region of the active region A top surface of the group of active regions is recessed relative to a top surface of a second group of active regions; an isolation structure is filled in the trench and is in lateral contact with a bottom portion of the active region; and a contact-enhancing sidewall The spacers respectively laterally surround a top of the active area.

In one embodiment of the present disclosure, a memory array structure is provided, including: an active area formed by a laterally separated surface portion of a semiconductor substrate, wherein a top surface of a first group of active areas is opposite to a A top surface of the second group of active regions is recessed; an isolation structure extends between the active regions and is in contact with a bottom portion of the active regions; and a contact-enhancing capping layer covers a top of the active regions, respectively. .

In yet another embodiment of the present disclosure, a method for fabricating a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines an active laterally separated by a surface region of the semiconductor substrate. region; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active region; recessing a first group of active regions from a top surface of the first group of active regions and covering a top surface of a second group of active regions at the same time; and forming a contact-enhancing sidewall spacer to laterally surround a top of the active region.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of the disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, and materials that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. composition, means, method, or steps. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are included within the disclosed claims of the present disclosure.

Claims (19)

1. A memory array structure, comprising: A semiconductor substrate having a trench defining an active region laterally separated by a surface region of the semiconductor substrate, wherein a top surface of a first set of active regions of the active region is opposite a top surface of a second set of active regions Concave; an isolation structure filled in the trench and in lateral contact with a bottom portion of the active region; and A contact-enhanced sidewall spacer respectively laterally surrounds a top of the active region. 2. The memory array structure of claim 1, wherein each of the first set of active areas is adjacent to one or more of the second set of active areas. 3. The memory array structure of claim 1 , wherein the trench defining a boundary of the first set of active regions is compared to a second sidewall of the trench defining a boundary of the second set of active regions A first side wall is shorter in height. 4. The memory array structure of claim 1, wherein a top surface of the isolation structure is lower than the top surface of the first group of active regions and the top surface of the second group of active regions. 5. The memory array structure of claim 1, wherein the top surface of the isolation structure is in contact with a bottom end of the contact-enhanced sidewall spacer. 6. The memory array structure of claim 1, wherein the laterally surrounding the first set of active regions is compared to a second set of contact enhancing sidewall spacers laterally surrounding the top of the second set of active regions A first set of contact-enhancing sidewall spacers at the top are shorter in height. 7. The memory array structure of claim 1 , wherein a corner of the first group of contact-enhancing sidewall spacers laterally surrounding the top of the first group of active regions is along a lateral direction and a vertical direction with lateral A top corner of the second set of contact enhancing sidewall spacers surrounding the top of the second set of active regions is spaced apart. 8. The memory array structure of claim 1, further comprising: A self-assembled monolayer covers the top surface of the active area. 9. The memory array structure of claim 8, wherein the contact enhanced sidewall spacer also covers a sidewall of the self-assembled monolayer. 10. The memory array structure of claim 8 , wherein a first set of self-assembled monolayers covering the top of the first set of active regions has a lower height than a first set of self-assembled monolayers covering the top of the second set of active regions. The height of the two sets of SAMs. 11. The memory array structure of claim 1, wherein the contact enhancing sidewall spacers are semiconducting or conducting. 12. A method for preparing a memory array, comprising: forming a trench in a front side of a semiconductor substrate, wherein the trench defines an active region laterally separated from a surface region of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active region; recessing a first set of active regions from a top surface of the first set of active regions while covering a top surface of a second set of active regions; and A contact-enhancing sidewall spacer is formed to laterally surround a top of the active region, respectively. 13. The manufacturing method of the memory array as claimed in claim 12, wherein the formation of the trench comprises: forming at least one insulating layer on the front side of the semiconductor substrate; forming a mask pattern on the at least one insulating layer; performing an etching process on the at least one insulating layer and the semiconductor substrate by using the mask pattern as a shadow mask to form the trench; and The mask pattern and the at least one insulating layer are removed. 14. The method for fabricating a memory array as claimed in claim 13, wherein the at least one insulating layer comprises a first insulating layer and a second insulating layer stacked on the first insulating layer. 15. The manufacturing method of the memory array as claimed in claim 12, wherein the formation of the isolation structure comprises: providing an insulating material in the trench; and Recessing the insulating material, thereby recessing the insulating material relative to the top surface of the active region, and forming the isolation structure. 16. The manufacturing method of a memory array as claimed in claim 12, wherein the second group of active regions is covered by a mask layer, and the first group of active regions is recessed to form a contact-enhanced sidewall spacer Before, remove the mask layer. 17. The preparation method of memory array as claimed in claim 12, further comprising: Before forming the contact-enhancing sidewall spacers, a self-assembled monolayer is formed on the top surface of the active region. 18 . The method for fabricating a memory array as claimed in claim 17 , wherein before forming the contact-enhanced sidewall spacers, the top sidewall of the active region remains uncovered by the self-assembled monolayer. 19. The method of fabricating the memory array of claim 17, wherein the method of fabricating the contact-enhanced sidewall spacers comprises an epitaxial process.

Images