CN116154020A - Two-dimensional material optimized low-gain avalanche multiplication anti-irradiation silicon carbide detector chip and preparation and application thereof - Google Patents

Abstract

The invention belongs to the technical field of detectors, and provides a two-dimensional material optimized low-gain avalanche multiplication irradiation-resistant silicon carbide detector chip, and preparation and application thereof, wherein the chip comprises: and the first electrode and/or the second electrode are/is provided with an inserting layer made of two-dimensional materials at one side close to the silicon carbide substrate, and the contact between the inserting layer and the corresponding electrode is ohmic contact. The preparation method of the chip comprises the following steps: sequentially manufacturing an insertion layer and a first electrode which are made of two-dimensional materials on a silicon carbide epitaxial wafer; and/or sequentially manufacturing an insertion layer and a second electrode which are made of two-dimensional materials on the back surface of the silicon carbide epitaxial wafer; the annealing temperature adopted in the process of manufacturing the first electrode and/or the second electrode is 400-600 ℃. The silicon carbide detector chip can increase the response signal of the detector and improve the signal to noise ratio, has higher response speed, and can be widely applied to high-energy particle detection.

Description

A two-dimensional material-optimized low-gain avalanche multiplication radiation-resistant silicon carbide detector core Tablets and their preparation and application

technical field

The invention relates to the technical field of detectors, in particular to a two-dimensional material-optimized low-gain avalanche multiplication radiation-resistant silicon carbide detector chip and its preparation and application.

Background technique

In order to meet the needs of high-energy physics scientific experiments in the next five years or longer, research on silicon carbide particle detectors with strong radiation resistance and high time resolution at room temperature has become a hot topic in the frontiers of high-energy physics. As a wide bandgap semiconductor, silicon carbide material has a high atomic displacement threshold and a large bandgap width, so it has the inherent advantages of radiation resistance and high temperature resistance. The critical breakdown field strength of silicon carbide materials is significantly higher than that of silicon-based materials, and the electron saturation drift rate of silicon carbide can reach twice that of silicon, which means that silicon carbide devices can withstand higher operating voltages and reduce carrier drift Time, reducing the probability of carriers being trapped, thereby improving the time resolution of the device. At the same time, silicon carbide materials with high thermal conductivity will promote the technological innovation of radiation-resistant detectors at room temperature, and greatly promote their applications in extreme environments such as space exploration, nuclear power plants, particle colliders, and nuclear reactors.

At present, silicon carbide materials are mainly used in the field of particle energy and intensity detection. The high band gap of silicon carbide materials leads to low response signals. At the same time, the stability of the ohmic contact of the silicon carbide device, especially the P-type ohmic contact, limits the development of the position resolution and time resolution performance of the particle detector. If the signal-to-noise ratio of the silicon carbide detector chip is improved while improving the response signal, it will help improve the time and position resolution ability of the silicon carbide detector for passing particles, thereby greatly broadening its application field.

In view of this, the present invention is proposed.

Contents of the invention

Aiming at the above-mentioned problems in the prior art, the present invention provides a low-gain avalanche multiplication anti-irradiation silicon carbide detector chip optimized by two-dimensional materials and its preparation method, which is a new approach in the structure of silicon carbide detectors and provides a It has a new silicon carbide structure with high radiation resistance and can improve the response signal while improving the signal-to-noise ratio of the silicon carbide detector chip, thereby improving the time resolution performance and position resolution performance of the silicon carbide detector for passing particles.

Specifically, the present invention provides a silicon carbide detector chip, including: a first electrode and a second electrode, and the first electrode and/or the second electrode are arranged on the side closer to the silicon carbide substrate and are made of a two-dimensional material The insertion layer, and the contact between the insertion layer and the corresponding electrode is an ohmic contact.

In the present invention, through the set insertion layer composed of two-dimensional materials, the chip can realize ohmic contact under low-temperature annealing conditions, which reduces the activation of impurities in the silicon carbide epitaxial layer by high-temperature annealing, thereby optimizing the detection The ohmic contact characteristics and leakage characteristics of the device can effectively reduce the dark current, promote the separation of carriers, and improve the energy resolution, thereby optimizing the performance of the detector device.

The contact between the insertion layer and the corresponding electrode is an ohmic contact, and the height of the Schottky barrier can be adjusted by changing the thickness of the insertion layer composed of two-dimensional materials. At the same time, the intercalated layer of 2D materials in contact with the interface and the mixed phase formed by the interaction with the metal have a lower work function. In addition, the electric dipole layer formed at the silicon carbide/two-dimensional material interface is also conducive to reducing the barrier height.

According to the silicon carbide detector chip provided by the present invention, the chip is a two-dimensional array detector chip with vertical incidence from the top surface, and sequentially includes a silicon carbide substrate, a buffer layer, an intrinsic layer, a gain layer and an ohmic contact layer from bottom to top The sides of the gain layer, the sides of the ohmic contact layer and the top of the exposed intrinsic layer are all provided with a passivation layer; the first electrode is located on the top of the ohmic contact layer, and the second electrode is located on the silicon carbide substrate layer At the bottom, the polarity of the first electrode is opposite to that of the second electrode; the insertion layer is located between the first electrode and the ohmic contact layer, and/or between the second electrode and the silicon carbide substrate;

Preferably, the preferred thickness of the insertion layer is 0.3nm-10nm.

According to the silicon carbide detector chip provided by the present invention, the two-dimensional materials include simple two-dimensional materials, transition metal dihalides, transition metal carbides, transition metal nitrides, transition metal carbonitrides, organic two-dimensional materials or hexagonal boron nitride;

Preferably, the simple two-dimensional material includes: graphene or black phosphorus, preferably, the atomic layer of the simple two-dimensional material is <10 layers;

Preferably, the transition metal dihalide includes: MoS ₂ or WS ₂ .

Graphene, MoS ₂ , black phosphorus, and WS ₂ are used as intermediate transition layers between metal and silicon carbide, which can regulate the electrical characteristics of the metal/silicon carbide contact, which is conducive to reducing the metal/silicon carbide interface barrier and improving ohmic characteristics. At the same time, graphene, as an intermediate transition layer between metal and silicon carbide, can promote the formation of carbides at the interface between metal and silicon carbide, achieving better results.

According to the silicon carbide detector chip provided by the present invention, the gain layer is N-type doped silicon carbide, the average doping concentration is controlled at 1×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 , and the thickness is 0.1 to 2 μm The average doping concentration and thickness of the gain layer in the present invention are very critical, compared with traditional silicon carbide detectors, when adding the above-mentioned gain layer in the silicon carbide detector chip of the present invention, the detector can be made Increase the response signal to effectively solve the problem of small signal due to the high electron-hole ionization energy of silicon carbide itself; at the same time, the intensity of the amplified signal of the detector is much higher than the noise, which can effectively improve the signal-to-noise ratio of the detector, especially Suitable for particle detectors.

Preferably, the overall longitudinal section formed by the gain layer and the ohmic contact layer is a trapezoid, and the internal angle of the trapezoid is 20°-90°.

According to the silicon carbide detector chip provided by the present invention, the ohmic contact layer is P-type heavily doped silicon carbide, with an average doping concentration of 1×10 ¹⁸ cm ^-3 to 1×10 ²⁰ cm ^-3 ;

And/or, the buffer layer is N-type doped silicon carbide, with an average doping concentration of 1×10 ¹⁶ cm ^-3 to 1×10 ¹⁸ cm ^-3 .

According to the silicon carbide detector chip provided by the present invention, the intrinsic layer is N-type low-doped silicon carbide, the average doping concentration is controlled below 1×10 ¹⁵ cm ^-3 , and the thickness is 10 μm to 100 μm;

And/or, the silicon carbide substrate is an N-type conductive silicon carbide substrate.

In the present invention, in the layer of doped silicon carbide structure, uniform doping is preferred.

The present invention also provides a method for preparing the silicon carbide detector chip as described above, comprising: sequentially fabricating an insertion layer made of two-dimensional material and a first electrode on the silicon carbide epitaxial wafer; and/or, on the back side of the silicon carbide epitaxial wafer Fabricating an insertion layer and a second electrode made of two-dimensional materials in sequence;

The annealing temperature used when making the first electrode and/or the second electrode is 400°C to 600°C;

Preferably, the insertion layer is made by thermal decomposition of silicon carbide, wet transfer chemical vapor deposition, chemical vapor deposition or coating solution.

The preparation method of the silicon carbide detector chip provided according to the present invention comprises:

SiC epitaxial wafers are cleaned and dried;

Fabrication of intercalated layers made of 2D materials;

making the first electrode;

Remove excess 2D material;

Mesa etching;

Make a passivation layer;

making the second electrode;

Scribing and packaging.

The method for preparing a silicon carbide detector chip according to the present invention further includes: pre-depositing a layer of Ni or Ti metal film on the insertion layer;

Preferably, the thickness of the metal film is 30nm-80nm.

The present invention also provides the above-mentioned silicon carbide detector for detecting, tracking and identifying electrons, protons, neutrons, quarks, X-rays, alpha, beta and gamma radiation, neutrinos and other high-energy particles in the field of particle physics.

A low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials of the present invention is provided with an insertion layer composed of two-dimensional materials, so that it has an adjustable band gap, and can realize Schottky barrier and electrical Performance regulation, and then achieve low-temperature annealing ohmic contact, reduce the influence of relatively high annealing temperature to excite impurities in the semiconductor epitaxial layer and make impurities become scattering centers, effectively reduce dark current, promote carrier separation, and improve energy resolution rate, thereby optimizing the performance of the detector device.

A two-dimensional material optimized low-gain avalanche multiplication radiation-resistant silicon carbide detector chip of the present invention can simultaneously solve the problem of the low radiation resistance performance of silicon detectors and the low response signal of traditional silicon carbide detectors, and can As a good time and position resolution detector chip, it is used in extreme environments such as high radiation and high temperature. Due to the fast response speed of the low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials, it can be widely used in the detection of high-frequency particle signals.

Description of drawings

In order to more clearly illustrate the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are the present invention. For some embodiments of the invention, those skilled in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is the flowchart of the preparation method of the low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by the two-dimensional material of the present invention;

2 is a schematic structural diagram of a low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials according to Embodiment 1 of the present invention;

3 is a schematic structural view of a low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials according to Embodiment 2 of the present invention;

4 is a schematic structural diagram of a low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials according to Embodiment 3 of the present invention;

In the figure: 1. First electrode; 2. Insertion layer; 3. Passivation layer; 4. Ohmic contact layer; 5. Gain layer; 6. Intrinsic layer; 7. Buffer layer; 8. Silicon carbide substrate; 9 , the second electrode.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

If no specific technique or condition is indicated in the examples, it shall be carried out according to the technique or condition described in the literature in this field, or according to the product specification. The reagents or instruments used were not indicated by the manufacturer, and they were all conventional products that can be purchased through formal channels.

The low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials of the present invention and its preparation and application are described below with reference to FIGS. 1-4 .

The silicon carbide detector chip provided by the present invention includes: a first electrode and a second electrode, and the first electrode and/or the second electrode is provided with an insertion layer made of a two-dimensional material on the side closer to the silicon carbide substrate , and the contact between the insertion layer and the corresponding electrode is an ohmic contact.

The above-mentioned first electrode and/or second electrode is provided with an insertion layer composed of a two-dimensional material on the side closer to the silicon carbide substrate, including 3 cases, specifically:

forming the insertion layer only under the first electrode;

forming the insertion layer only between the second electrode and the silicon carbide substrate;

forming the insertion layer under the first electrode and between the second electrode and the silicon carbide substrate, respectively;

Preferably, the chip is a two-dimensional array detector chip with vertical incidence from the top surface, including a silicon carbide substrate, a buffer layer, an intrinsic layer, a gain layer and an ohmic contact layer from bottom to top; the side of the gain layer, the ohmic contact The side of the layer and the top of the exposed intrinsic layer are provided with a passivation layer; the first electrode is located on the top of the ohmic contact layer, the second electrode is located at the bottom of the silicon carbide substrate layer, the first electrode and the second The polarity of the electrodes is opposite; the insertion layer is located between the first electrode and the ohmic contact layer, and/or between the second electrode and the silicon carbide substrate;

Preferably, the insertion layer has a thickness of 0.3nm-10nm.

Preferably, the two-dimensional material includes simple two-dimensional materials, transition metal dihalides, transition metal carbides, transition metal nitrides, transition metal carbonitrides, organic two-dimensional materials or hexagonal boron nitride;

Preferably, the simple two-dimensional material includes: graphene or black phosphorus, preferably, the atomic layer of the simple two-dimensional material is <10 layers;

Preferably, the transition metal dihalide includes: MoS ₂ or WS ₂ .

Preferably, the gain layer is N-type doped silicon carbide, the average doping concentration is controlled at 1×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 , and the thickness is 0.1 μm to 2 μm;

Preferably, the overall longitudinal section formed by the gain layer and the ohmic contact layer is a trapezoid, and the internal angle of the trapezoid is 20°-90°.

Preferably, the ohmic contact layer is P-type heavily doped silicon carbide, with an average doping concentration of 1×10 ¹⁸ cm ^-3 to 1×10 ²⁰ cm ^-3 ;

And/or, the buffer layer is N-type doped silicon carbide, with an average doping concentration of 1×10 ¹⁶ cm ^-3 to 1×10 ¹⁸ cm ^-3 .

The thickness of the ohmic contact layer in the present invention may be 0.3 μm˜0.6 μm.

The thickness of the buffer layer in the present invention may be 1 μm˜10 μm.

Preferably, the intrinsic layer is N-type low-doped silicon carbide, the average doping concentration is controlled below 1×10 ¹⁵ cm ^-3 , and the thickness is 10 μm to 100 μm;

And/or, the silicon carbide substrate is an N-type conductive silicon carbide substrate.

The thickness of the silicon carbide substrate in the present invention may be 150 μm to 400 μm.

The method for preparing a silicon carbide detector chip as described above includes: sequentially fabricating an insertion layer made of a two-dimensional material and a first electrode on a silicon carbide epitaxial wafer; An insertion layer and a second electrode composed of a dimensional material;

The annealing temperature used when making the first electrode and/or the second electrode is 400°C to 600°C;

Preferably, the insertion layer is made by thermal decomposition of silicon carbide, wet transfer chemical vapor deposition, chemical vapor deposition or coating solution.

Preferably, the method for preparing the silicon carbide detector chip as described above includes:

SiC epitaxial wafers are cleaned and dried;

Fabrication of intercalated layers made of 2D materials;

making the first electrode;

Remove excess 2D material;

Mesa etching;

Make a passivation layer;

making the second electrode;

Scribing and packaging.

As shown in Figure 1, taking an N-type silicon carbide substrate and the first electrode and the second electrode are provided with an insertion layer composed of a two-dimensional material on the side close to the silicon carbide substrate as an example, the specific preparation steps are as follows:

Step 1, SiC epitaxial wafer cleaning and drying:

Clean the silicon carbide epitaxial wafer to be cleaned according to the RCA standard. After cleaning, the chip is blown dry with high-purity nitrogen protection to ensure that the silicon carbide epitaxial wafer to be processed is heated and dried for use. Wherein, the silicon carbide epitaxial wafer to be cleaned can be obtained by conventional epitaxial manufacturing methods, such as epitaxially growing a buffer layer, an intrinsic layer, a gain layer and an ohmic contact layer on a silicon carbide substrate.

Step 2. Make the first insertion layer

First, the first intercalation layer needs to be prepared on the ohmic contact layer by silicon carbide thermal decomposition method, wet transfer chemical vapor deposition method, vapor deposition method or coating solution method, wherein the coating solution method can be spin coating solution method, Drip solution method or spray solution method.

Due to the weak chemical adsorption between two-dimensional materials and metals, the electronic properties of two-dimensional materials will not be significantly changed, and the structural integrity of two-dimensional materials can be preserved to the greatest extent. Therefore, a thin Ni or Ti metal film is pre-deposited on the two-dimensional material to protect the two-dimensional material. The thickness of the metal film can be selected according to the material of the electrode, such as when the material of the electrode on the metal film is In the case of Ni/Ti/Al alloy, the metal film can be a Ni metal film, and when the electrode on the metal film is made of Ti/Al, the metal film can be a Ti metal film.

The role of the metal Ni and Ti is to protect the two-dimensional material, and the second can be used as an electrode material. When used as metal electrode materials, the main role of Ni and Ti is to ensure good adhesion between metal and semiconductor. Too thin or too thick Ni and Ti metals will increase the contact resistivity. When the thickness of the Ni and Ti metal layers is too thin, there are more lattice gaps due to the network structure of the metal film, resulting in greater resistance to electron movement, which in turn leads to low contact resistivity; when the thickness of the Ni and Ti metal layers is too thick , there are many lattice defects on the metal surface, and the lattice defects form obvious inelastic scattering, resulting in a decrease in contact resistivity.

Preferably, the thickness of the metal film may be 30nm-80nm.

Finally, a photoresist is coated on the metal of the epitaxial wafer, and the excess metal film not covered by the photoresist is removed by photolithography development, wet etching or etching (that is, at the position where the first electrode is not formed).

Step 3. Make the first electrode

The epitaxial wafer to be processed is coated with a negative peeling photoresist such as SU-8, and developed by photolithography to make the first electrode pattern. Then, magnetron sputtering technology and other metal processes are used to grow electrode metal materials. Finally, a metal lift-off process is performed to fabricate the metal first electrode.

Step 4. Remove excess 2D material

A photoresist such as AZ5214 is coated on the epitaxial wafer to be processed as a soft mask for etching or etching, and photolithography is developed to obtain the first electrode structure pattern. Then, the excess two-dimensional material on the epitaxial wafer is removed by wet etching or dry etching, and the chip is cleaned according to the RCA standard. After cleaning, the epitaxial wafers to be processed are blown dry with high-purity nitrogen protection to ensure that they are clean, then heat and dry the wafers for later use.

Step 5. Mesa etching

First, a metal mask with a certain thickness is deposited or sputtered on the epitaxial wafer to be processed. Coat AZ5214 or other photoresist on the epitaxial wafer to be processed, which is deposited or sputtered with a certain thickness of metal mask, as an etching soft mask, and photolithographically developed to obtain a mesa structure pattern. Secondly, a metal mesa mask is fabricated by wet etching or dry etching. Clean the chip according to the RCA standard. After cleaning, the epitaxial wafer to be processed is blown dry with high-purity nitrogen protection. After ensuring that it is clean, heat and dry the wafer. Then, etch or etch the silicon carbide mesa by wet etching or dry etching, etch the chip to the upper surface of the intrinsic layer, and control the etching conditions to ensure that the adjacent gain layer and ohmic contact layer formed The longitudinal section of the two-layer structure is trapezoidal, and the internal angle of the trapezoid is 20°-90°. Finally, the excess metal mask layer is removed by wet etching. Clean the chip according to RCA standard. After cleaning, the epitaxial wafers to be processed are blown dry with high-purity nitrogen protection to ensure that they are clean, then heat and dry the wafers for later use.

Step 6. Make a passivation layer

First, deposit or sputter a certain thickness of insulating materials such as SiO ₂ , AlN, and Si ₃ N ₄ on the epitaxial wafer to be processed as a passivation layer; secondly, coat the epitaxial wafer to be processed with photoresist such as AZ5214, and develop the first electrode by photolithography Holes are etched or etched in the passivation layer to create holes for the first electrode, waiting for wire bonding packaging to be used.

Step 7. Make the second insert layer

Prepare the second insertion layer on the back side of the silicon carbide epitaxial wafer according to the method in step 2.

Step 8. Make the second electrode

The metal second electrode is sputtered on the second insertion layer by magnetron sputtering technology, and the metal alloy is annealed by a rapid annealing process, wherein the annealing temperature is 400°C-600°C, and the annealing time is 30s-3min.

Step 9, dicing and packaging:

The finished chip is diced with a dicing machine, and the welding of the electrodes and welding points of the external power supply system is completed by means of wire bonding and thermocompression welding, and the chip packaging is completed.

If the insertion layer is only provided on one side of the first electrode, step seven is omitted in the preparation process, and in step eight, the second electrode is formed by sputtering on the back of the silicon carbide epitaxial wafer.

If the insertion layer is only provided on one side of the second electrode, step 2 is omitted in the preparation process.

Example 1

As shown in Figure 1, a low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials provided by the present invention is a two-dimensional array detector chip with vertical incidence from the top surface, including: first Electrode 1 , insertion layer 2 , passivation layer 3 , ohmic contact layer 4 , gain layer 5 , intrinsic layer 6 , buffer layer 7 , silicon carbide substrate 8 and second electrode 9 .

Wherein, the side of the gain layer 5 and the ohmic contact layer 4 and the top of the exposed intrinsic layer 6 are provided with a passivation layer 3; the top of the ohmic contact layer 4 is provided with a first electrode 1, and the silicon carbide substrate 8 is provided with a second electrode. Electrode 9, the polarity of the first electrode and the second electrode is opposite; between the first electrode 1 and the ohmic contact layer 4 and the second electrode 9 and the silicon carbide substrate 8, a two-dimensional material with a thickness of about It is an insertion layer 2 of 0.334nm, and the material of the insertion layer 2 is single-layer graphene; the longitudinal section of the two-layer structure formed by the adjacent gain layer and the ohmic contact layer between the layers is a trapezoid, and the internal angle of the trapezoid is 85°.

The ohmic contact layer 4 is P-type heavily doped silicon carbide, the doping ions are Al ³⁺ , the average doping concentration is 5×10 ¹⁹ cm ^-3 , and the thickness is 0.4 μm.

The gain layer 5 is N-type doped silicon carbide, the doping ions are N ^3- , the average doping concentration is 1.4×10 ¹⁷ cm ^-3 , and the thickness is 1 μm.

The intrinsic layer 6 is N-type low-doped silicon carbide, the average doping concentration is controlled to 5×10 ¹³ cm ^-3 , and the thickness is 100 μm.

The buffer layer 7 is N-type doped silicon carbide with an average doping concentration of 1×10 ¹⁸ cm ⁻³ and a thickness of 5 μm.

Silicon carbide substrate 8 is an N-type conductive silicon carbide substrate with a thickness of 350 μm.

The passivation layer 3 is made of SiO ₂ and has a thickness of 400nm.

The material of the first electrode 2 is Ni/Ti/Al, and the corresponding thickness is 60nm/30nm/500nm.

The material of the second electrode 3 is Ni/Ti/Al, and the corresponding thickness is 60nm/30nm/500nm.

Example 2

As shown in Figure 2, the present invention provides a low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials. The chip is a two-dimensional array detector chip with vertical incidence from the top surface, including: a first electrode 1 , an insertion layer 2 , a passivation layer 3 , an ohmic contact layer 4 , a gain layer 5 , an intrinsic layer 6 , a buffer layer 7 , a silicon carbide substrate 8 and a second electrode 9 .

In the present invention, the sides of the intrinsic layer 6, the gain layer 5 and the ohmic contact layer 4 and the top of the exposed intrinsic layer 6 are provided with a passivation layer 3; the top of the ohmic contact layer 4 is provided with a first electrode 1, and the silicon carbide lining The bottom 8 is provided with a second electrode 9, the polarity of the first electrode is opposite to that of the second electrode; an insertion layer made of a two-dimensional material with a thickness of about 1.3 nm is arranged between the first electrode 1 and the ohmic contact layer 4 2. The material of the insertion layer 2 is double-layer molybdenum disulfide; the longitudinal section of the two-layer structure formed by the adjacent gain layer and ohmic contact layer is trapezoidal, and the internal angle of the trapezoid is 60°.

The ohmic contact layer 4 is P-type heavily doped silicon carbide, the doping ions are Al ³⁺ , the average doping concentration is 5×10 ¹⁹ , and the thickness is 0.5 μm.

The gain layer 5 is N-type doped silicon carbide, the doping ions are N ^3- , the average doping concentration is controlled at 1.48×10 ¹⁷ cm ^-3 , and the thickness is 1 μm.

The intrinsic layer 6 is N-type low-doped silicon carbide with an average doping concentration of 6×10 ¹³ cm ⁻³ and a thickness of 50 μm.

The buffer layer 7 is N-type doped silicon carbide with an average doping concentration of 1×10 ¹⁸ cm ⁻³ and a thickness of 5 μm.

Silicon carbide substrate 8 is an N-type conductive silicon carbide substrate with a thickness of 300 μm.

The passivation layer 3 is made of SiO ₂ and has a thickness of 300nm.

The material of the first electrode 2 is Ni/Ti/Al, and the corresponding thickness is 60nm/30nm/500nm.

The material of the second electrode 3 is Ni/Ti/Al, and the corresponding thickness is 60nm/30nm/500nm.

Example 3

As shown in Figure 3, the present invention provides a low-gain avalanche multiplication radiation-resistant silicon carbide detector chip optimized by two-dimensional materials. The chip is a two-dimensional array detector chip with vertical incidence from the top surface, including: a first electrode 1 , an insertion layer 2 , a passivation layer 3 , an ohmic contact layer 4 , a gain layer 5 , an intrinsic layer 6 , a buffer layer 7 , a silicon carbide substrate 8 and a second electrode 9 .

In the present invention, the sides of the intrinsic layer 6, the gain layer 5 and the ohmic contact layer 4 and the top of the exposed intrinsic layer 6 are provided with a passivation layer 3; the top of the ohmic contact layer 4 is provided with a first electrode 1, and the silicon carbide lining The bottom 8 is provided with a second electrode 9, and the polarity of the first electrode and the second electrode is opposite; an insertion layer composed of a two-dimensional material with a thickness of about 1 nm is arranged between the second electrode 9 and the silicon carbide substrate 8 2. The material of the insertion layer 2 is a single layer of black phosphorus; the longitudinal section of the two-layer structure formed by the adjacent gain layer and the ohmic contact layer is trapezoidal, and the internal angle of the trapezoid is 20°.

The ohmic contact layer 4 is P-type heavily doped silicon carbide, the doping ions are Al ³⁺ , the average doping concentration is 5×10 ¹⁹ cm ^-3 , and the thickness is 0.5 μm.

The gain layer 5 is N-type doped silicon carbide, the doping ions are N ^3- , the average doping concentration is controlled at 1.5×10 ¹⁷ cm ^-3 , and the thickness is 1 μm.

The intrinsic layer 6 is N-type low-doped silicon carbide with an average doping concentration of 8×10 ¹⁴ cm ⁻³ and a thickness of 50 μm.

The buffer layer 7 is N-type doped silicon carbide with an average doping concentration of 1×10 ¹⁶ cm ⁻³ and a thickness of 5 μm.

Silicon carbide substrate 8 is an N-type conductive silicon carbide substrate with a thickness of 350 μm.

The passivation layer 3 is made of SiO ₂ and has a thickness of 350nm.

The material of the first electrode 2 is Ni/Ti/Al, and the corresponding thickness is 60nm/30nm/500nm.

The material of the second electrode 3 is Ni/Ti/Al, and the corresponding thickness is 60nm/30nm/500nm.

A two-dimensional material optimized low-gain avalanche multiplication radiation-resistant silicon carbide detector chip of the present invention can increase the response signal of the detector and improve the signal-to-noise ratio, and can simultaneously solve the low radiation resistance and carbonization of the silicon detector Due to the low response signal problem of silicon detectors, it can be used as a good time and position resolution detector in extreme scenarios such as high radiation and high temperature; at the same time, due to the optimized low-gain avalanche multiplication of two-dimensional materials, radiation-resistant silicon carbide detectors The chip has a fast response speed, so it can be widely used in the detection of high-frequency particle signals.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A silicon carbide detector chip, comprising: and the first electrode and/or the second electrode is/are provided with an inserting layer made of a two-dimensional material on the side of the first electrode and/or the second electrode, which is closer to the silicon carbide substrate, and the contact between the inserting layer and the corresponding electrode is ohmic contact.

2. The silicon carbide detector chip of claim 1, wherein the chip is a two-dimensional array detector chip vertically incident from a top surface, comprising, in order from bottom to top, a silicon carbide substrate, a buffer layer, an intrinsic layer, a gain layer, and an ohmic contact layer; the side surface of the gain layer, the side surface of the ohmic contact layer and the top of the exposed intrinsic layer are all provided with passivation layers; the first electrode is positioned at the top of the ohmic contact layer, the second electrode is positioned at the bottom of the silicon carbide substrate layer, and the polarities of the first electrode and the second electrode are opposite; the insertion layer is positioned between the first electrode and the ohmic contact layer and/or between the second electrode and the silicon carbide substrate;

preferably, the thickness of the insertion layer is 0.3nm to 10nm.

3. The silicon carbide detector chip of claim 1 or 2, wherein the two-dimensional material comprises an elemental two-dimensional material, a transition metal dihalide, a transition metal carbide, a transition metal nitride, a transition metal carbonitride, an organic two-dimensional material, or hexagonal boron nitride;

preferably, the elemental two-dimensional material comprises: graphene or black phosphorus, preferably an atomic layer of elemental two-dimensional material < 10 layers;

preferably, the transition metal dihalide comprises: moS (MoS) ₂ Or WS ₂ 。

4. The silicon carbide detector chip of claim 2, wherein the gain layer is N-doped silicon carbide with an average doping concentration controlled to be 1 x 10 ¹⁷ cm ^-3 ～1×10 ¹⁸ cm ^-3 The thickness is 0.1 mu m to 2 mu m;

preferably, the integral longitudinal section formed by the gain layer and the ohmic contact layer is trapezoid, and the internal angle of the trapezoid is 20-90 degrees.

5. The silicon carbide detector chip of claim 2, wherein the ohmic contact layer is P-type heavily doped silicon carbide having an average doping concentration of 1 x 10 ¹⁸ cm ^-3 ～1×10 ²⁰ cm ^-3 ；

And/or the buffer layer is N-type doped silicon carbide, and the average doping concentration is 1 multiplied by 10 ¹⁶ cm ^-3 ～1×10 ¹⁸ cm ^-3 。

6. The silicon carbide detector chip of claim 2, wherein the intrinsic layer is an N-type low doped silicon carbideSilicon with average doping concentration controlled at 1×10 ¹⁵ cm ^-3 The thickness is 10-100 μm;

and/or the silicon carbide substrate is an N-type conductive silicon carbide substrate.

7. The method of manufacturing a silicon carbide detector chip according to any one of claims 1 to 6, comprising: sequentially manufacturing an insertion layer and a first electrode which are made of two-dimensional materials on a silicon carbide epitaxial wafer; and/or sequentially manufacturing an insertion layer and a second electrode which are made of two-dimensional materials on the back surface of the silicon carbide epitaxial wafer;

the annealing temperature adopted in the process of manufacturing the first electrode and/or the second electrode is 400-600 ℃;

preferably, the intercalating layer is made by a silicon carbide thermal decomposition method, a wet transfer chemical vapor deposition method, a vapor deposition method or a coating solution method.

8. The method of fabricating a silicon carbide detector chip according to claim 7, comprising:

washing and drying a silicon carbide epitaxial wafer;

manufacturing an insertion layer made of a two-dimensional material;

manufacturing a first electrode;

removing redundant two-dimensional materials;

etching the table top;

manufacturing a passivation layer;

manufacturing a second electrode;

dicing and packaging.

9. The method of fabricating a silicon carbide detector chip according to claim 8, further comprising: pre-depositing a layer of Ni or Ti metal film on the insertion layer;

preferably, the thickness of the metal film is 30nm to 80nm.

10. Use of a silicon carbide detector chip according to any of claims 1 to 6 for high energy particle detection.

Images