CN116088760A - Memory system and control method - Google Patents

Abstract

Embodiments of the present invention provide a memory system and a control method capable of increasing the number of write target blocks that can be used simultaneously. The memory system according to the embodiment receives a write request from the host including a first identifier and storage location information, the first identifier is associated with a write target block, and the storage location information indicates that a block to be written is stored. The first data location within the write buffer on the host's memory. When the memory system writes the first data into the nonvolatile memory, the first data is acquired from the write buffer by sending a transfer request including the storage location information to the host, and the first data is transferred to the nonvolatile memory. Write the first data to the one write target block in the non-volatile memory.

Description

Memory system and control method

Information about divisional applications

This case is a divisional application. The parent case of this divisional case is an invention patent application with an application date of July 13, 2018, an application number of 201810768175.5, and an invention title of "memory system and control method".

[Related applications]

This application enjoys the priority of the basic application based on Japanese Patent Application No. 2017-236269 (filing date: December 8, 2017). This application includes the entire content of the basic application by referring to this basic application.

technical field

- Embodiments of the present invention relate to a memory system including a nonvolatile memory and a control method thereof.

Background technique

In recent years, memory systems including nonvolatile memories have been widely used. As one of such memory systems, a solid state drive (SSD, solid state drive) based on NAND flash memory technology is known.

Even in servers in data centers, SSDs are used as storage devices.

Storage devices utilized in host computer systems such as servers require high I/O (Input/Output, input/output) performance.

Therefore, a new interface between a host and a storage device has recently started to be proposed.

Furthermore, in recent memory devices, there are cases where it is required to be able to write different kinds of data into different write target blocks.

However, when the number of write target blocks that can be used simultaneously increases, the number of write buffers required to temporarily store write data to be written in each write target block must also be increased. Generally, the capacity of the random access memory in the memory device is limited, and therefore it may be difficult for the memory device to prepare a sufficient number of write buffers. Therefore, in practice, the number of write target blocks that can be used simultaneously is limited as a result.

Contents of the invention

Embodiments of the present invention provide a memory system and a control method capable of increasing the number of write target blocks that can be used simultaneously.

According to an embodiment, a memory system connectable to a host includes: a nonvolatile memory; and a controller configured to be electrically connected to the nonvolatile memory and manage Multiple write target blocks assigned to multiple blocks in the memory. The controller receives a write request including a first identifier and storage location information from the host, and saves the first identifier and the storage location information, the first identifier and a write target block In association, the storage location information indicates the location in the write buffer on the memory of the host that stores the first data to be written. The controller acquires the first data from the write buffer by sending a transfer request including the storage location information to the host when writing the first data into the nonvolatile memory. first data, and transmit the first data to the non-volatile memory and write the first data into the one write target block. When the writing of the first data is completed and the first data can be read from the nonvolatile memory, the controller notifies the host of the data stored in the write buffer. The first data becomes unnecessary.

Description of drawings

FIG. 1 is a block diagram showing the relationship between a host and a memory system (flash memory device).

FIG. 2 is a block diagram showing a configuration example of a flash memory device.

FIG. 3 is a block diagram showing the relationship of a plurality of channels and a plurality of NAND type flash memory chips used in a flash memory device.

FIG. 4 is a diagram showing a configuration example of a super block used in a flash memory device.

FIG. 5 is a diagram showing the relationship between a plurality of write target blocks and a plurality of write buffer areas corresponding to a plurality of end users.

FIG. 6 is a block diagram for explaining the relationship between the flash memory device and the host-side UWB, and the data writing process executed by the host and the flash memory device.

7 is a diagram showing an example of the relationship between a plurality of write target blocks and a plurality of write buffer areas (UWB areas).

FIG. 8 is a block diagram for explaining the relationship between the flash memory device and the host-side UWB, and data read processing performed by the host and the flash memory device.

9 is a block diagram for explaining the relationship between the flash memory device supporting fuzzy-fine writing and the UWB on the host side, and the data writing process performed by the host and the flash memory device.

10 is a block diagram illustrating the relationship between a flash memory device supporting fuzzy-fine writing and a host-side UWB, and data read processing performed by the host and the flash memory device.

FIG. 11 is a sequence diagram showing the steps of data writing processing executed by the host and the flash memory device.

Fig. 12 is a flowchart showing the steps of notification processing performed by the flash memory device.

Fig. 13 is a flowchart showing the procedure of host-side processing executed upon receipt of a transfer request.

FIG. 14 is a flowchart showing the steps of a data read operation performed by the flash memory device upon receipt of a read request.

FIG. 15 is a flowchart showing the steps of host-side processing for data readout.

16 is a block diagram for explaining the relationship between a flash memory device supporting streaming writing and a host-side UWB, and data writing processing performed by the host and the flash memory device.

FIG. 17 is a diagram showing the relationship between a plurality of stream IDs and a plurality of write target blocks associated with the stream IDs.

FIG. 18 is a block diagram illustrating the relationship between a flash memory device supporting streaming writing and a host-side UWB, and data read processing performed by the host and the flash memory device.

FIG. 19 is a sequence diagram showing the steps of a data writing process performed by a flash memory device supporting fuzzy-fine writing and a host.

Fig. 20 is a block diagram showing a configuration example of a host.

FIG. 21 is a flowchart showing the procedure of data writing processing executed by a processor (CPU) in the host computer.

FIG. 22 is a flowchart showing the procedure of data read processing executed by the processor in the host.

Fig. 23 is a flowchart showing another procedure of the data reading process executed by the processor in the host.

FIG. 24 is a flowchart showing the procedure of the UWB area release process executed by the processor in the host.

Detailed ways

Embodiments will be described below with reference to the drawings.

First, the relationship between the host and the memory system will be described with reference to FIG. 1 .

This memory system is a semiconductor memory device configured such that data is written into a nonvolatile memory and data is read from the nonvolatile memory. The memory system is implemented as a flash memory device 3 based on NAND flash memory technology.

A host (host device) 2 is configured to control a plurality of flash memory devices 3 . The host 2 is realized by an information processing device configured to use a flash memory array composed of a plurality of flash memory devices 3 as a memory. The information processing device can also be a personal computer or a server computer.

In addition, the flash memory device 3 can also be used as one of a plurality of memory devices provided in the memory array. The memory array can also be connected to an information processing device such as a server computer via a cable or a network, and the memory array includes a controller that controls a plurality of memories (for example, a plurality of flash memory devices 3 ) in the memory array. When the flash memory device 3 is applied to a memory array, the controller of the memory array can also function as a host of the flash memory device 3 .

Hereinafter, a case where an information processing device such as a server computer functions as the host computer 2 will be described as an example.

The host (server) 2 and the plurality of flash memory devices 3 are connected to each other (interconnected internally) via an interface 50 . As the interface 50 for this interconnection, PCI Express (Peripheral Component Interconnect Express, Peripheral Component Interconnect Express) (PCIe) (registered trademark), NVM Express (Non Volatile Memory Express, Non-Volatile Memory Express) (NVMe) can be used. (registered trademark), Ethernet (Ethernet) (registered trademark), NVMeover Fabrics (structural NVMe) (NVMeOF), etc., but are not limited thereto.

As a typical example of the server computer functioning as the host computer 2, a server computer (hereinafter, referred to as a server) in a data center can be mentioned.

When the host 2 is realized by a server in the data center, the host (server) 2 may be connected to a plurality of end user terminals (clients) 61 via the network 51 . The host 2 can provide various services to these end user terminals 61 .

Examples of services that can be provided by the host (server) 2 include: (1) platform as a service (PaaS, platform as a service) that provides a system operation platform for each client (each end user terminal 61); and (2) Infrastructure as a service (IaaS, infrastructure as a service) or the like that provides infrastructure such as a virtual server to each client (each end user terminal 61).

A plurality of virtual machines are executed on a physical server functioning as the host (server) 2 . Each of these virtual machines running on the host (server) 2 can function as a virtual server configured to provide various services to corresponding several client terminals (end user terminal 61 ).

The host (server) 2 includes a memory management function for managing a plurality of flash memory devices 3 constituting the flash memory array, and a front-end function for providing various services including memory access to end user terminals 61, respectively.

The flash memory device 3 includes a nonvolatile memory such as a NAND flash memory. One flash memory device 3 manages a plurality of write target blocks allocated from a plurality of blocks in the nonvolatile memory. The write target block refers to a block to which data should be written. The write request (write command) sent from the host 2 to the flash memory device 3 includes an identifier associated with one write target block to which data should be written. Based on the identifier included in the write request, the flash memory device 3 determines a write target block to which the data should be written among a plurality of write target blocks.

The identifier included in the write request may also be a block identifier specifying a specific write target block. The block identifier can also be represented by a block address (block number). Alternatively, when the flash memory device 3 includes a plurality of NAND flash memory chips, the block identifier can also be represented by a combination of a block address (block number) and a chip number.

If the flash memory device 3 supports stream writing, the identifier included in the write request may also be an identifier (stream ID (IDentification)) of one of the multiple streams. In stream writing, multiple write target blocks are respectively associated with multiple streams. In other words, when the flash memory device 3 receives a write request containing a stream ID from the host 2, the flash memory device 3 writes data into the stream associated with the stream ID Write the target block. When the flash memory device 3 receives a write request containing other stream IDs from the host 2, the flash memory device 3 writes data into the other streams associated with the other stream IDs. Other writes to the target block.

A plurality of write target blocks managed by the flash memory device 3 can also be respectively used by a plurality of end users (clients) who share the flash memory device 3 . In this case, the same number or more of write target blocks as the number of end users who share the flash memory device 3 are opened in the flash memory device 3 .

Thus, in an environment where there are a plurality of write target blocks that can be used simultaneously in the flash memory device 3, it is necessary to prepare the same number of write buffers as the number of these write target blocks.

The reason for this is that most recent NAND flash memories are configured by writing multiple bits of data in each memory cell, and it is necessary to save in advance each write-in target block the data that should be written into the write-in target area. Multiple pages of data in a block.

In addition, in recent NAND flash memories, in order to reduce program disturb, there are cases in which a write method is applied by using a programming operation in multiple stages accompanied by multiple transfers of write data to the NAND flash memory. And the writing data is written into the NAND type flash memory. A typical example of such a writing method is fuzzy-fine programming operation. Even in this case, it is necessary to save the write data until the program operation of multiple stages is completed, so it is necessary to prepare the same number of write buffers as the number of write target blocks.

In the fuzzy-fine programming operation, for example, the first write data of a plurality of pages is transferred to the NAND flash memory, and the first write data is written into the initial physical page (memory cells connected to a word line) group) (write in the first stage: fuzzy write). Thereafter, fuzzy writing is performed on other physical pages (memory cell groups connected to other word lines) adjacent to the initial physical page. Then, the first write data of the plurality of pages is transferred to the NAND flash memory again, and the first write data is written to the initial physical page (writing in the second stage: fine writing) . Thereafter, fine writing is performed on the other physical pages.

However, since the capacity of the random access memory in the flash memory device 3 is limited, there are cases where it is difficult to prepare a sufficient number of write buffers on the random access memory in the flash memory device 3 . Also, even if the flash memory device 3 has a large-capacity random access memory, if the number of end users who share the flash memory device 3 is small, the large-capacity random access memory will be wasted.

Therefore, in this embodiment, a specific storage area on the memory of the host computer 2 is used as a write buffer (hereinafter referred to as UWB: Unified Write Buffer (unified write buffer)) 2A. The UWB 2A on the host 2 side includes a plurality of write buffer areas corresponding to a plurality of write target blocks.

The host 2 stores the write data to be written in one write target block in UWB2A (the write buffer area corresponding to the write target block). Moreover, the host 2 sends to the flash memory device 3 a write request including an identifier (block identifier or stream ID) and storage location information, the identifier is associated with the write target block, and the storage The location information indicates the location in UWB 2A where the written data is stored.

The flash memory device 3 receives the write request from the host 2, and stores the identifier and storage location information. The flash memory device 3 acquires the write data from the UWB 2A by sending a transfer request including the storage location information to the host 2 when writing the write data into the NAND flash memory. For example, in the case where the NAND-type flash memory is a TLC (Trinary-Level Cell, three-level storage unit)-flash memory that stores 3 bits of data in each memory cell, the 3 bits written to the same physical page are obtained from UWB2A. Page amount of written data. It is also possible to assign three page addresses to one physical page. Furthermore, the flash memory device 3 writes the write data into a write target block (a physical page of the write target block).

The flash memory device 3 can also write the write data into a write target block through a full sequence programming operation.

Alternatively, the flash memory device 3 can also be programmed by a multi-stage programming operation (such as a fuzzy-fine programming operation) accompanied by multiple transfers of write data (for example, three pages of write data) to the NAND flash memory. The write data is written into a write target block. In this case, the flash memory device 3 first executes the first-stage write operation. Thereafter, when it is time to execute the write operation of the second stage, the flash memory device 3 again sends a transfer request including the storage location information to the host 2 . The host 2 transfers the write data from the UWB 2A to the flash memory device 3 whenever receiving a transfer request including the storage location information from the flash memory device 3 . When the write data is acquired from UWB2A again, the flash memory device 3 executes the write operation of the second stage.

In the flash memory device 3, when the writing of the write data is completed and the write data becomes readable from the NAND flash memory (in the case of the end of the full sequence programming operation in the full sequence programming operation, In the fuzzy-fine programming operation, when both the fuzzy write operation and the fine write operation are completed), the host 2 is notified that the write data stored in the UWB 2A is redundant.

Therefore, in this embodiment, a plurality of write target blocks can be used simultaneously without preparing a plurality of write buffers in the flash memory device 3 . Therefore, there is no need to provide a large-capacity random access memory in the flash memory device 3 , thereby easily increasing the number of end users who share the flash memory device 3 without increasing the cost of the flash memory device 3 .

FIG. 2 shows a configuration example of the flash memory device 3 .

The flash memory device 3 includes a controller 4 and a nonvolatile memory (NAND type flash memory) 5 . The flash memory device 3 may also have random access memory, such as DRAM (dynamic random access memory, dynamic random access memory) 6 .

The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a two-dimensional structured NAND flash memory, or may be a three-dimensional structured NAND flash memory.

The memory cell array of the NAND flash memory 5 includes a plurality of blocks BLK0 to BLKm-1. Each of the blocks BLK0 to BLKm-1 is organized by a plurality of pages (here, pages P0 to Pn-1). The blocks BLK0 to BLKm-1 function as deletion units. Blocks may also be called "deleted blocks", "physical blocks", or "physically deleted blocks". Each of pages P0 to Pn-1 includes a plurality of memory cells connected to the same word line. The pages P0 to Pn−1 may also be called “physical pages”. Pages P0 to Pn-1 are units of data writing operation and data reading operation.

The controller 4 is electrically connected to a NAND-type flash memory 5 as a nonvolatile memory via a flip-flop and a flash memory programming controller 13 such as an Open NAND Flash Interface (ONFI). The controller 4 operates as a memory controller configured to control the NAND flash memory 5 . The controller 4 can also be realized by a circuit such as a System-on-a-chip (SoC, system-on-a-chip).

The NAND flash memory 5 may also include a plurality of NAND flash memory chips (NAND flash memory bare chips) as shown in FIG. 3 . Each NAND flash memory chip can operate independently. Therefore, the NAND flash memory chip functions as a unit capable of operating in parallel. FIG. 3 exemplifies the case where 16 channels Ch.1 to Ch.16 are connected to the flash memory programming controller 13, and two NANDs are connected to each of the 16 channels Ch.1 to Ch.16. type flash memory chips. In this case, 16 NAND flash memory chips #1 to #16 connected to channels Ch.1 to Ch.16 are organized into bank #0, and the remaining 16 chips connected to channels Ch.1 to Ch.16 NAND flash memory chips #17-#32 are organized into bank #1. The bank functions as a unit that allows a plurality of memory modules to operate in parallel by interleaving the banks. In the configuration example shown in FIG. 3, a maximum of 32 NAND flash memory chips can be operated in parallel by interleaving 16 channels and using two banks.

The deletion operation can also be performed in units of one block (physical block), or in units of super blocks including a collection of multiple physical blocks that can be operated in parallel. One super block may include a total of 32 physical blocks selected from NAND flash memory chips #1 to #32, but the present invention is not limited thereto. In addition, each of the NAND flash memory chips #1 to #32 may have a multiplane configuration. For example, in the case where each of the NAND flash memory chips #1 to #32 has a multi-plane configuration including two planes, one super block may also include the slaves and the NAND flash memory chips #1 to #32. A total of 64 physical blocks are selected for each of the corresponding 64 planes.

In Fig. 4, there are 32 physical blocks (here, physical block BLK2 in NAND flash memory chip #1, physical block BLK3 in NAND flash memory chip #2, NAND flash memory chip Physical block BLK7 in #3, physical block BLK4 in NAND type flash memory chip #4, physical block BLK6 in NAND type flash memory chip #5, ... in NAND type flash memory chip #32 A super block (SB) of the physical block BLK3).

The writing target block can also be a physical block or a super block. In addition, a configuration in which one super block only includes one physical block may also be used. In this case, one super block is equivalent to one physical block.

Next, the configuration of the controller 4 in FIG. 1 will be described.

The controller 4 includes a host interface 11 , a CPU 12 , a flash memory programming controller 13 , and a DRAM interface 14 . These CPU 12 , flash memory program controller 13 , and DRAM interface 14 are connected to each other via a bus 10 .

The host interface 11 is a host interface circuit configured to communicate with the host 2 . The host interface 11 can also be, for example, a PCIe controller (NVMe controller). Alternatively, in a configuration in which the flash memory device 3 is connected to the host 2 via Ethernet (registered trademark), the host interface 11 may also be an NVMe over Fabrics (NVMeOF) controller. The configuration in which the flash memory device 3 is connected to the host computer 2 via Ethernet (registered trademark) can easily increase the number of flash memory devices 3 as needed. Furthermore, the number of hosts 2 can also be easily increased.

The host interface 11 receives various requests (commands) from the host 2 . These requests (commands) include write requests (write commands), read requests (read commands), and various other requests (commands).

The CPU 12 is a processor configured to control the host interface 11 , the flash memory program controller 13 , and the DRAM interface 14 . CPU 12 loads a control program (firmware) into DRAM 6 from NAND flash memory 5 or ROM (not shown) in response to power-on of flash memory device 3 , and executes the firmware to perform various processes. In addition, the firmware may be loaded on a not-shown SRAM in the controller 4 . The CPU 12 can execute command processing and the like for processing various commands from the host computer 2 . The operation of the CPU 12 is controlled by the firmware executed by the CPU 12 . In addition, part or all of command processing may be executed by dedicated hardware within the controller 4 .

The CPU 12 can function as a block identifier/buffer address receiving unit 21 , a transfer request sending unit 22 , and a notification unit 23 .

The block identifier/buffer address receiving unit 21 receives a write request including a block identifier and a buffer address from the host 2, and stores the block identifier and buffer address in a specific storage area. The block identifier included in the write request can also be a block address specifying a specific write target block. Alternatively, the write request may also include the stream ID instead of the block identifier. The block identifier or stream ID functions as an identifier associated with one write target block. The buffer address included in the write request is storage location information indicating a location in UWB 2A where data to be written (write data) is stored. Alternatively, the write request may also include an offset within the buffer as storage location information instead of the buffer address. The offset in the buffer indicates the offset position in the UWB 2A where the write data is stored.

When writing the write data into the NAND-type flash memory 5, the transfer request sending unit 22 sends a transfer request including storage location information (such as a buffer address) to the host 2, thereby obtaining the write data from the UWB 2A. .

The notification unit 23 notifies the host 2 that the write data stored in the UWB 2A has changed when the writing of the write data is completed and the write data can be read from the NAND flash memory 5 . as redundant.

The flash memory program controller 13 is a memory control circuit configured to control the NAND flash memory 5 under the control of the CPU 12 .

The DRAM interface 14 is a DRAM control circuit configured to control the DRAM 6 under the control of the CPU 12 . Part of the storage area of the DRAM 6 is used to store a read buffer (RB) 30 , a write buffer (WB) 31 , a block management table 32 , and a defect information management table 33 . Note that these read buffer (RB) 30 , write buffer (WB) 31 , block management table 32 and defect information management table 33 may be stored in a not-shown SRAM in the controller 4 . The block management table 32 manages whether the data stored in each block is valid data or invalid data. The bad information management table 33 manages a list of bad blocks.

FIG. 5 shows the relationship between a plurality of write target blocks and a plurality of write buffer areas corresponding to a plurality of end users.

In the flash memory device 3 , the states of blocks are roughly divided into valid blocks storing valid data and free blocks not storing valid data. Each block that is a valid block is managed by a list called a valid block pool. On the other hand, blocks that are free blocks are managed by a list called a free block pool.

In this embodiment, the controller 4 allocates a plurality of blocks (free blocks) selected from the free block pool as write target blocks to which write data received from the host 2 should be written. In this case, the controller 4 first performs a delete operation on each of the selected blocks (free blocks), thereby putting each block into a writable delete state. A block set to a write-enabled delete state is called an open write target block. When a write target block is completely filled with write data from the host 2, the controller 4 moves the write target block to the valid block pool, and allocates a new block (free block) from the free block pool as the new write target block.

In the flash memory device 3 , the same number or more write target blocks (flash memory blocks) as the end users (end user terminals) sharing the flash memory device 3 are opened. The UWB 2A on the host 2 side may include the same number of write buffer areas (UWB areas) as these write target blocks (flash memory blocks).

In FIG. 5 , the write buffer area #1 is associated with the write target block #1, and all data to be written in the write target block #1 is stored in the write buffer area #1. The write buffer area #2 is associated with the write target block #2, and all data to be written into the write target block #2 is stored in the write buffer area #2. The write buffer area #3 is associated with the write target block #3, and all data to be written into the write target block #4 is stored in the write buffer area #3. Similarly, the write buffer area #n is associated with the write target block #n, and all data to be written in the write target block #n is stored in the write buffer area #n.

Host 2 stores write data from end user terminal #1 in write buffer area #1, stores write data from end user terminal #2 in write buffer area #2, and stores write data from end user terminal #3 in write buffer area #2. Write data is stored in write buffer area #3, write data from end user terminal #4 is stored in write buffer area #4, and write data from end user terminal #n is stored in write buffer Area #n.

The host 2 sends to the flash memory device 3 a write request including an identifier and storage location information, the identifier is associated with the write target block #1, and the storage location information indicates that the data from the end user terminal #1 is stored. The location within the write buffer area #1 where the data is written. The identifier associated with the write target block #1 may also be a block identifier (block address) specifying the write target block #1, or may be a string associated with the write target block #1 Stream ID.

The flash memory device 3 acquires write data corresponding to the size of one physical page from the write buffer area #1 by sending a transfer request including the storage location information to the host 2 (for example, in the TLC-flash memory's In the case of 3 pages of written data). In addition, the transmission request may include not only storage location information, but also an identifier associated with the write target block #1 (for example, a block identifier specifying the write target block #1, or a block identifier associated with the write target block #1). Block #1 establishes the associated stream ID). Thus, the host 2 can easily specify the write buffer area in which the write data to be transferred to the flash memory device 3 is stored and the position (storage position) in the write buffer area.

The host computer 2 sends to the flash memory device 3 a write request including an identifier and storage location information, the identifier is associated with the write target block #2 (for example, the block identification for specifying the write target block #2 character, or a stream ID associated with the write target block #2), the storage location information indicates the location in the write buffer area #2 where the write data from the end user terminal #2 is stored.

The flash memory device 3 acquires write data corresponding to the size of 1 physical page from the write buffer area #2 by sending a transfer request including the storage location information to the host computer 2 (for example, in the case of TLC-flash memory The following is the write data of 3 pages). In addition, the transfer request may not only include storage location information, but may also include an identifier associated with the write target block #2 (for example, a block identifier specifying the write target block #2, or a block identifier associated with the write target block #2). Block #2 establishes the associated stream ID). Thus, the host 2 can easily specify the write buffer area storing the write data to be transferred to the flash memory device 3 and the position (storage position) in the write buffer area.

Similarly, the host computer 2 sends to the flash memory device 3 a writing request including an identifier and storage location information, the identifier is associated with the writing target block #n (for example, the area designated for writing the target block #n Block identifier, or stream ID associated with the write target block #n), the storage location information indicates the location in the write buffer area #n where the write data from the end user terminal #n is stored.

The flash memory device 3 acquires write data corresponding to the size of 1 physical page from the write buffer area #n by sending a transfer request including the storage location information to the host 2 (for example, in the case of TLC-flash memory The following is the write data of 3 pages). In addition, the transfer request may include not only storage location information, but also an identifier associated with the write target block #n (for example, a block identifier specifying the write target block #n, or a block identifier associated with the write target block #n). Block #n establishes the associated stream ID). Thus, the host 2 can easily specify the write buffer area in which the write data to be transferred to the flash memory device 3 is stored and the position (storage position) in the write buffer area.

FIG. 6 shows the relationship between the storage device 3 and the host-side UWB 2A and the data writing process performed by the host 2 and the flash memory device 3 .

Here, in order to simplify the illustration, the data writing process to a certain write target block BLK is exemplified and described. In addition, it is assumed here that write data is written into one write target block BLK through a full-sequence programming operation.

(1) The host computer 2 executes a flash memory manager which is host software that manages the flash memory device 3 . The flash memory manager can also be incorporated in the device driver for the flash memory device 3 . The flash memory manager manages UWB2A. In response to a data write request from upper-level software (application program or file system), the flash memory manager stores a write request accompanied by data to be written, a label, and a block identifier in UWB2A. A tag is an identifier that can identify the data. A label can also be a logical address such as a Logical Block Address (LBA, Logical Block Address), a key of a key-value store, or a document identifier such as a document name. The block identifier is the block address to be written into the target block BLK. In addition, the write request may include the length (Length) of the data to be written, and the write request may not include the length (Length) when writing of write data of a fixed length is requested. In addition, the write request may also include a page address indicating a page to which data should be written. Also, the host software may issue the write request, and the flash memory manager receives the write request from the host software, and stores the received write request in UWB2A.

(2) The flash memory manager sends out a write request (write command) to the flash memory device 3 . The write request includes a tag, a block identifier (block address), and a buffer address (or buffer offset). The buffer address indicates the location in UWB 2A where write data is stored. In addition, the write request may also include a page address indicating a page to which data should be written. The controller 4 of the flash memory device 3 receives the write request, and saves the tag, block identifier, and buffer address (or offset in the buffer) included in the write request.

(3) When the flash memory programming controller 13 writes the data into the write target block BLK, the controller 4 of the flash memory device 3 sends a transfer request (Transfer Request) to the host 2. The transfer request contains the saved buffer address (or offset within the buffer). Alternatively, the transfer request may also include the stored tag and the stored buffer address (or offset in the buffer). Alternatively, the transfer request may also include the stored buffer address (or offset in the buffer), and the stored block identifier (block address).

(4) When the flash memory manager of the host computer 2 receives a transfer request containing at least the buffer address (or offset in the buffer), it will store the data in the address specified by the buffer address (or offset in the buffer). Data for locations within UWB2A is transferred from UWB2A to flash memory device 3 . For example, in the case where the NAND-type flash memory 5 is a TLC-flash memory, 3 pages worth of data are transferred from the UWB 2A to the flash memory device 3 . The transfer request may also contain the length of the data to be transferred.

(5) The controller 4 of the flash memory device 3 receives the data, and transfers the data to the NAND type flash memory 5 via the flash memory programming controller 13, and writes the data into the write target block BLK . In the case of writing three pages of data into a certain physical page through a full sequence programming operation, the flash memory programming controller 13 sequentially transfers three pages of data to the page buffer in the NAND flash memory 5 group, and then send a write instruction to the NAND flash memory 5 . The flash memory programming controller 13 can monitor the state from the NAND flash memory 5 to determine whether the writing operation (full sequence programming operation) is completed.

(6) When the writing operation ends and the data (here, data of 3 pages) can be read, that is, when the full sequence programming operation succeeds and ends, the controller 4 notifies the host computer 2 to save the data in the UWB2A The data (here, data corresponding to 3 pages) becomes unnecessary. In this case, the controller 4 of the flash memory device 3 may also send a write completion (Write Done) including the label, page address, and length to the host 2, or send an invalidation request (invalidate Request) to the host 2 . The invalidation request includes a buffer address (or buffer internal offset) storing readable data. Alternatively, the invalidation request may include a tag of readable data and a buffer address (or offset within the buffer) in which readable data is stored. Alternatively, when the full-sequence programming operation to the last physical page of the write target block BLK ends and the write target block BLK is completely filled with data, the controller 4 notifies the host computer 2 of the write target area The UWB area corresponding to the block BLK becomes redundant. In this case, the controller 4 sends a close request (Close Request) to the host 2. The shutdown request may also include a block identifier (block address) written into the target block BLK. In the case of receiving a close request including the block identifier of the write-in target block BLK, the flash memory manager of the host computer 2 opens the UWB area associated with the write-in target block BLK, and the UWB area for other purposes. In this case, the flash memory manager may reuse the opened UWB area as a UWB area for another write target block (for example, a newly opened write target block).

FIG. 7 shows an example of the relationship between a plurality of write target blocks and a plurality of write buffer areas (UWB areas).

The write buffer area (UWB area #1) corresponding to a write target block BLK#1 may also include a plurality of storage areas for temporarily storing data of a plurality of pages, for example. In this case, each storage area may include a label field, a legal/illegal field, a data storage field, and a page address field. The label field stores the label of the corresponding data. The legal/illegal field holds a legal/illegal flag indicating whether the corresponding data must be saved. The data storage field stores data to be written into the write target block BLK#1. A data storage field may also have a size of 1 page amount. The page address field is an optional field, and if the write request includes a page address, the page address is stored in the page address field.

When notified from the flash memory device 3 that the data stored in the UWB area #1 becomes unnecessary, the host computer 2 (flash memory manager) updates the valid/illegal flag in the storage area corresponding to the data to Indicates an invalid value. The storage area in which the legitimate/illegal flag is updated to a value indicating invalidity is reused for storing other data to be written in the write target block BLK#1.

The data structure of the UWB area shown in FIG. 7 is an example, and for example, data (write data) having a size different from the page size may be managed in the UWB area.

FIG. 8 shows the relationship between the flash memory device 3 and the host-side UWB 2A and data read processing performed by the host 2 and the flash memory device 3 .

(1) In response to a request to read data from upper-level software, the flash memory manager of the host computer 2 sends a read request to the flash memory device 3 to read the data. The read request may also include, for example, a tag, a block identifier (block address), a page address, and a length.

(2) If the write operation of the data specified by the read request to the write target block BLK has been completed and the data can be read, the controller 4 of the flash memory device 3 will This data is read from the write target block BLK.

(3) The controller 4 of the flash memory device 3 sends the read data to the host 2 together with the data tag.

(3') If the data specified by the read request cannot be read, that is, a read request for reading the data is received from the host 2 during the period from when the data is written to when the data can be read. In the case of , the controller 4 of the flash memory device 3 sends to the host 2 a transfer request to send back the data from the UWB 2A as a response to the read request. The transfer request, as information capable of specifying the data in the UWB2A that should be transferred, may also include a buffer address corresponding to the data, or a buffer address corresponding to the data and a block identifier corresponding to the data. both. Alternatively, the transmission request may also include a tag corresponding to the data, and may also include a block identifier and a page address corresponding to the data.

(4') The flash memory manager of the host computer 2 reads the data from the UWB2A, and sends the read data back to the host software together with the data tag.

Alternatively, the flash memory manager of the host computer 2 directly reads the data from the UWB2A in response to a request from the host software to read the data before the flash memory device 3 notifies that the data stored in the UWB2A becomes redundant. No read request is issued to the flash memory device 3 . In this case, the data reading process is performed as follows.

(1″) Before the flash memory device 3 notifies that certain data stored in the UWB 2A becomes redundant, the flash memory manager of the host computer 2 responds to a request for reading the data from the host software, and sends the read request The data is sent to UWB 2A and read from UWB 2A. The read request may include, for example, a tag, a buffer address, and a length.

(2") The flash memory manager sends the data read from UWB2A back to the host software together with the tag of the data.

FIG. 9 shows the relationship between the flash memory device 3 supporting fuzzy-fine writing and the host-side UWB 2A, and the data writing process performed by the host 2 and the flash memory device 3 .

Here, it is assumed that write data is written into one write target block BLK through a write operation (fuzzy-fine programming operation) in multiple stages.

(1) In the host computer 2, the flash memory manager stores in UWB 2A a write request accompanied by data to be written, a label, and a block identifier in response to a data write request from upper-level software. In addition, the write request may include the length (Length) of the data to be written, and the write request may not include the length (Length) when writing of write data of a fixed length is requested. In addition, the write request may also include a page address indicating a page to which data should be written. In addition, the write request may be issued by the host software, and the write request may be received by the flash memory manager from the host software, and the received write request may be stored in UWB2A.

(2) The flash memory manager sends out a write request (write command) to the flash memory device 3 . The write request includes a tag, a block identifier (block address), and a buffer address (or buffer offset). In addition, the write request may also include a page address indicating a page to which data should be written. The controller 4 of the flash memory device 3 receives the write request, and saves the tag, block identifier, and buffer address (or offset in the buffer) included in the write request.

(3) When the flash memory programming controller 13 starts the writing operation (fuzzy writing) of the first stage of the data, the controller 4 of the flash memory device 3 sends a transfer request (Transfer Request) to the host computer 2. The transfer request contains the saved buffer address (or offset within the buffer). Alternatively, the transfer request may also include the stored tag and the stored buffer address (or offset in the buffer). Alternatively, the transfer request may also include the stored buffer address (or offset in the buffer) and the stored block identifier (block address).

(4) When the flash memory manager of the host computer 2 receives a transfer request containing at least the buffer address (or offset in the buffer), it will store the data in the address specified by the buffer address (or offset in the buffer). The data of the position within UWB2A (here, illustrated as “Foggy Data”) is transferred from UWB2A to flash memory device 3 . For example, when the NAND-type flash memory 5 is a TLC-flash memory, three pages of data are transferred from the UWB 2A to the flash memory device 3 as Foggy Data. The transfer request may also contain the length of the data to be transferred.

(5) The controller 4 of the flash memory device 3 receives the data, and transfers the data to the NAND type flash memory 5 via the flash memory programming controller 13, thereby writing the data into the write target block BLK The write target physical page (the first phase of writing: fuzzy writing). When 3 pages of data are written to a certain write target physical page by fuzzy writing, the flash memory programming controller 13 sequentially transfers 3 pages of data to the NAND flash memory 5. page buffer group, and send the write instruction of the first stage to the NAND flash memory 5 . The flash memory programming controller 13 can determine whether the writing operation (the writing operation of the first stage) is completed by monitoring the status from the NAND flash memory 5 . Generally, the fuzzy-fine programming action is used to reduce programming interference, such as fuzzy writing of physical page #1, fuzzy writing of physical page #2, fine writing of physical page #1, and fine writing of physical page #2 The method is executed repeatedly on multiple word lines (multiple physical pages).

(6) When the timing of executing the second-stage writing (fine writing) to the write target physical page arrives, the controller 4 of the flash memory device 3 obtains the data to be written by the fine writing (the same data as the data already written by fuzzy writing), and send a transfer request (Transfer Request) to the host 2 again. This transfer request includes the stored buffer address, that is, the same buffer address as the buffer address included in the transfer request sent in the process (3).

(7) When the flash memory manager of the host computer 2 receives a transfer request containing at least a buffer address (or an offset in the buffer), it will store the data in the address specified by the buffer address (or offset in the buffer). Data of a position within UWB2A (here, illustrated as “Fine Data”) is transferred from UWB2A to flash memory device 3 . Fine Data is the same data as Foggy Data. For example, when the NAND-type flash memory 5 is a TLC-flash memory, the data for the three pages is transferred from the UWB 2A to the flash memory device 3 as Fine Data. The transfer request may also contain the length of the data to be transferred. In addition, the host 2 does not need to recognize that the data to be transferred is either Foggy Data or Fine Data.

(8) The controller 4 of the flash memory device 3 receives the data, and transfers the data to the NAND type flash memory 5 via the flash memory programming controller 13, thereby writing the data into the write target block BLK The write target physical page (the second phase of writing: fine writing). When writing 3 pages of data into the write target physical page by fine writing, the flash memory programming controller 13 writes the same 3 pages of data as the 3 pages of data used in fuzzy writing The data in the NAND flash memory 5 are sequentially transferred to the page buffer group in the NAND flash memory 5 , and the second-stage write instruction is sent to the NAND flash memory 5 . The flash memory programming controller 13 can determine whether the write operation (the write operation of the second stage) is completed by monitoring the status from the NAND flash memory 5 .

(9) When the writing operation of the second stage ends and the data (here, data of 3 pages) can be read, that is, when the fuzzy-fine programming operations are all successful and terminated, the controller 4 The host 2 notifies that the data stored in the UWB 2A (here, 3 pages of data) is redundant. In this case, the controller 4 of the flash memory device 3 may also send a write completion (Write Done) including the label, page address, and length to the host 2, or send an invalidation request (invalidate Request) to the host 2 . The invalidation request includes a buffer address (or buffer internal offset) storing readable data. Alternatively, the invalidation request may include a tag of readable data and a buffer address (or offset within the buffer) in which readable data is stored. Alternatively, when the fuzzy-fine programming operation on the last physical page of the write target block BLK ends and the write target block BLK is completely filled with data, the controller 4 notifies the host 2 of the write target The UWB area corresponding to the block BLK becomes redundant. In this case, the controller 4 sends a close request (Close Request) to the host 2. The shutdown request may also include a block identifier (block address) written into the target block BLK. When receiving a close request including a block identifier of the write target block BLK, the flash memory manager of the host computer 2 opens the UWB area associated with the write target block BLK to open the UWB area. used for other purposes. In this case, the flash memory manager may reuse the opened UWB area as a UWB area for another write target block (for example, a newly opened write target block).

FIG. 10 shows the relationship between the flash memory device 3 supporting fuzzy-fine writing and the UWB 2A on the host side, and the data read processing performed by the host 2 and the flash memory device 3 .

(1) In response to a request to read data from upper-level software, the flash memory manager of the host computer 2 sends a read request to the flash memory device 3 to read the data. The read request may include, for example, a tag, a block identifier (block address), a page address, and a length.

(2) If the write operation of the data designated by the read request to the write target block BLK is completed and the data can be read, that is, both of the fuzzy write of the data and the fine write of the data After finishing, the controller 4 of the flash memory device 3 reads out the data from the writing target block BLK via the flash memory programming controller 13 .

(3) The controller 4 of the flash memory device 3 sends the read data to the host 2 together with the data tag.

(3') If the data specified by the read request cannot be read, that is, a read request for reading the data is received from the host 2 during the period from when the data is written to when the data can be read. In the case of , the controller 4 of the flash memory device 3 sends to the host 2 a transfer request to send back the data from the UWB 2A as a response to the read request. The transfer request may also include a buffer address corresponding to the data.

(4') The flash memory manager of the host computer 2 reads the data from the UWB2A, and sends the read data back to the host software together with the data tag.

Alternatively, the flash memory manager of the host computer 2 directly reads the data from the UWB2A in response to a request from the host software to read the data before the flash memory device 3 notifies that the data stored in the UWB2A becomes redundant. No read request is issued to the flash memory device 3 . In this case, the data reading process is performed as follows.

(1″) Before the flash memory device 3 notifies that the data stored in the UWB 2A becomes redundant, the flash memory manager of the host computer 2 sends a read request in response to a request for reading the data from the host software. The data is read from UWB 2A to UWB 2A. The read request may include, for example, a tag, a buffer address, and a length.

(2") The flash memory manager sends the data read from UWB2A back to the host software together with the tag of the data.

The sequence diagram of FIG. 11 shows the steps of the data writing process performed by the host 2 and the flash memory device 2 .

Host 2 stores the data (write data) that should be written into a certain write target block in the UWB area associated with the write target block, and will include the block identifier and buffer address (or buffer address) Inner offset) write request is sent to the flash memory device 3 (step S11). The block identifier is the block address of the write target block where the write data should be written. The buffer address indicates the location in the UWB area where the write data is stored.

The controller 4 of the flash memory device 3 receives the write request from the host 2, and saves the block identifier and the buffer address (or offset in the buffer) in the write request (step S21). In this case, the controller 4 may store the block identifier and the buffer address by storing the block identifier and the buffer address in the write buffer 31 on the DRAM 6 .

When the write target block specified by the saved block identifier writes the write data corresponding to the write request, the controller 4 of the flash memory device 3 will include the saved buffer address (or buffer Inner offset) transmission request is sent to the host 2 (step S22).

When the host 2 receives the transfer request, the host 2 transfers the write data from the UWB area to the flash memory device 3 (step S12).

The controller 4 of the flash memory device 3 receives the write data transmitted from the host 2 (step S23). The controller 4 saves the received write data by storing the received write data in, for example, the write buffer 31 on the DRAM 6 (step S24).

The controller 4 transfers the received write data to the NAND type flash memory 5 (step S25). The controller 4 stores the written data until the transfer of the written data to the NAND flash memory 5 is completed. And, the controller 4 writes the write data into the write target block specified by the stored block identifier (step S26 ). In this case, the controller 4 determines the write target page in the write target block where the write data should be written. In addition, the write request may also include a page address specifying the write target page.

When the writing operation of the writing data is completed and the writing data can be read (in the case of the completion of the full-sequence programming operation in the full-sequence programming operation), the controller 4 notifies the host computer 2 of the data stored in the UWB area. The write data of becomes redundant (step S27).

The flowchart of FIG. 12 shows the steps of notification processing performed by the flash memory device 3 .

The controller 4 of the flash memory device 3 can determine whether the writing operation of the data written into the target block is completed and the data can be read (step S31 ).

If the writing operation of the data ends and the data can be read (Yes in step S31), the controller 4 determines whether the writing operation to the last page (the last physical page) of the writing target block ends and the writing operation ends. All of the target blocks are filled with data (step S32).

If there are remaining physical pages (unwritten physical pages) that can be used in the write target block (No in step S32), the controller 4 changes the readable data stored in the UWB area to the host 2. For redundancy, a write completion (Write Done) or an invalidation request (invalidate Request) is sent to the host 2 (step S33).

If the write operation to the last page (last physical page) of the write target block ends and the entire write target block is filled with data (Yes in step S32), then the controller 4 notifies the host computer 2 with The entire UWB area corresponding to the write target block becomes redundant, and a close request (Close Request) is sent to the host computer 2 (step S34).

The flowchart of FIG. 13 shows the steps of host-side processing executed upon receipt of a transfer request.

The host 2 sends a write request including the block identifier and the buffer address (or offset in the buffer) to the flash memory device 3 (step S40). The host 2 judges whether or not a transfer request has been received from the flash memory device 3 (step S41).

If a transfer request is received from the flash memory device 3 (Yes in step S41), the host 2 transfers the data stored in the location within the UWB area specified by the buffer address (or offset within the buffer) in the transfer request. to the flash memory device 3 (step S42). Also, the host computer 2 determines whether the flash memory device 3 is notified of excess data in the UWB area, or whether a close request (Close Request) is received from the flash memory device 3 (steps S43, S44).

If the redundant data in the UWB region is notified from the flash memory device 3 (yes of step S43), the host computer 2 will update the legal/illegal flag corresponding to the redundant data to a value representing invalidity, and store the redundant data in the A storage area in the UWB area is opened (step S44). The host 2 can reuse this open storage area as a storage area for writing new write data into the write target block corresponding to the UWB area.

Thus, in the present embodiment, when the write operation of certain data is completed and the data can be read, it is unnecessary to notify the host 2 of the data in the UWB area from the flash memory device 3 . Therefore, the data is stored in the UWB area until the data can be read from the NAND flash memory 5 .

If a closing request (Close Request) is received from the flash memory device 3 (Yes in step S45), the host computer 2 will open all the UWB areas associated with the writing target block of the block identifier contained in the closing request (step S46). The host 2 can reuse the opened UWB area as a UWB area newly allocated by the flash memory device 3 for writing the target block.

The flowchart of FIG. 14 shows the steps of the data read operation performed by the flash memory device 3 upon receipt of a read request.

The controller 4 of the flash memory device 3 receives a readout request from the host 2 (step S51). The controller 4 determines whether or not the read data designated by the read request is data that can be read after the write operation to the write target block has been completed (step S52 ).

If the data to be read is data that can be read after the write operation to the write target block is completed (Yes in step S52), the controller 4 reads the data to be read from the NAND flash memory 5. (step S53), and send the read data back to the host computer 2 (step S54).

On the other hand, if the data to be read is not the data that can be read after the write operation to the write target block is completed, that is, from the host computer during the period from when the data is written to when the data can be read 2. Upon receiving the readout request for the data (No in step S52), the controller 4 sends to the host computer 2 a transfer request to send back the data from the UWB area as a response to the readout request (step S52: S55).

The flowchart of Fig. 15 shows the steps of host-side processing for data readout.

Regardless of whether there is data to be read in the UWB area or not, the host 2 sends a read request to the flash memory device 3 to read the data (step S61).

Furthermore, the host 2 judges whether or not a transfer request for returning (reading) the data from the UWB area has been received from the flash memory device 3 (step S62).

If the transfer request is received from the flash memory device 3 (YES at step S62), the host 2 reads out the data from the UWB area (step S63).

FIG. 16 shows the relationship between the flash memory device 3 supporting streaming writing and the host-side UWB 2A, and the data writing process performed by the host 2 and the flash memory device 3 .

Here, it is assumed that write data is written into one write target block BLK by a full-sequence programming operation.

(1) In the host computer 2, according to the request for writing data from the host software (application program or file system), the flash memory manager writes the data to be written, stream ID, LBA, and length Requests are stored in UWB2A. The stream ID is an identifier of a certain stream among the multiple streams associated with the multiple write target blocks. In addition, the host software may issue the write request, and the flash memory manager may receive the write request from the host software and store the received write request in UWB2A.

(2) The flash memory manager sends out a write request (write command) to the flash memory device 3 . The write request includes stream ID, LBA, length, buffer address (or buffer offset). The buffer address indicates the location in UWB2A where the data to be written is stored. The controller 4 of the flash memory device 3 receives the write request, and saves the stream ID, LBA, length, and buffer address included in the write request.

(3) When the flash memory programming controller 13 writes the data into the write target block BLK, the controller 4 of the flash memory device 3 sends a transfer request (Transfer Request) to the host 2. The transfer request contains the saved buffer address (or offset within the buffer). Alternatively, the transfer request may also include the saved LBA and the saved buffer address (or offset in the buffer). Alternatively, the transfer request may also include the saved buffer address (or offset in the buffer) and the saved stream ID. Alternatively, the transfer request may also include the saved buffer address (or offset in the buffer) and the block identifier (block address) of the write target block associated with the saved stream ID.

(4) When the flash memory manager of the host computer 2 receives a transfer request containing at least the buffer address (or offset in the buffer), it will store the data in the address specified by the buffer address (or offset in the buffer). Data for locations within UWB2A is transferred from UWB2A to flash memory device 3 . For example, in the case where the NAND-type flash memory 5 is a TLC-flash memory, three pages worth of data are transferred from the UWB 2A to the flash memory device 3 . The transfer request contains the length of the data that should be transferred.

(5) The controller 4 of the flash memory device 3 receives the data, and transfers the data to the NAND type flash memory 5 via the flash memory programming controller 13, thereby writing the data into the write target block BLK . In the case of writing three pages of data into physical pages by a full sequence programming operation, the flash memory programming controller 13 sequentially transfers three pages of data to the page buffer group in the NAND flash memory 5 , and sends a write command to the NAND flash memory 5 . The flash memory programming controller 13 can determine whether the writing operation (full sequence programming operation) is completed by monitoring the status from the NAND type flash memory 5 .

(6) When the writing operation ends and the data (here, data of 3 pages) can be read, that is, when the full sequence programming operation succeeds and ends, the controller 4 notifies the host computer 2 to save the data in the UWB2A The data (here, data corresponding to 3 pages) becomes redundant. In this case, the controller 4 of the flash memory device 3 may also send a write completion (Write Done) including the LBA and length to the host 2, or send an invalidation request (invalidate Request) to the host 2. The invalidation request includes a buffer address (or buffer internal offset) storing readable data. Alternatively, the invalidation request may include the LBA of the readable data and the buffer address (or offset in the buffer) in which the readable data is stored. Alternatively, when the full-sequence programming operation to the last physical page of the write target block BLK ends and the write target block BLK is completely filled with data, the controller 4 notifies the host computer 2 of the write target area The UWB area corresponding to the block BLK becomes redundant. In this case, the controller 4 sends a close request (Close Request) to the host 2. The shutdown request may also include a block identifier (block address) written into the target block BLK. When receiving a close request including a block identifier of the write target block BLK, the flash memory manager of the host computer 2 opens the UWB area associated with the write target block BLK to open the UWB area. used for other purposes. In this case, the flash memory manager may reuse the opened UWB area as a UWB area for another write target block (for example, a newly opened write target block).

FIG. 17 shows the relationship between a plurality of stream IDs and a plurality of write target blocks associated with these stream IDs.

Here, it is exemplified that the write target block BLK#1 is associated with the stream of stream ID#1, the write target block BLK#2 is associated with the stream of stream ID#2, and the write target block BLK #3 is associated with the stream of stream ID #3, and the write target block BLK#n is associated with the stream of stream ID #n.

The write data specified by the write request including the stream ID#1 is written into the write target block BLK#1. The write data specified by the write request including the stream ID#2 is written into the write target block BLK#2. The write data specified by the write request including the stream ID#3 is written into the write target block BLK#3. The write data specified by the write request including the stream ID #n is written to the write target block BLK #n.

FIG. 18 shows the relationship between the flash memory device 3 supporting streaming writing and the host-side UWB 2A, and data read processing performed by the host 2 and the flash memory device 3 .

(1) The flash memory manager of the host computer 2 sends out the read request for reading data to the flash memory device 3 in response to a request for reading data from upper-level software. The read request may include, for example, LBA and length.

(2) If the write operation of the data specified by the read request to the write target block BLK has been completed and the data can be read, the controller 4 of the flash memory device 3 program the controller 4 via the flash memory 13 Read the data from the write target block BLK.

(3) The controller 4 of the flash memory device 3 sends the read data to the host 2 together with the LBA of the data.

(3') If the data specified by the read request cannot be read, that is, a read request for reading the data is received from the host 2 during the period from when the data is written to when the data can be read. In the case of , the controller 4 of the flash memory device 3 sends to the host 2 a transfer request to send back the data from the UWB 2A as a response to the read request. The transfer request may also include a buffer address corresponding to the data.

(4') The flash memory manager of the host 2 reads the data from the UWB2A, and sends the read data back to the host software together with the LBA of the data.

Alternatively, the flash memory manager of the host computer 2 may directly read the data from UWB2A in response to a request from the host software to read the data before the flash memory device 3 notifies that the data stored in UWB2A becomes redundant. This data is sent out to the flash memory device 3 without a read request. In this case, the data reading process is performed as follows.

(1″) Before the flash memory device 3 notifies that the data stored in the UWB 2A becomes redundant, the flash memory manager of the host computer 2 sends a read request in response to a request for reading the data from the host software. The data is read from UWB 2A to UWB 2A. The read request may include, for example, LBA and length.

(2") The flash memory manager sends the data read from UWB2A back to the upper software together with the LBA of the data.

The sequence diagram of FIG. 19 shows the steps of data writing processing performed by the flash memory device 3 supporting fuzzy-fine writing and the host computer 2 .

Here, the case where the write request includes the block identifier and the buffer address (or offset in the buffer) is exemplified for description.

Host 2 stores the data (write data) that should be written into a certain write target block in the UWB area associated with the write target block, and will include the block identifier and buffer address (or buffer address) Inner offset) write request is sent to the flash memory device 3 (step S71). The block identifier is the block address of the write target block where the write data should be written. The buffer address indicates the location in the UWB area where the write data is stored.

The controller 4 of the flash memory device 3 receives the write request from the host 2, and saves the block identifier and the buffer address (or offset in the buffer) in the write request (step S81). In this case, the controller 4 may store the block identifier and the buffer address by storing the block identifier and the buffer address in the write buffer 31 on the DRAM 6 .

When the write data corresponding to the write request is written into the write target block specified by the stored block identifier through multi-stage programming operations (fuzzy-fine programming operations), the flash memory The controller 4 of the device 3 first sends a transfer request including the saved buffer address (or offset in the buffer) to the host in order to obtain the write data (fuzzy data) used for fuzzy writing from the UWB area. 2 (step S82).

When the host 2 receives the transfer request, the host 2 transfers the write data from the UWB area to the flash memory device 3 (step S72).

The controller 4 of the flash memory device 3 receives the write data transferred from the host 2 as obfuscated data (step S83). The controller 4 saves the received write data (fuzzy data) by storing it in, for example, the write buffer 31 or the like on the DRAM 6 (step S84).

The controller 4 transfers the received write data (fuzzy data) to the NAND type flash memory 5 (step S85). The controller 4 saves the written data (fuzzy data) until the transfer of the written data (fuzzy data) to the NAND flash memory 5 is completed. And, the controller 4 writes the write data (fuzzy data) into the write target physical page of the write target block specified by the saved block identifier (writing in the first stage: fuzzy write) (step S86).

Thereafter, when the timing to execute the second stage of writing (fine writing) to the write target physical page comes, the controller 4 of the flash memory device 3 uses the write data for fine writing to acquire from the UWB area. input data (fine data), and send the transfer request including the saved buffer address (or offset in the buffer) to the host 2 again (step S87). The fine data is the same data as the fuzzy data.

When the host 2 receives the transfer request, the host 2 transfers the write data from the UWB area to the flash memory device 3 (step S73).

The controller 4 of the flash memory device 3 receives the write data transmitted from the host 2 as fine data (step S88). The controller 4 saves the received write data (fine data) by storing it in, for example, the write buffer 31 or the like on the DRAM 6 (step S89 ).

The controller 4 transfers the received write data (fine data) to the NAND type flash memory 5 (step S90). The controller 4 holds the write data (fine data) until the transfer of the write data (fine data) to the NAND type flash memory 5 is completed. And, the controller 4 writes the writing data (fine data) into the writing target physical page of the writing target block (writing in the second stage: fine writing) (step S91 ).

When the write operation is completed and the write data can be read (that is, when both the fuzzy write operation and the fine write operation are completed), the controller 4 notifies the host 2 of the data stored in the UWB area. Writing data becomes unnecessary (step S92).

FIG. 20 shows a configuration example of the host computer 2 (information processing device).

The host 2 includes a processor (CPU, Central Processing Unit, central processing unit) 101, a main memory 102, a BIOS (Basic Input Output System, basic input and output system)-ROM (Read-Only Memory, read-only memory) 103, a network A controller 105, a peripheral interface controller 106, a controller 107, an embedded controller (EC, Embedded Controller) 108, and the like.

The processor 101 is a CPU configured to control the operation of each component in the information processing device. The processor 101 executes various programs on the main memory 102 . The main memory 102 is constituted by a random access memory such as DRAM. The programs executed by the processor 101 include an application software layer 41, an operating system (OS, Operating System) 42, a file system 43, a device driver 44, and the like.

Various applications run on the application software layer 41 . As is generally known, the OS 42 is software configured to manage the entire information processing device, control hardware in the information processing device, and execute control for enabling the software to use the hardware and the flash memory device 3 . The file system 43 is used to control file operations (creation, storage, update, deletion, etc.).

The device driver 44 is a program for controlling and managing the flash memory device 3 . The device driver 44 contains the flash memory manager. The flash memory manager 45 includes a command group for managing the UWB 2A on the main memory 102, a command group for sending a write request, a read request, etc. to the flash memory device 3, and every time the slave flash memory device 3 A command group for transferring data from the UWB2A to the flash memory device 3 when a transfer request is received, and a command group for reading the data from the UWB2A until the flash memory device 3 notifies that the data stored in the UWB2A becomes redundant wait. The processor 101 executes a command group of the flash memory manager 45 in the device driver 44 to execute data writing processing, data reading processing, UWB area opening processing, and the like.

The network controller 105 is a communication device such as an ethernet controller. The peripheral interface controller 106 is configured to perform communication with peripheral devices such as USB (Universal Serial Bus, Universal Serial Bus) devices.

The controller 107 is configured to perform communication with devices respectively connected to the plurality of connectors 107A. In this embodiment, a plurality of flash memory devices 3 may be respectively connected to a plurality of connectors 107A. Controller 107 can also be SAS (serial attached Small Computer System Interface, serial connection small computer system interface) expander (expander), PCIe Switch (switch), PCIe expander, flash memory array controller, or RAID (Redundant Arrays ofIndependent Disks, redundant array of independent disks) controller. Alternatively, a plurality of flash memory devices 3 may be connected to the network controller 105 via ethernet.

The flowchart of FIG. 21 shows the steps of the data writing process executed by the processor 101 .

In the data writing process, the processor 101 stores write data to be written in one write target block in UWB2A (the UWB area corresponding to the write target block) (step S101 ). The processor 101 sends a write request including an identifier and storage location information to the flash memory device 3. The identifier is associated with the write target block, and the storage location information indicates the location in UWB2A that stores the write data. position (position without UWB area) (step S102). The identifier associated with the write target block may be the block identifier (block address) of the write target block as described above. The storage location information may also be a buffer address (or an offset within the buffer) as described above. In this case, the processor 101 may also send a write request including a tag, a block identifier, and a buffer address (or offset in the buffer) to the flash memory device 3 . In addition, in the configuration in which the host 2 designates not only a block but also a page, the write request may include a tag, a block identifier (block address), a page address, and a buffer address (or buffer internal offset).

Alternatively, when using stream writing, a stream ID may be used instead of the block identifier (block address). In this case, the write request may also include the stream ID, LBA, and buffer address (or offset within the buffer).

After the processor 101 sends the write request to the flash memory device 3, whenever the processor 101 receives a transfer request containing the buffer address (or offset in the buffer) from the flash memory device 3, the The write data is transferred from UWB2A (UWB area) to flash memory device 3 (steps S103, S104). More specifically, the processor 101 determines whether or not a transfer request including a buffer address (or offset within the buffer) has been received from the flash memory device 3 (step S103). Also, if the transfer request is received from the flash memory device 3 (YES at step S103 ), the processor 101 transfers the write data from UWB2A (UWB area) to the flash memory device 3 .

As described above, when the write data is written into the write target block through the multi-stage programming operation (fuzzy-fine programming operation), the processor 101 receives multiple times from the flash memory device 3 Transfer request for buffer address (or offset within the same buffer). Also, processor 101 transfers the write data from UWB2A (UWB area) to flash memory device 3 every time the transfer request is received.

The flowchart of FIG. 22 shows the steps of the data reading process executed by the processor 101 .

Before being notified from the flash memory device 3 that the data stored in the UWB2A (UWB area) becomes redundant, the processor 101 reads the data from the UWB2A (UWB area) in response to a request for reading the data from the upper software. output, and send the read data back to the host software.

That is, if data reading is requested from the host software (Yes in step S111), the processor 101 determines whether the flash memory device 3 has notified that the data on UWB2A (UWB area) becomes redundant (step S112).

If it has not been notified that the data becomes redundant (No in step S112), the processor 101 reads the data from UWB2A (UWB area), and sends the read data back to the upper software (step S112).

On the other hand, if it has been notified that the data becomes redundant (Yes in step S112), the processor 101 sends out a read request for reading the data to the flash memory device 3, thereby transferring the data from the flash memory device 3 to the flash memory device 3. The memory device 3 is read (step S114).

The flowchart of FIG. 23 shows other steps of the data reading process executed by the processor 101 .

If a request to read data is received from the host software (Yes in step S121), the processor 101 does not care whether the data exists in UWB2A (UWB area), that is, whether or not the data change has been notified from the flash memory device 3. For redundancy, a read request for reading the data is sent to the flash memory device 3 (step S122).

If the data designated by the read request cannot be read yet, the flash memory device 3 sends to the host 2 a transfer request requesting to return the data from UWB2A (UWB area).

If the transmission request is received from the flash memory device 3 (yes in step S123), the processor 101 reads the data from UWB2A (UWB area), and sends the read data back to the host software (step S124 ).

If the transfer request is not received from the flash memory device 3 (No in step S123), the processor 101 receives the data sent back from the flash memory device 3 as a response to the read request, and sends the data back to Host software (step S125).

The flowchart of FIG. 24 shows the procedure of the UWB area opening process executed by the processor 101 .

When the processor 101 receives from the flash memory device 3 a notification (shutdown request) indicating that the entire UWB area associated with one write target block becomes redundant (Yes in step S131), the processor 101 sets the The entire UWB area is opened (step S132). In step S132, the processor 101 may use the memory space corresponding to the open UWB area for other arbitrary purposes. For example, the processor may also reuse the open UWB area as a UWB area associated with a write target block newly allocated by the controller 4 of the flash memory device 3 . When data must be written in the newly allocated write target block, the processor 101 first stores the data in the UWB area associated with the newly allocated write target block, and will contain the identifier (area Block identifier (or stream ID) and the write request of storage location information (such as buffer address) are sent to the flash memory device 3, and the identifier is associated with the newly allocated write target block, and the storage location The information indicates the location within the UWB area where the data is stored.

As described above, according to the present embodiment, the controller 4 of the flash memory device 3 receives from the host 2 information including the first identifier (block identifier, or stream ID) and storage location information (buffer address, or address in the buffer), the first identifier is associated with a write target block, and the storage location information indicates the write buffer on the memory of the host 2 that stores the first data to be written (UWB2A) location. Then, when writing the first data into the NAND flash memory 5, the controller 4 sends a transfer request including storage location information to the host 2 to acquire the first data from the write buffer (UWB2A). Therefore, data necessary for the write operation can be acquired from the write buffer (UWB2A) of the host computer 2, so that the number of write target blocks that can be used simultaneously can be increased without preparing a large number of blocks in the flash memory device 3. write buffer. Thus, the number of end users sharing the flash memory device 3 can be easily increased without causing an increase in the cost of the flash memory device 3 .

In addition, when the writing of the first data is completed and the first data can be read from the NAND flash memory 5, the controller 4 notifies the host 2 that the first data stored in the write buffer (UWB2A) has become superfluous. Based on this notification, the host 2 discards the data as necessary. Therefore, until the data to be written can be read from the NAND flash memory 5, the controller 4 may repeatedly acquire the data from the write buffer (UWB2A) if necessary. Therefore, even when performing a multi-stage programming operation such as a fuzzy-fine programming operation, the controller 4 can acquire necessary data from the write buffer (UWB2A) every time the programming operation of each stage is started.

In addition, in this embodiment, a NAND flash memory is exemplified as a nonvolatile memory. However, the functions of this embodiment can also be applied to, for example, MRAM (Magnetoresistive Random Access Memory, magnetoresistive random access memory), PRAM (Phase change Random Access Memory, phase change random access memory), ReRAM (Resistive Random Access Memory , resistive random access memory), or FeRAM (Ferroelectric Random Access Memory, ferroelectric random access memory) such other various non-volatile memories.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope or gist of the invention, and are included in the invention described in the claims and their equivalents.

[explanation of the symbol]

2 host

2A write buffer

3 Flash memory devices

4 controllers

5 NAND flash memory

21 block identifier/buffer address receiving unit

22 Transmission Request Sending Department

23 Notify the Ministry.

Claims (18)

1. A memory system capable of being connected to a host and having: a non-volatile memory including a plurality of blocks each as a unit of deletion; and a controller configured in such a way that it is electrically connected to the non-volatile memory and controls the non-volatile memory; and The controller is constituted in the following manner, that is, receiving a write request from the host that includes storage location information indicating a location within a write buffer on a memory of the host where the first data is stored, When writing the first data into the non-volatile memory through a multi-stage programming operation, In each of the plurality of stages of programming actions, acquiring the first data from the write buffer by sending a transfer request including the storage location information to the host, transferring the first data to the non-volatile memory, Writing the first data to a writing target block among the plurality of blocks. 2. The memory system according to claim 1, wherein the controller is configured such that, during a period from when the first data is written to when the first data can be read from When the host receives a read request to read the first data, it sends an acquisition request to the host to acquire the first data from the write buffer. 3. The memory system of claim 1 , wherein the write buffer comprises a plurality of write buffer areas corresponding to the plurality of blocks, and The controller is configured to notify the host of the write buffer corresponding to the one write target block when all of the one write target block is filled with data. The write buffer area in the device becomes redundant. 4. The memory system of claim 1, wherein the write request includes a block identifier specifying a write target block. 5. The memory system according to claim 1, wherein the plurality of blocks are respectively associated with a plurality of streams, and The write request includes an identifier of a stream within the plurality of streams. 6. The memory system of claim 1 , wherein the write buffer comprises a plurality of write buffer areas corresponding to the plurality of blocks, and The transfer request includes the identifier of the write target block and the storage location information. 7. The memory system according to claim 1, wherein the controller is configured in such a manner that the programming operations in the plurality of stages are completed and the first data can be read from the nonvolatile memory. In case of output, it is unnecessary to notify the host that the first data stored in the write buffer becomes unnecessary. 8. The memory system of claim 1 , wherein the non-volatile memory further comprises a page buffer, and The controller is configured to transfer the first data to the page buffer of the nonvolatile memory. 9. The memory system of claim 1 , wherein each of the plurality of blocks comprises a group of memory cells connected to a word line, and The controller is constituted in the following manner, that is, In the programming action of the first stage among the programming actions of the plurality of stages, acquiring the first data from the write buffer by sending a transfer request including the storage location information to the host, transferring the first data to the non-volatile memory, writing the first data into the memory cell group connected to the word line of the write target block; In the programming action of the second stage among the programming actions of the plurality of stages, reacquiring the first data from the write buffer by sending a transfer request including the storage location information to the host, retransmitting the first data to the non-volatile memory, rewriting the first data to the memory cell group connected to the word line of the write target block. 10. A control method for controlling a nonvolatile memory, the nonvolatile memory including a plurality of blocks each as a unit of a deletion action, the control method having: receiving a write request from the host that includes storage location information indicating a location within a write buffer on a memory of the host where the first data is stored; When writing the first data into the non-volatile memory through a multi-stage programming operation, In each of the plurality of stages of programming actions, acquiring the first data from the write buffer by sending a transfer request including the storage location information to the host, transferring the first data to the non-volatile memory, Writing the first data to a writing target block among the plurality of blocks. 11. The control method according to claim 10 , further comprising: when receiving from the host a command to read the first data during the period from when the first data is written until the first data can be read. When a read request of the first data is issued, an acquisition request to acquire the first data from the write buffer is issued to the host. 12. The control method according to claim 10, wherein the write buffer includes a plurality of write buffer areas corresponding to the plurality of blocks, and The control method further includes: notifying the host of the write data in the write buffer corresponding to the one write target block when the whole of the one write target block is full of data. The input buffer area becomes redundant. 13. The control method according to claim 10, wherein the write request includes a block identifier specifying a write target block. 14. The control method according to claim 10, wherein the plurality of blocks are respectively associated with a plurality of streams, and The write request includes an identifier of a stream within the plurality of streams. 15. The control method according to claim 10, wherein the write buffer includes a plurality of write buffer areas corresponding to the plurality of blocks, and The transfer request includes the identifier of the write target block and the storage location information. 16. The control method according to claim 10, further comprising: when the programming operation of the plurality of stages is completed and the first data can be read from the nonvolatile memory, the The host notifies that the first data stored in the write buffer becomes unnecessary. 17. The control method according to claim 10, wherein the non-volatile memory further comprises a page buffer, and The first data is transferred to the page buffer of the nonvolatile memory. 18. The control method according to claim 10, wherein each of the plurality of blocks includes a memory cell group connected to a word line, In the programming action of the first stage among the programming actions of the plurality of stages, acquiring the first data from the write buffer by sending a transfer request including the storage location information to the host, transferring the first data to the non-volatile memory, writing the first data into the memory cell group connected to the word line of the write target block; In the programming action of the second stage among the programming actions of the plurality of stages, reacquiring the first data from the write buffer by sending a transfer request including the storage location information to the host, retransmitting the first data to the non-volatile memory, rewriting the first data to the memory cell group connected to the word line of the write target block.

Images