CN116072664A

CN116072664A - Package structure and method for forming the same

Info

Publication number: CN116072664A
Application number: CN202211464723.8A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Biren Intelligent Technology Co Ltd
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-05-05

Abstract

The embodiment of the disclosure provides a packaging structure and a forming method thereof, wherein the packaging structure comprises: a first die and a second die; and a package connection member including a bridge die and an encapsulation layer; the package connection member is arranged on one side of the first die and one side of the second die in a first direction perpendicular to the main surfaces of the first die and the second die, and is electrically connected to the first die and the second die, the bridge die at least comprises a first interconnection structure, the first interconnection structure comprises a first organic dielectric structure and a first rerouting structure, and the first rerouting structure is embedded in the first organic dielectric structure and is used for electrically connecting the first die to the second die; the encapsulation layer is disposed on the sides of the bridge die in a second direction parallel to the major surfaces of the first die and the second die and encapsulates at least the sidewalls of the bridge die.

Description

Package structure and method for forming the same

Technical Field

Embodiments of the present disclosure relate to a package structure and a method of forming the same.

Background

Semiconductor packaging techniques may integrate multiple chips together, for example, a system on chip (SoC) and a memory chip may be integrated together to provide High bandwidth to the system chip and to enable High-performance operations (HPC). However, how to reduce manufacturing costs, reduce signal loss, and improve power integrity in packaging processes remains a problem facing current packaging technologies.

Disclosure of Invention

There is provided, in accordance with at least one embodiment of the present disclosure, a package structure including: a first die and a second die; and a package connection member including a bridge die and an encapsulation layer, the package connection member being disposed on one side of the first die and the second die in a first direction perpendicular to a major surface of the first die and the second die and being electrically connected to the first die and the second die, wherein the bridge die includes at least a first interconnect structure including a first organic dielectric structure and a first rerouting structure embedded in the first organic dielectric structure and for electrically connecting the first die to the second die; and the encapsulation layer is arranged on the side edge of the bridging die in a second direction parallel to the main surfaces of the first die and the second die, and encapsulates at least the side wall of the bridging die.

In the package structure provided according to at least one embodiment of the present disclosure, the package connection member further includes: and the conductive columns are positioned on the side edges of the bridging die in the first direction and laterally encapsulated by the encapsulation layer, wherein the conductive columns provide electrical connection between the first die and the second die and an external conductive connecting piece.

In the package structure provided according to at least one embodiment of the present disclosure, further includes: and a second interconnect structure disposed between the bridge die, the encapsulation layer, the conductive pillars, and the first and second dies in the first direction, and the second interconnect structure comprising a second organic dielectric structure and a second redistribution structure embedded in the second organic dielectric structure, wherein the first and second dies are electrically connected to each other through a first portion of the second redistribution structure and the bridge die, and electrically connected to the conductive pillars through a second portion of the second redistribution structure.

In a package structure provided according to at least one embodiment of the present disclosure, a pitch of a rerouting layer in the first rerouting structure is smaller than a pitch of a rerouting layer in the second rerouting structure.

In a package structure provided according to at least one embodiment of the present disclosure, the first organic dielectric structure and the first re-wiring structure include at least one organic dielectric layer and at least one re-wiring layer stacked on each other, a first re-wiring layer of the at least one re-wiring layer includes a seed layer and a conductive layer, and an orthographic projection of the seed layer on a main surface of the first organic dielectric structure in the first direction is located within an orthographic projection range of the conductive layer on the main surface of the first organic dielectric structure in the first direction.

In accordance with at least one embodiment of the present disclosure, there is provided a package structure wherein, in the second direction, the sidewalls of the seed layer are laterally recessed with respect to the sidewalls of the conductive layer.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the conductive layer has sidewalls in contact with the at least one organic dielectric layer.

In the package structure provided according to at least one embodiment of the present disclosure, the first organic dielectric structure includes a first organic dielectric layer and a second organic dielectric layer; the first rerouting structure includes an initial rerouting layer and a first rerouting layer, the initial rerouting layer being embedded in the first organic dielectric layer, and the first rerouting layer extending through the first organic dielectric layer to connect to the initial rerouting layer; the first redistribution layer includes a via portion in the first organic dielectric layer and a trace portion in the second organic dielectric layer, wherein a major surface of the second organic dielectric layer is closer to the first die and the second die than a major surface of the trace portion of the second redistribution layer.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the organic dielectric structure includes a polymer material.

In an encapsulation structure provided according to at least one embodiment of the present disclosure, the encapsulation layer includes an organic dielectric material.

In a package structure provided according to at least one embodiment of the present disclosure, a surface of the first interconnection structure of the bridge die, which is remote from the first die and the second die, is flush with a surface of the encapsulation layer, which is remote from the first die and the second die, in the second direction.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the bridge die further includes a substrate, the substrate is located on a side of the first interconnect structure away from the first die and the second die, and a portion of the encapsulation layer is located on a side of the substrate in the second direction.

In a package structure provided according to at least one embodiment of the present disclosure, the substrate includes a semiconductor substrate or an insulating substrate.

In the package structure provided according to at least one embodiment of the present disclosure, further includes: and the passive device die is embedded in the packaging connecting member, is arranged side by side with the bridging die in the second direction, is laterally encapsulated by the encapsulating layer, and is electrically connected with at least one of the first die and the second die.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the passive device die includes a deep trench capacitor.

In the package structure provided according to at least one embodiment of the present disclosure, further includes: the conductive connecting piece is arranged on one side of the packaging connecting member, which is far away from the first die and the second die, and is electrically connected to the first die and the second die through the packaging connecting member; and the packaging substrate is arranged on one side of the conductive connecting piece far away from the packaging connecting member and is electrically connected to the first die and the second die through the conductive connecting piece and the packaging connecting member.

At least one embodiment of the present disclosure provides a method for forming a package structure, including: providing a first die and a second die; and forming a package connection member to be electrically connected to the first die and the second die, the package connection member being disposed on one side of the first die and the second die in a first direction perpendicular to main surfaces of the first die and the second die, wherein forming the package connection member includes: forming a bridge die, the bridge die including at least a first interconnect structure including a first organic dielectric structure and a first rerouting structure embedded in the first organic dielectric structure and configured to electrically connect the first die to the second die; and forming an encapsulation layer formed on sides of the bridge die in a second direction parallel to the major surfaces of the first die and the second die to encapsulate sidewalls of the bridge die.

In a method for forming a package structure provided according to at least one embodiment of the present disclosure, forming the bridge die includes: providing a substrate; and forming the first interconnection structure on the substrate, wherein forming the first interconnection structure comprises: forming an initial organic dielectric layer on the substrate, and forming an initial rerouting layer on a side of the initial organic dielectric layer remote from the substrate; forming a first organic dielectric layer having an opening on a side of the initial organic dielectric layer and the initial re-wiring layer away from the substrate, the opening exposing a portion of a surface of the initial re-wiring layer away from the substrate; forming a seed layer on the first organic dielectric layer, and the seed layer filling into the opening to contact the initial redistribution layer; forming a conductive layer on a first portion of the seed layer; and removing a second portion of the seed layer not covered by the conductive layer, and the remaining first portion of the seed layer and the conductive layer constitute a first redistribution layer electrically connected to the initial redistribution layer.

In a method for forming a package structure provided according to at least one embodiment of the present disclosure, forming the conductive layer on the first portion of the seed layer includes: forming a patterned mask layer having a mask opening over the seed layer to cover the second portion of the seed layer and the mask opening exposing the first portion of the seed layer; and forming the conductive layer on the first portion of the seed layer in the mask opening.

In a method for forming a package structure provided according to at least one embodiment of the present disclosure, removing the second portion of the seed layer not covered by the conductive layer includes: removing the patterned mask layer; and taking the conductive layer as an etching mask, and carrying out an etching process on the seed crystal layer.

In the method for forming the package structure provided in accordance with at least one embodiment of the present disclosure, the method further includes: the substrate of the bridge die is removed and the first interconnect structure and the encapsulation layer of the bridge die are made to have surfaces that are flush with each other in the second direction on a side away from the first die and the second die.

In the method for forming a package structure provided according to at least one embodiment of the present disclosure, forming the package connection member further includes: before forming the encapsulation layer, forming a conductive pillar, wherein the conductive pillar is disposed at a side of the bridge die in the second direction, and the encapsulation layer is formed to also encapsulate a sidewall of the conductive pillar.

In the method for forming a package structure provided according to at least one embodiment of the present disclosure, forming the package connection member further includes: forming a second interconnect structure on a side of the bridge die, the conductive pillars, and the encapsulation layer proximate to the first die and the second die, the second interconnect structure including a second organic dielectric structure and a second redistribution structure embedded in the second organic dielectric structure, wherein the first die and the second die are electrically connected to the bridge die and the conductive pillars through the second redistribution structure.

In the method for forming a package structure according to at least one embodiment of the present disclosure, before forming the encapsulation layer, the method further includes: a passive device die is provided, the passive device die and the bridge die being disposed side-by-side in the second direction, and the encapsulation layer being formed to also encapsulate sidewalls of the passive device die.

In the method for forming the package structure provided in accordance with at least one embodiment of the present disclosure, the method further includes: forming a conductive connection on a side of the package connection member remote from the first die and the second die; and electrically connecting the conductive connecting piece to the packaging substrate.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1A and 1B illustrate schematic cross-sectional views of package structures according to some embodiments of the present disclosure.

Fig. 2A and 2B illustrate schematic cross-sectional views of package structures according to further embodiments of the present disclosure; fig. 2C illustrates a schematic plan view of a package structure according to some embodiments of the present disclosure.

Fig. 3A-3P illustrate schematic cross-sectional views of methods of forming a bridge die according to some embodiments of the present disclosure.

Fig. 4A-4G illustrate schematic cross-sectional views of methods of forming package structures according to some embodiments of the present disclosure.

Fig. 5A-5B illustrate schematic cross-sectional views of methods of forming package structures according to further embodiments of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Referring to fig. 1A, in some embodiments, a package structure 50a includes a die 10, a die 20a, a die 20b, a package connection member 9a, an encapsulation layer 12, and external connections 15. The

dies

10, 20a and 20b are disposed on one side of the package connection member 9a and are surrounded by the encapsulation layer 12, and the connectors 15 are disposed on the opposite side of the package connection member 9a from the

dies

10a, 20a and 20 b. The plurality of

dies

10, 20a, 20b are electrically connected to each other by the package connection member 9a, and may be further connected to the external connection 15 by the package connection member 9 a. The package structure 50a may be further connected to other package members through the external connection 15.

In some embodiments, the package connection member 9a may be an interposer (interposer), and includes, for example, a substrate 1, a through substrate via (through substrate via, TSV) 2, and an interconnect structure 6. The substrate 1 may be a semiconductor substrate, for example a silicon substrate. An interconnect structure 6 is provided on a side of the substrate 1 near the die and may include a dielectric structure 3 and conductive traces 5 embedded in the dielectric structure 3. The conductive traces 5 provide electrical connection between the dies and the substrate via 2; that is, the

dies

10, 20a, 20b are electrically connected to each other through some portions of the conductive traces 5 in the interposer and to the external connection 15 through other portions of the conductive traces 5 in the interposer and the substrate vias 2. In some embodiments, the dielectric structure 3 comprises an inorganic dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof; the conductive trace 5 may comprise a metallic material such as copper and may be formed in the dielectric structure 3 by a damascene process, such as a damascene (damascene) process. In some embodiments, passive devices (passive devices), such as capacitors (not shown), may also be included in the interposer.

Referring to fig. 1B, a package structure 50B is similar to the package structure 50a, except that in the package structure 50B, a package connection member 9B includes a bridge die (bridge die) 8, an encapsulation structure MS, and a plurality of conductive members 7a and 7B. The plurality of dies 10, 20a, 20b are electrically connected to each other by bridging die 8 and conductive member 7a, and to conductive connector 15 by conductive member 7b. In some embodiments, the bridge die 8 is, for example, a die formed based on a semiconductor substrate (e.g., a silicon substrate), and may include conductive traces 8b embedded in a dielectric structure 8a to provide electrical connections between different dies. The dielectric structure 8a may comprise an inorganic dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The conductive trace 8b may comprise a metal material such as copper, and the conductive trace 8b may be formed in the dielectric structure 8a by a damascene process (e.g., a dual damascene process). The encapsulation structure MS surrounds the encapsulated bridge die 8 and the plurality of conductive members 7a and 7b. The encapsulation structure MS may include an organic dielectric material such as a polymer, for example, the encapsulation structure MS may be a molding compound (molding compound). In some embodiments, the bridge die 8 includes only the substrate and the interconnect structures for electrical connection, without additional active or passive devices.

In the

package structures

50a and 50b, the dies 10, 20a, 20b are integrated together by an interposer or package connection member that includes a bridge die; for example, die 10 is a system on chip (SoC), and die 20a and 20b are memory dies, such as high bandwidth memory (high bandwidth memory, HBM) chips. However, in the embodiment of fig. 1A using the interposer as the package connection member, the interposer is formed from a silicon substrate of a larger size, and the interconnection structure 6 is formed by a semiconductor process including a damascene process, which makes the manufacturing cost higher, and the line width of the formed conductive trace 5 is smaller, which may cause a larger signal loss (signal loss); on the other hand, when the interposer includes passive devices such as capacitors, larger-sized silicon interposers may generate larger capacitor leakage currents, thereby affecting the yield of the package structure. In the embodiment of fig. 1B using a bridge die as a package connection member, conductive traces in the bridge die are formed in the inorganic dielectric structure using a damascene process, which makes it possible to limit the fabrication of the bridge die 8 to a silicon wafer fabrication facility, thereby limiting the supply chain of the bridge die 8 to some extent; the line width of the conductive wire formed by the embedding process is smaller, the signal loss is larger, and the performance of the device is further affected; on the other hand, the dielectric structure 8a and the encapsulation structure MS in the bridge die 8 are made of an inorganic dielectric material and an organic dielectric material, respectively, and the thermal expansion coefficients of the two materials are greatly different, so that warpage of the encapsulation structure may be caused by mismatch of the thermal expansion coefficients, and additional stress is generated on components in the encapsulation structure. On the other hand, in the package structure 50b, no capacitor is provided in the package connection member including the bridge die, which may affect the Power Integrity (PI) of the package structure to some extent.

In order to solve the above-described problems, further embodiments of the present disclosure provide a package structure including a plurality of dies and a package connection member, and a method of manufacturing the same. The package connection member provides interconnection between the plurality of dies and electrical connection between the plurality of dies and an external member, e.g., the package connection member includes a bridge die and an encapsulation layer. The bridge die includes at least an interconnect structure for making electrical connection between the plurality of dies, e.g., the interconnect structure includes a re-routing structure embedded in a dielectric structure. In some embodiments, the interconnect structure of the bridge die employs an organic dielectric material to form the dielectric structure, and the process of forming the re-wiring structure includes forming a seed layer using a sputtering process and forming a conductive layer on the seed layer using a plating (e.g., electroplating) process, the re-wiring layer in the re-wiring structure formed using this process may have a larger line width/line spacing and/or thickness than the conductive traces formed using a damascene process in fig. 1A and 1B (e.g., conductive trace 5 of interconnect structure 6 in fig. 1A and conductive trace 8B of bridge die 8 in fig. 1B), thereby reducing signal loss and, for example, may facilitate high-speed signal transmission, thereby improving device performance. Herein, the "line width" refers to the width of a trace or a wiring or the like in a direction perpendicular to the extending direction thereof, and the "pitch" refers to the distance between the centers of adjacent traces or wirings, and may also be referred to as a line center-to-center spacing.

On the other hand, the interconnection structure in the bridging tube core adopts an organic dielectric structure, and the encapsulating layer also comprises an organic dielectric material, and the thermal expansion coefficients of the two are similar, so that the mismatch of the thermal expansion coefficients of the dielectric structure in the interconnection structure and the encapsulating layer can be avoided or reduced, and further the problem of warping of the encapsulating structure and the like caused by the mismatch of the thermal expansion coefficients can be avoided or reduced. In addition, in the present embodiment, the dielectric structure in the interconnection structure of the bridge die is made of an organic dielectric material, and the redistribution layer is formed in the dielectric structure by the above-mentioned process including sputtering and plating, and the manufacturing process of the interconnection structure can be completed at the end of the semiconductor package and test (outsourced semiconductor assembly and testing, OSAT), so that the supply chain of the bridge die of the present embodiment can be more flexible and the manufacturing cost can be lower.

Additionally, passive device die (e.g., including capacitors) may also be provided in the package connection members to improve the power integrity of the device; moreover, compared with the passive device integrated in the silicon interposer in fig. 1A, the passive device die of the present embodiment may be embedded in the encapsulation layer and may be disposed separately from the bridge die side by side, and during the packaging process, a good passive device die is selected for packaging, so that the situation that the whole packaging connection member fails due to the leakage current generated by the passive device such as the capacitor, which may occur in the embodiment shown in fig. 1A, may be avoided, and thus the product yield may be better controlled and improved.

Fig. 2A and 2B illustrate schematic cross-sectional views of package structures according to some embodiments of the present disclosure, and fig. 2C illustrates a schematic top view of package structures according to some embodiments of the present disclosure. It should be understood that some of the components in the package structure are shown in fig. 2C for simplicity.

Referring to fig. 2A and 2C, in some embodiments, package structure 200 includes a plurality of dies (e.g., dies 120 and 122), package connection members 110, encapsulation layer 126, and conductive connections 130. The package connection member 110 is located on one side of the dies 120 and 122 in a direction perpendicular to the main surfaces of the dies 120 and 122 (e.g., direction D1), and is used to integrate the plurality of dies 120 and 122 together. The encapsulation layer 126 is located on a side of the package connection member 110 near the dies 120 and 122 in the direction D1 and surrounds the plurality of dies 120 and 122. The conductive connection 130 is located on a side of the package connection member 110 remote from the plurality of dies 120 and 122, and is electrically connected to the package connection member 110. For example, the package connection member 110 may provide electrical connections between the plurality of dies 120 and 122 and the conductive connection 130. That is, the plurality of dies 120 and 122 are electrically connected to each other through the package connection member 110, and may be connected to the conductive connection member 130 through the package connection member 110, and may be further connected to other package members, such as a package substrate, through the conductive connection member 130.

In some embodiments, die 120 and die 122 may also be referred to as a first die and a second die, respectively; it should be understood that the number of dies shown in the figures is merely illustrative, and the present disclosure is not so limited. The plurality of dies may each be any suitable type of die, for example, may each be selected from a system on chip (SoC), a memory chip, or other type of chip, and the plurality of dies may be or include the same type or different types of dies. For example, die 120 may be a system chip and include logic circuitry and input-output circuitry; die 122 is, for example, a memory die, and in some examples, a high bandwidth memory (high bandwidth memory, HBM) chip, although the disclosure is not so limited. The plurality of dies 120 and 122 are disposed side-by-side with one another in a direction D2 that intersects (e.g., is substantially perpendicular to) the direction D1. The dimensions of the plurality of dies 120 and 122 may be the same or different from one another, and the disclosure is not so limited.

In some embodiments, the package connection member 110 includes a bridge die BD, conductive pillars 105, an encapsulation layer 106, and an interconnect structure 108. The plurality of dies 120 and 122 are electrically connected to each other through the interconnect structure 108 and the bridge die BD, and electrically connected to the conductive connection 130 through the interconnect structure 108 and the conductive pillars 105. The bridge die BD is disposed on one side of the plurality of dies 120 and 122 in the direction D1, and may overlap (e.g., partially overlap) the plurality of dies 120 and 122. For example, the orthographic projection of the bridge die BD onto the main surface of the package connection member 110 in the direction D1 coincides with the orthographic projection portion of the plurality of dies 120 and 122 onto the main surface of the package connection member 110 in the direction D1. The bridge die BD is used to provide electrical interconnection between the plurality of dies 120 and 122.

In some embodiments, the bridge die BD includes a substrate 80 and an interconnect structure 88. The substrate 80 may be a semiconductor substrate or an insulating substrate. For example, the substrate 80 may be a silicon substrate, a glass substrate including silicon oxide, or an insulating substrate including an organic dielectric material. Interconnect structure 88 is located on a side of substrate 80 adjacent to the plurality of dies 120 and 122 and may include an organic dielectric structure OS1 and a redistribution structure RS1. The re-wiring structure RS1 is embedded in the organic dielectric structure OS1 and is used to provide electrical connection between the plurality of dies 120 and 122.

Fig. 3K illustrates a schematic cross-sectional view of a bridge die BD according to some embodiments of the present disclosure.

Referring to fig. 2A and 3K, in some embodiments, in the bridge die BD, the organic dielectric structure OS1 and the rerouting structure RS1 of the interconnect structure 88 include at least one organic dielectric layer and at least one rerouting layer stacked on top of each other. For example, the organic dielectric structure OS1 includes a plurality of organic dielectric layers 81, 82, 83, 84 (e.g., sequentially stacked in the direction D1), and the re-wiring structure RS1 includes a plurality of re-wiring layers RL1, RL2, RL3, RL4 (e.g., sequentially stacked in the direction D1). The plurality of organic dielectric layers 81-84 and the plurality of re-wiring layers RL1-RL4 are alternately stacked with each other, for example, the re-wiring layer RL1 is located on the organic dielectric layer 81, and the organic dielectric layer 82 is covered on the re-wiring layer RL1; the re-wiring layer RL2 is located on the organic dielectric layer 82 and extends through the organic dielectric layer 82 to be electrically connected to the re-wiring layer RL1; the organic dielectric layer 83 covers the re-wiring layer RL2, and the re-wiring layer RL3 is located on the organic dielectric layer 83 and extends through the organic dielectric layer 83 to be electrically connected to the re-wiring layer RL2; the organic dielectric layer 84 overlies the re-wiring layer RL3, and the re-wiring layer RL4 is located on the organic dielectric layer 84 and extends through the organic dielectric layer 84 to be electrically connected to the re-wiring layer RL3. In some embodiments, organic dielectric layer 81 and rerouting layer RL1 closest to substrate 80 and furthest from

die

120 and 122 may be referred to as an initial organic dielectric layer and an initial rerouting layer, respectively, and organic dielectric layers 82 and 83 may be referred to as a first organic dielectric layer and a second organic dielectric layer, respectively; the rerouting layers RL2 and RL3 may be referred to as a first rerouting layer and a second rerouting layer, respectively; the organic dielectric layer 84 and the rewiring layer RL4 that are furthest from the substrate 80 and closest to the dies 120 and 122 may be referred to as the end organic dielectric layer and the conductive pads, respectively.

In some embodiments, the plurality of organic dielectric layers in the organic dielectric structure OS1 may each comprise a suitable organic dielectric material, such as a polymeric material comprising polyimide. The plurality of redistribution layers RL1-RL4 in the redistribution structure RS1 may include metallic materials such as titanium, copper, tungsten, and the like. Each redistribution layer may include a seed layer and a conductive layer. For example, as shown in the enlarged view in fig. 3K, the re-wiring layer RL2 includes a seed layer SL that is a metal seed layer, such as a copper metal layer, and may include a metal material such as titanium, copper, tungsten, and a conductive layer ML that includes a metal material such as copper.

With continued reference to fig. 2A and 3K, in some embodiments, conductive layer ML is located on a side of seed layer SL that is remote from substrate 80 and proximate to dies 120 and 122, seed layer SL and conductive layer ML overlap each other in direction D1, and the orthographic projection of seed layer SL onto the major surface of organic dielectric structure OS1 in direction D1 is located within the orthographic projection of conductive layer ML onto the major surface of organic dielectric structure OS1 in direction D1. In some embodiments, the sidewall S1 of the seed layer SL is laterally recessed in the direction D2 relative to the sidewall S2 of the conductive layer ML.

In some embodiments, one or more redistribution layers each include a via portion and a trace portion connected to each other, the via portion being embedded in a corresponding organic dielectric layer, and the trace portion extending over a major surface of the organic dielectric layer. The routing portions of the rewiring layers located in different layers are electrically connected with each other through the through hole portions. For example, the re-wiring layer RL2 includes a via portion V embedded in the organic dielectric layer 82 and a trace portion T extending on a main surface of the organic dielectric layer 82, and the organic dielectric layer 83 covers a sidewall of the trace portion T and a surface thereof on a side away from the organic dielectric layer 82. In some embodiments, the surface of the organic dielectric layer 83 on the side away from the organic dielectric layer 82 and the surface of the trace portion T of the re-wiring layer RL2 on the side away from the organic dielectric layer 82 are at different levels. For example, the surface of the organic dielectric layer 83 on the side away from the organic dielectric layer 82 is farther from the substrate 80 and closer to the dies 120 and 122 than the surface of the wiring portion T of the specific gravity wiring layer RL2 on the side away from the organic dielectric layer 82.

In some embodiments, each redistribution layer has a substantially planar major surface, although the disclosure is not so limited.

With continued reference to fig. 2A, in some embodiments, the encapsulation layer 106 is located on the sides of the bridge die BD and conductive pillars 105 in a direction parallel to the major surfaces of the dies 120 and 122 (e.g., direction D2), and laterally encapsulates the sidewalls of the bridge die BD and conductive pillars 105. For example, the encapsulation layer 106 surrounds and contacts the sidewalls of the organic dielectric structure OS1 that bridge the substrate 80 of the die BD and the interconnect structure 88. In some embodiments, encapsulation layer 106 may also extend to cover the surface of organic dielectric structure OS1 on the side near die 120 and 122 (e.g., the major surface of end organic dielectric layer 84 on the side near die 120 and 122) and around the sidewalls of the portion of redistribution layer RL4 protruding from the major surface of organic dielectric layer 84.

In some embodiments, the encapsulation layer 80 also includes an organic dielectric material, for example, the encapsulation layer 80 may include a molding compound, such as an epoxy molding compound (epoxy molding compound, EMC), but the disclosure is not limited thereto. Since the organic dielectric structure OS1 of the interconnection structure 88 of the bridge die BD is made of an organic dielectric material, the thermal expansion coefficients of the organic dielectric structure OS1 and the encapsulation layer 80 are similar, so that the problem of package warpage caused by mismatch of the thermal expansion coefficients between the dielectric structure OS1 of the bridge die and the encapsulation layer 80 can be avoided or reduced. On the other hand, in the embodiment where the substrate 80 is an insulating substrate (e.g., a glass substrate), the thermal expansion coefficient of the insulating substrate may be adjusted to be similar to that of the encapsulation layer 106 and/or the organic dielectric structure OS1, so as to avoid or reduce the warpage of the encapsulation structure caused by the mismatch of the thermal expansion coefficients between different materials.

With continued reference to fig. 2A, in some embodiments, a plurality of conductive pillars 105 are arranged around the bridge die BD in direction D2 and laterally encapsulated by the encapsulation layer 106. The interconnect structure 108 is located between the bridge die BD and the encapsulation layer 106 and the plurality of dies 120 and 122, and provides electrical connection between the plurality of dies 120 and 122 and the bridge die BD and electrical connection between the plurality of dies 120 and 122 and the conductive pillars 105.

In some embodiments, the interconnect structure 108 has a similar structure to the interconnect structure 88 in the bridge die BD, and the interconnect structure 88 and the interconnect structure 108 may be referred to as a first interconnect structure and a second interconnect structure, respectively, or vice versa. For example, the interconnect structure 108 includes an organic dielectric structure OS2 and a re-routing structure RS2. The organic dielectric structure OS2 and the re-wiring structure RS2 may include at least one organic dielectric layer and at least one re-wiring layer stacked on each other. For example, the rerouting structure RS2 includes a plurality of rerouting layers RL11, RL12, RL13, RL14 connected to each other. For brevity, the plurality of organic dielectric layers included in the organic dielectric structure OS2 are not specifically shown in fig. 2A. It should be understood that the number of layers of organic dielectric layers and/or redistribution layers in the

interconnect structures

88 and 108 shown in the figures are illustrative and not limiting.

In some embodiments, the plurality of dies 120 and 122 are electrically connected to the rewiring structure RS2 of the interconnect structure 108 through a plurality of conductive connections 123. In some embodiments, interconnect structure 108 provides electrical connection between die 120 and die 122, and electrical connection between dies 120 and 122 and conductive pillars 105; for example, in interconnect structure 108, re-routing structure RS2 includes a first portion P1 electrically connecting

dice

120 and 122 to bridge die BD and a second portion P2 electrically connecting

dice

120 and 122 to plurality of conductive pillars 105. That is, die 120 and die 122 are electrically connected to each other through a first portion of re-routing structure RS2 in interconnect structure 108 and bridging re-routing structure RS1 in die BD, and die 120 and die 122 are connected to conductive connection 130 through a second portion of re-routing structure RS2 in interconnect structure 108 and plurality of conductive pillars 105.

In some embodiments, interconnect structure 88 and interconnect structure 108 have different dimensions, e.g., in direction D1, the dimension (e.g., width, area, etc.) of interconnect structure 88 is smaller than the dimension (e.g., width, area, etc.) of interconnect structure 108, and the orthographic projection of interconnect structure 88 on the major surface of package connection member 110 in direction D1 is within the orthographic projection of interconnect structure 108 on the major surface of package connection member 110 in direction D1. Interconnect structure 108 extends laterally beyond the sidewalls of interconnect structure 88 in direction D2, and the sidewalls of interconnect structure 108 may be substantially aligned with the sidewalls of encapsulation layer 106 in direction D1. In some embodiments, the linewidth of the re-wiring layer of re-wiring structure RS1 in interconnect structure 88 may be different than the linewidth of the re-wiring layer of re-wiring structure RS2 in interconnect structure 108. For example, the line width of the re-wiring layer of the re-wiring structure RS1 may be smaller than the line width of the re-wiring layer of the re-wiring structure RS2. In some embodiments, the thickness of the rewiring layer of the rewiring structure RS1 in the direction D1 is less than or equal to the thickness of the rewiring layer of the rewiring structure RS2 in the direction D1. In some embodiments, the rerouting structures bridging the die BD and the interconnect structure 108 employ different linewidths/pitches/thicknesses. On the other hand, the line width/pitch/thickness of the re-wiring structure of the bridge die BD is larger than the line width/pitch/thickness of the conductive trace 8B of the bridge die B (formed in the inorganic dielectric structure 8a using the damascene process) shown in fig. 1B, so that the signal loss can be reduced.

With continued reference to fig. 2A and 2C, in some embodiments, the package structure 200 further includes a passive device die PD that may be embedded in the package connection member 110 and connected to at least one of the plurality of dies 120 and 122. The passive device die PD may include passive devices such as capacitors (e.g., deep trench capacitors).

For example, the passive device die PD is disposed side-by-side with the bridge die BD and the conductive pillars 105 in the direction D2 and spaced apart from the bridge die BD. The encapsulation layer 106 encapsulates the sidewalls of the passive device die PD at least in direction D2. The passive device die PD has conductive terminals CT that are electrically connected to the rewiring structure RS2 of the interconnect structure 108. At least one of the plurality of dies 120 and 122 (e.g., die 120) is electrically connected to the conductive terminal CT of the passive device die PD through the conductive connection 123 and the interconnect structure 108 (e.g., the third portion P3 of the re-routing structure RS 2). By providing a passive device die including, for example, a capacitor, the power integrity of the package structure 200 may be improved. On the other hand, since the passive device die PD is embedded in the package connection member 110 and is a structure separately (discrete) from the bridge die BD and spaced apart from each other, the yield can be better controlled, for example, when a good passive device die is selected for packaging during the packaging process, the situation that the whole package connection member fails due to leakage current generated by the passive device itself such as a capacitor, which may occur in the embodiment shown in fig. 1A, can be avoided, and thus the product yield can be improved.

In some embodiments, the surfaces of the substrate 80, the passive device die PD, the plurality of conductive pillars 105, and the encapsulation layer 106 on the side away from the interconnect structure 108 and the plurality of dies 120 and 122 of the bridge die BD are substantially flush with each other in a direction parallel to the major surfaces of the plurality of dies 120 and 122 (e.g., direction D2). However, the disclosure is not limited thereto.

Fig. 2B shows a schematic cross-sectional view of a package structure 200' according to an alternative embodiment of the present disclosure. Package structure 200 'is similar to package structure 200 except that in package structure 200', bridge die BD includes interconnect structure 88, but does not include a substrate.

Referring to fig. 2B, the interconnect structure 88 of the bridge die BD includes an organic dielectric structure OS1 and a re-routing structure RS1 embedded in the organic dielectric structure OS 1. In some embodiments, the bridge die BD has no substrate on the side of the interconnect structure 88 away from the interconnect structure 108 and the plurality of dies 120 and 122, and the surface of the organic dielectric structure OS1 on the side away from the interconnect structure 108 and the plurality of dies 120 and 122 is substantially flush with the surface of the passive device die PD, the plurality of conductive pillars 105, and the encapsulation layer 106 on the side away from the interconnect structure 108 and the plurality of dies 120 and 122 in the direction D2. In this embodiment, the bridge die BD does not include a substrate, so that the problem of package warpage due to thermal expansion coefficient mismatch caused by too large a difference in thermal expansion coefficients of the substrate material and the organic dielectric structure OS1 and the encapsulation layer 106 can be avoided. In this way, the substrate material of the bridge die BD may be selected more freely during the manufacturing process of the package structure.

In some embodiments, the package structures 200 and 200' may be further connected to other package components, such as the package substrate 220 (fig. 4G and 5B), through the conductive connection 130.

Fig. 3A-3K illustrate schematic cross-sectional views of various process steps in a method of forming a bridge die BD according to some embodiments of the present disclosure.

Referring to fig. 3A, a substrate 80 is provided, and the substrate 80 may include a semiconductor material, an insulating material, or a combination thereof. For example, the substrate 80 may be a semiconductor substrate (e.g., a silicon substrate), a glass substrate (e.g., comprising silicon oxide), but may alternatively or additionally comprise other suitable semiconductor materials and/or insulating materials (e.g., organic insulating materials). In some embodiments, the coefficient of thermal expansion of the substrate 80 may be adjusted according to product requirements, for example, when a glass substrate (or referred to as a silicon oxide substrate) is used, the coefficient of thermal expansion of the substrate may be adjusted by doping the silicon oxide glass and/or adjusting the type and amount of doping substances so that the coefficient of thermal expansion of the substrate 80 may be within a suitable range to be similar to the coefficient of thermal expansion of the subsequently formed encapsulation layer. In some embodiments, the substrate 80 is a wafer (wafer) that includes a plurality of die regions and dicing regions (not shown), the dicing regions being located between the plurality of die regions, and fig. 3A-3K illustrate a fabrication process in one of the die regions of the wafer. It should be appreciated that the structure and fabrication process of the multiple die regions are substantially identical prior to the dicing process.

In some embodiments, the organic dielectric layer 81 is formed on the substrate 80, and a material of the organic dielectric layer 81 may include, for example, a polymer material such as Polyimide (PI), and may be formed on the substrate 80 through a deposition process such as chemical vapor deposition (cvd) or a spin coating (spin coating) process.

Referring to fig. 3B to 3F, a re-wiring layer (redistribution layer) RL1 is formed on the organic dielectric layer 81, and the re-wiring layer RL1 includes a conductive material, for example, a metal material that may include titanium, copper, tungsten, or the like. In some embodiments, forming the re-wiring layer RL1 includes the following processes.

Referring to fig. 3B, a seed layer SL0 'is formed on the organic dielectric layer 81, and the seed layer SL0' may be a metal seed layer, for example, a seed layer for copper plating. For example, the seed layer SL0' may comprise a metallic material such as titanium, tungsten, copper, etc., including, for example, tiCu, tiWCu, etc., metallic alloys. In some embodiments, the seed layer SL0' may be formed by a sputtering (sputtering) process.

Referring to fig. 3C, in some embodiments, a patterned masking layer 79 is formed on the seed layer SL0 'to cover a portion of the surface of the seed layer SL0' remote from the organic dielectric layer 81. Patterned masking layer 79 may comprise a patterned photoresist layer and may be formed by: a photoresist layer is formed on the seed layer SL0', and then a photolithography process including exposure and development is performed on the photoresist layer to remove a portion of the photoresist layer and form a mask opening 79a to expose a portion of the surface of the seed layer SL0'.

Referring to fig. 3D, a conductive layer ML0 is formed in the mask opening 79a of the patterned mask layer 79 on a portion of the seed layer SL0' exposed by the mask opening 79 a. The conductive layer ML0 may include a metal material such as copper, and may be formed through a plating (e.g., electroplating) process.

Referring to fig. 3D to 3F, the patterned mask layer 79 is removed to expose the seed layer SL0', and then a portion of the seed layer SL0' not covered by the conductive layer ML0 (i.e., a portion previously covered by the patterned mask layer 79) is removed to form the seed layer SL0. For example, after removing the patterned mask layer 79, an etching process is performed on the seed layer SL0 'with the conductive layer ML0 as an etching mask to remove a portion of the seed layer SL0' not covered by the conductive layer ML0, the remaining seed layer SL0 is located under the conductive layer ML0 (e.g., directly under in the drawing), and a surface of the seed layer SL0 on a side remote from the organic dielectric layer 81 is covered (e.g., entirely covered) by the conductive layer ML 0. The seed layer SL0 and the conductive layer ML0 together constitute the rewiring layer RL1. In some embodiments, the orthographic projection of seed layer SL0 onto the major surface of substrate 80 in a direction perpendicular to the major surface of substrate 80 is within the orthographic projection of conductive layer ML0 onto the major surface of substrate 80 in a direction perpendicular to the major surface of substrate 80.

Referring to fig. 3F, in some embodiments, the above-described etching process includes a wet etching process, and is isotropic, for example, and thus, the sidewalls of the formed seed layer SL0 may be laterally recessed with respect to the sidewalls of the conductive layer ML0, i.e., lateral grooves (lateral grooves) RC are formed at sides of the seed layer SL0 in a direction parallel to the main surface of the substrate 80, and the lateral grooves RC are located between the conductive layer ML0 and the organic dielectric layer 81 in a direction perpendicular to the main surface of the substrate 80. However, the embodiments of the disclosure are not limited thereto.

Referring to fig. 3G, an organic dielectric layer 82 is formed on the re-wiring layer RL1 to cover the sidewall of the re-wiring layer RL1 and the surface thereof on the side remote from the organic dielectric layer 81. The material and forming method of the organic dielectric layer 82 are similar to those of the organic dielectric layer 81, and will not be described here. It should be appreciated that the seed layer and conductive layer of the re-wiring layer RL1 are not specifically shown in fig. 3G and subsequent figures for simplicity and clarity of the drawing.

Referring to fig. 3H, a patterning process is performed on the organic dielectric layer 82 to remove portions of the organic dielectric layer 82 that cover the re-wiring layer RL1 and form one or more openings OP1 in the organic dielectric layer 82. The opening exposes a portion of the surface of the redistribution layer RL1 remote from the substrate 80. In some embodiments, the patterning process may include a photolithography process (including exposure and development), a laser drilling (laser drilling) process, the like, or a combination thereof.

Referring to fig. 3I, a seed layer SL 'is formed on the organic dielectric layer 82, and the seed layer SL' may be a metal seed layer, for example, a seed layer for copper plating. The seed layer SL' covers a surface of the side of the organic dielectric layer 82 remote from the substrate 80 and the organic dielectric layer 81, and fills the opening OP1 to line the surface of the opening OP1 and contact a portion of the surface of the re-wiring layer RL1 previously exposed by the opening OP 1. In some embodiments, the seed layer SL' may be a conformal layer, but the disclosure is not limited thereto. The seed layer SL' may comprise a metallic material such as titanium, tungsten, copper, etc., including, for example, metal alloys such as TiCu, tiWCu, etc. In some embodiments, the seed layer SL' may be formed by a sputtering (sputtering) process.

Referring to fig. 3J, in some embodiments, a patterned masking layer 89 is formed over the seed layer SL 'to cover a portion of the surface of the seed layer SL' remote from the organic dielectric layer 82. Patterned masking layer 89 may comprise a patterned photoresist layer and may be formed by: a photoresist layer is formed on the seed layer SL', and then a photolithography process including exposure and development is performed on the photoresist layer to remove a portion of the photoresist layer and form a mask opening MOP. In some embodiments, the mask opening MOP exposes portions of the seed layer SL' located in the opening OP1 and portions located on the major surface of the organic dielectric layer 82.

Referring to fig. 3K, a conductive layer ML is formed on a portion of the seed layer SL' exposed by the mask opening MOP in the mask opening MOP of the patterned mask layer 89. The conductive layer ML may include a metal material such as copper, and may be formed through a plating (e.g., electroplating) process.

Referring to fig. 3L to 3M, the patterned mask layer 89 is removed, and then a portion of the seed layer SL' not covered by the conductive layer ML (i.e., a portion previously covered by the patterned mask layer 89) is removed to form the seed layer SL. For example, after removing the patterned mask layer 89, the seed layer SL 'is subjected to an etching process with the conductive layer ML as an etching mask to remove a portion of the seed layer SL' not covered by the conductive layer ML, the remaining seed layer SL is located under the conductive layer ML (e.g., directly under in the drawing), and a surface of the seed layer SL on a side remote from the re-wiring layer RL1 is covered (e.g., entirely covered) by the conductive layer ML. The seed layer SL and the conductive layer ML together constitute the rewiring layer RL2.

Referring to fig. 3M, an enlarged schematic view of a portion of the rewiring layer RL2 is shown. The seed layer SL is located between the conductive layer ML and the organic dielectric layer 82 and between the conductive layer ML and the rewiring layer RL 1. The seed layer SL and the conductive layer ML overlap each other (e.g., completely overlap) in a direction perpendicular to the main surface of the substrate 80. In other words, the orthographic projections of the seed layer SL and the conductive layer ML on the main surface of the substrate 80 in the direction perpendicular to the main surface of the substrate 80 coincide with each other (e.g., completely coincide). In some embodiments, the orthographic projection of seed layer SL on the major surface of substrate 80 is within the orthographic projection of conductive layer ML on the major surface of substrate 80.

In some embodiments, the re-wiring layer RL2 includes a via (via) portion V located in the opening OP1 of the organic dielectric layer 82 and a trace portion T extending on a major surface (e.g., a top surface as shown in the figures) of the organic dielectric layer 82 remote from the organic dielectric layer 81. The via portion V of the re-wiring layer RL2, in which the seed layer SL surrounds the sidewall of the conductive layer ML and its surface on the side close to the re-wiring layer RL, includes the portion of the seed layer SL and the conductive layer ML in the opening OP1 of the organic dielectric layer 82; the trace portion T of the rewiring layer RL2 includes portions of the seed layer SL and the conductive layer ML that are located on the main surface of the organic dielectric layer 82. In some embodiments, similar to the re-wiring layer RL1, the seed layer of re-wiring layer RL2 also has a lateral recess RC similar to that shown in fig. 3E; for example, in the trace portion T, the sidewall S1 of the seed layer SL is laterally recessed with respect to the sidewall S2 of the conductive layer ML in a direction parallel to the main surface of the substrate 80, i.e., has lateral grooves on the sides of the seed layer SL, which are located between the conductive layer ML and the organic dielectric layer 82 in a direction perpendicular to the main surface of the substrate 80. The sidewall S2 of the conductive layer ML in the trace portion T is not covered by the seed layer SL.

As shown in the enlarged view of the re-wiring layer RL2, in some embodiments, the major surface of the re-wiring layer RL2 remote from the re-wiring layer RL1 is substantially planar, but the disclosure is not so limited.

In some embodiments, the redistribution layer formed by the process may have a larger line width/line spacing and/or thickness than the conductive trace formed by the damascene process, thereby reducing signal loss and improving device performance. For example, the thickness T1 of the trace portion of the re-wiring layer RL2 may be greater than 2 microns, such as in the range of 2 microns to 5 microns.

Referring to fig. 3N to 3P, a similar process to that of fig. 3G to 3M is then performed to form further organic dielectric layers and re-wiring layers on the organic dielectric layer 82 and re-wiring layer RL 2. For example, an organic dielectric layer 83 is formed on the side of the organic dielectric layer 82 and the re-wiring layer RL2 remote from the organic dielectric layer 81, the organic dielectric layer 83 covering the sidewall of the re-wiring layer RL2 and its surface on the side remote from the re-wiring layer RL1, in this embodiment the organic dielectric layer 83 covering and directly contacting the sidewall S1 of the seed layer SL of the re-wiring layer RL2 and the sidewall S2 of the conductive layer ML; then, portions of the organic dielectric layer 83 are removed, to expose a portion of the surface of the re-wiring layer RL2 remote from the re-wiring layer RL 1; forming a re-wiring layer RL3 on the organic dielectric layer 83, the re-wiring layer 83 extending on a main surface of the organic dielectric layer 83 remote from the organic dielectric layer 82 and filling into the opening of the organic dielectric layer 83 to be electrically connected with the re-wiring layer RL 2; next, an organic dielectric layer 84 and a re-wiring layer RL4 are formed on the organic dielectric layer 83 and the re-wiring layer RL3, and the re-wiring layer RL4 extends through the organic dielectric layer 84 to be electrically connected with the re-wiring layer RL 3. It should be noted that the formation process of each of the re-wiring layers RL1-RL4 is similar to that of the re-wiring layer RL2 and each includes a seed layer and a conductive layer, but the seed layer and the conductive layer of each re-wiring layer are not specifically shown in FIGS. 3J-3K for simplicity of the drawing. It should be understood that the number of layers of the organic dielectric layer and the redistribution layer shown in the drawings is merely illustrative, and the present disclosure is not limited thereto, and the number of layers of the organic dielectric layer and the redistribution layer may be adjusted based on product needs.

In some embodiments, the re-wiring layer RL3 also includes a via portion embedded in the organic dielectric layer 83 and a trace portion extending over a major surface of the organic dielectric layer 83; the rewiring layer farthest from the substrate 80 (e.g., the uppermost rewiring layer RL4 in the drawing) includes a via portion in the organic dielectric layer 84 and a pad portion protruding from the main surface of the organic dielectric layer 84 for electrical connection with an external member. In some embodiments, the rewiring layer RL4 may also be referred to as a conductive pad (conductive pad) of the bridge die BD.

Referring to FIG. 3P, organic dielectric layers 81-84 constitute organic dielectric structure OS1, re-wiring layers RL1-RL4 constitute re-wiring structure RS1, and organic dielectric structure OS1 and re-wiring structure RS1 constitute interconnect structure 88. In some embodiments, the substrate 80 is a wafer and the interconnect structure 88 is formed in each die region of the wafer, and after forming the interconnect structure 88, a dicing process (e.g., a laser dicing (laser dicing), a mechanical saw (mechanical saw) process, or a combination thereof, etc.) is performed along the dicing region of the wafer to dice the die regions of the wafer apart from one another and form a plurality of Bridge Dies (BD) independent of one another.

The bridge die BD includes a substrate 80 and an interconnect structure 88 located on one side of the substrate 80. In some embodiments, the bridge die BD does not include active devices (active devices) such as transistors or passive devices such as capacitors. The bridge die BD may further be used in a packaging process to provide electrical connections between different dies (e.g., between a system chip and a memory chip).

Fig. 4A-4G illustrate schematic cross-sectional views of various steps in a method of forming a package structure using a bridge die BD formed by the process of fig. 3A-3K as part of a package connection member, according to some embodiments of the present disclosure.

Referring to fig. 4A, a carrier substrate 100 is provided, and the carrier substrate 100 is, for example, a temporary carrier plate (temporary carrier) to be removed in a subsequent process step, and may be a glass carrier plate, a ceramic carrier plate or the like, but the disclosure is not limited thereto. The carrier substrate 100 may use any material that provides structural support for the overlying structure in subsequent processes. In some embodiments, the carrier substrate 100 has a release layer (101) formed thereon, and the release layer 101 may be formed of an adhesive such as ultraviolet-Violet (UV) adhesive, light-to-Heat Conversion (LTHC) adhesive, or other types of adhesives. In a subsequent process, the release layer 101 may decompose under the influence of light and lose or reduce the viscosity, thereby detaching the carrier substrate 100 from the overlying structure to be formed in a subsequent step.

In some embodiments, a dielectric layer PL is formed over the carrier substrate 100, which may comprise a polymeric material such as polyimide, for example. A seed layer 102 is formed over dielectric layer PL, and seed layer 102 may be a metal seed layer, such as a seed layer for copper plating. The seed layer 102 comprises, for example, a metallic material such as titanium, tungsten, copper, etc., and may be formed by a sputtering process. In some embodiments, the seed layer 102 may include TiCu, tiWCu, or the like. However, the disclosure is not limited thereto.

Referring to fig. 4B, a plurality of conductive pillars 105 are formed on a side of the seed layer 102 remote from the carrier substrate 100, the conductive pillars 105 may comprise a metallic material such as copper, and may be formed by: first, a patterned mask layer (e.g., a patterned photoresist layer) is formed on a side of the seed layer 102 remote from the carrier substrate 100, the patterned mask layer having a plurality of mask openings to expose a portion of a surface of the seed layer 120 on the side remote from the carrier substrate 100, the plurality of mask openings being located corresponding to locations where the conductive pillars 105 are expected to be formed; next, a plurality of conductive pillars 105 are formed on the seed layer 102 in the openings of the patterned mask layer by a plating (e.g., electroplating) process; thereafter, the patterned mask layer is removed.

With continued reference to fig. 4B, in some embodiments, the bridge die BD formed from the fabrication process shown in fig. 3A-3K is mounted (mount) onto a carrier substrate 100, e.g., the bridge die BD may be attached to a seed layer 102 on the carrier substrate 100 by a Die Attach Film (DAF). In some embodiments, the substrate 80 of the bridge die BD faces the carrier substrate 100 and its re-routing structure RS1 is located on a side of the substrate 80 away from the carrier substrate 100, i.e., the conductive pads RL4 of the re-routing structure RS1 face upward for electrical connection in a subsequent process.

In some embodiments, the passive device die PD is also mounted over the carrier substrate 100, and may be mounted in a manner similar to that described above for the bridge die BD. The bridge die BD, passive device die PD, and conductive pillars 105 are disposed side-by-side and spaced apart from one another on the carrier substrate 100. For example, the conductive pillars 105 are disposed around the bridge die BD and the passive device die PD. It should be appreciated that the die attach film used to attach the bridge die BD and the passive device die PD is not shown in the figures for simplicity of the drawing. In addition, prior to mounting the bridge die BD and the passive device die PD onto the carrier substrate 100, the bridge die BD and the passive device die PD are each tested and a known good die (known good die) is selected for mounting onto the carrier substrate 100 to control and improve product yield.

The passive device die PD may include passive devices such as capacitors, resistors, etc., and the present disclosure is not limited to the type of passive devices, and suitable types of passive device die may be selected based on product requirements. On the other hand, the number of bridge die BD and passive device die PD shown in the figures is merely illustrative, and the present disclosure is not limited thereto, and an appropriate number of bridge die and passive device die PD may be selected based on product requirements.

As shown in the enlarged view of passive device die PD in fig. 4B, in some embodiments passive device die PD may be or include deep trench capacitors (deep trench capacitor, DTCs) and may include substrate 90, electrodes E1 and E2, dielectric material layer 91, conductive terminals (conductive terminal) CT1 and CT2, and dielectric layer 92. The material of substrate 90 may be selected from the same candidate materials as substrate 80 of bridge die BD, and may be similar, the same, or different from the material of substrate 80. For example, the substrate 90 may be a semiconductor substrate, such as a silicon substrate, but the disclosure is not limited thereto, and the substrate 90 may also be an insulating substrate, such as a glass substrate, and may include an insulating material such as silicon oxide.

The deep trench capacitor includes electrodes E1 and E2 opposing each other and a portion of a dielectric material layer 91 (or referred to as an inter-electrode dielectric layer) interposed between the electrodes E1 and E2. In some embodiments, the substrate 90 has deep trenches, and the electrodes E1 and E2 of the capacitor and portions of the inter-electrode dielectric layer extend into the deep trenches of the substrate 90. In some embodiments in which the substrate 90 is a semiconductor substrate, an insulating liner (insulator) is also provided between the substrate 90 and the electrode E1 to electrically isolate the substrate 90 from the electrode E1.

In some embodiments, a layer of dielectric material 91 covers the surfaces of electrodes E1 and E2 remote from substrate 90 and is located between electrodes E1 and E2 to isolate electrodes E1 and E2 from each other. The dielectric material layer 91 may comprise a plurality of layers of dielectric material, and may include, for example, a first dielectric layer on a major surface of the substrate 90 and on a side of the electrode E1, a second dielectric layer (at least a portion of the second dielectric layer being an inter-electrode dielectric layer) on a side of the first dielectric layer away from the substrate and between the electrode E1 and the electrode E2, and a third dielectric layer on a side of the second dielectric layer and the electrode E2 away from the substrate. In some embodiments, the materials of the first dielectric layer to the third dielectric layer may be the same or different, and may be selected from inorganic dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, organic dielectric materials such as polypropylene, polystyrene, polyethylene terephthalate, the like, or a combination thereof. In some embodiments, the second dielectric layer comprising the inter-electrode dielectric layer may be or comprise a high-k dielectric material, for example comprising silicon nitride.

The dielectric layer 92 is disposed on a side of the dielectric material layer 91 remote from the substrate 90 and may also be referred to as a passivation layer. In some embodiments, the dielectric layer 92 may be selected from inorganic dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, organic dielectric materials including polymeric materials such as polyimide, the like, or combinations thereof.

The deep trench capacitor includes a plurality of conductive terminals CT including conductive terminals CT1 and CT2 connected to electrodes E1 and E2, respectively. For example, the conductive terminal CT1 extends through the dielectric layer 92 and the dielectric material layer 91 to be electrically connected with the electrode E1, and the conductive terminal CT2 extends through the dielectric layer 92 and the dielectric material layer 91 to be electrically connected with the electrode E2. It should be understood that the number of conductive terminals CT shown in the figures is merely illustrative, and the disclosure is not so limited, and that in fig. 4B and subsequent figures, the specific structure of the passive device die PD is not specifically shown, and that two conductive terminals CT represent more conductive terminals that it may include, for the sake of brevity.

In some embodiments, the materials of the electrodes E1, E2 and the conductive terminals CT may each be selected from suitable conductive materials, for example, may include a metal material such as copper, and the materials of the electrodes E1, E2 and the conductive terminals CT may be the same or different from each other.

With continued reference to fig. 4B, in some embodiments, the bridge die BD and the passive device die PD may have substantially the same height, e.g., the surface of the rewiring layer RL4 of the bridge die BD on the side away from the carrier substrate 100 and the surface of the conductive terminals CT of the passive device die PD on the side away from the carrier substrate 100 may be at substantially the same level with respect to the major surface of the carrier substrate 100. However, the disclosure is not limited thereto.

Referring to fig. 4C, in some embodiments, an encapsulation layer (encapsulation layer) 106 is formed on the carrier substrate 100, the encapsulation layer 106 being formed on the sides of the bridge die BD, passive device die PD, and conductive pillars 105, surrounding the sidewalls of the bridge die BD, passive device die PD, and conductive pillars 105, and may also cover portions of the surfaces of the bridge die BD and passive device die PD on the side away from the carrier substrate 100 in some embodiments. In some embodiments, the encapsulation layer 80 comprises an organic dielectric material. For example, the encapsulation layer 80 may include a molding compound, such as an epoxy molding compound (epoxy molding compound, EMC), but the disclosure is not limited thereto. The encapsulation layer 80 may be formed, for example, by the following method: forming an encapsulation material layer over the carrier substrate 100 to encapsulate the bridge die BD, the passive device die PD, and the sidewalls of the conductive pillars 105 and surfaces thereof on a side away from the carrier substrate 100; next, a planarization process (e.g., a grinding process, a chemical mechanical polishing (chemical mechanical polishing)) is performed on the encapsulation material layer to remove a portion of the encapsulation material layer and expose the re-wiring layer RL4 of the bridge die BD, the conductive terminals CT of the passive device die PD, and the surface of the conductive pillars 105 remote from the carrier substrate 100. In some embodiments, after the planarization process, the encapsulation layer 106, the re-routing layer RL4 of the bridge die BD, the conductive terminals CT of the passive device die PD, and the surfaces of the conductive pillars 105 (e.g., the top surfaces shown in the figures) that are remote from the carrier substrate 100 are substantially flush with each other in a direction (e.g., direction D2) parallel to the major surface of the carrier substrate 100, i.e., at substantially the same level with respect to the major surface of the carrier substrate 100.

In some embodiments, the encapsulation layer 106 surrounds the encapsulation bridge die BD and is in contact with the organic dielectric structure OS1 of the rerouting structure RS1 of the bridge die BD. For example, the encapsulation layer 106 covers the sidewalls of the organic dielectric structure OS1, and may also cover a major surface of the organic dielectric structure OS1 remote from the substrate 80 in some embodiments. In this embodiment, the encapsulating layer 106 and the organic dielectric structure OS1 both comprise organic dielectric materials, and the thermal expansion coefficients of the two materials are similar, so that the problem of warpage of the encapsulating structure caused by mismatch of the thermal expansion coefficients can be avoided. In some embodiments, the substrate 90 (fig. 4B) of the passive device die PD is a glass substrate, and the coefficient of thermal expansion of the glass substrate may be tuned to be similar to that of the encapsulation layer 106, and one or more of the dielectric material layers 91 and 92 may be organic material layers, such that the coefficient of thermal expansion of the relevant materials of the passive device die PD and the encapsulation layer 106 are similar, thereby avoiding or reducing package warpage issues caused by mismatch of the coefficients of thermal expansion of the respective material layers of the passive device die PD and the encapsulation layer.

Referring to fig. 4D, an interconnect structure 108 is formed on a side of the encapsulation layer 106 remote from the carrier substrate 100. Similar to interconnect structure 88, interconnect structure 108 includes an organic dielectric structure OS2 and a re-routing structure RS2 embedded in organic dielectric structure OS 2. In some embodiments, the interconnect structure 108 includes a plurality of organic

dielectric layers

111, 112, 113 and a plurality of redistribution layers RL11, RL12, RL13 stacked alternately with each other; the re-wiring layer RL11 extends through the organic dielectric layer 111 to electrically connect with the re-wiring layer RL4 of the bridge die BD, the conductive terminals CT of the passive device die PD, and the conductive pillars 105; the re-wiring layer RL12 extends through the organic dielectric layer 112 to be electrically connected with the re-wiring layer RL 11; the re-wiring layer RL13 extends through the organic dielectric layer 113 to be electrically connected with the re-wiring layer 112.

The material and method of forming the interconnect structure 108 is similar to the material and method of forming the interconnect structure 88, for example, the organic dielectric structure 108 comprises an organic dielectric material such as a polymer (e.g., polyimide), and the re-wiring structure RS2 comprises a metallic material such as titanium, copper, tungsten, etc.; the method for forming the interconnection structure 108 includes, for example: forming an organic dielectric layer 111 on a side of the encapsulation layer 106 away from the carrier substrate 100, and forming an opening in the organic dielectric layer 111 by a laser drilling process, an exposure and development process or the like to expose a portion of the surfaces of the conductive pillars 105, the conductive terminals CT and the conductive pads RL 4; forming a seed layer on a side of the organic dielectric layer 111 remote from the encapsulation layer 106 and in an opening thereof; forming a patterned mask layer on the seed layer, the patterned mask layer having mask openings corresponding to locations where the re-wiring layer is to be formed; forming a conductive layer on the seed layer exposed by the mask opening; removing the patterned mask layer, and performing an etching process on the seed crystal layer by using the conductive layer as an etching mask to remove a part of the seed crystal layer which is not covered by the conductive layer, wherein the remaining seed crystal layer and the conductive layer together form a rewiring layer RL11; the similar process described above is then repeated to form the organic dielectric layer 112, the re-wiring layer RL12, the organic dielectric layer 113 and the re-wiring layer RL13.

In some embodiments, the re-wiring layer RL11 and the re-wiring layer RL12 have via portions V11 and V12 embedded in the organic

dielectric layers

111 and 112, respectively, and trace portions T11 and T12 extending on the main surfaces of the organic

dielectric layers

111 and 112 on the side away from the encapsulation layer. The trace portion T11 is connected to the conductive member below the conductive post 105, the conductive terminal CT, the conductive pad RL4, and the like through the via portion V11; the trace portion T12 is connected to the trace portion T11 of the rewiring layer R11 through the via portion V12. In some embodiments, the rewiring layer of the rewiring structure RS2 that is furthest from the encapsulation layer 106, for example, the topmost rewiring layer RL13 shown in the figures, may also be referred to as a conductive pad for electrical connection with a subsequently disposed component. The re-wiring layer RL13 may include via portions located in the organic dielectric layer 113, and in some embodiments may also include pad portions (not shown) located on a surface of the organic dielectric layer 113 remote from the organic dielectric layer 112.

In some embodiments, each of the redistribution layers in the redistribution structure RS1 may have substantially the same line width/thickness, and each of the redistribution layers in the redistribution structure RS2 may have substantially the same line width/thickness; multiple redistribution layers of the same redistribution structure may have different linewidths/thicknesses. Moreover, the linewidth/thickness of each of the redistribution layers RL1-RL3 in the redistribution structure RS1 of the bridge die BD is different from the linewidth/thickness of each of the redistribution layers RL11-RL13 in the interconnect structure 108, e.g., the linewidth/pitch (i.e., the linewidth/pitch of the trace portion) and/or the thickness of each of the redistribution layers RL1-RL3 in the redistribution structure RS1 is less than or equal to the linewidth (i.e., the linewidth/pitch of the trace portion) and/or the thickness of each of the redistribution layers RL11-RL13 in the redistribution structure RS 2. For example, as shown in the enlarged view of fig. 4D, the line width and thickness T1 of the routing portion of the re-routing layer in the interconnect structure 88 are smaller than the line width and thickness T2 of the routing portion T11 of the re-routing layer in the interconnect structure 108, respectively. In some embodiments, the thickness of the via portion of the re-wiring layer and the thickness of the organic dielectric layer in interconnect structure 88 are also less than the thickness of the via portion of the re-wiring layer and the thickness of the organic dielectric layer in interconnect structure 108, respectively.

In this way, the package connection member 110 including the bridge die BD, the plurality of conductive pillars 105, the encapsulation layer 106, and the interconnection structure 108 is formed, and the passive device die PD is embedded in the package connection member 110.

Referring to fig. 4E, a plurality of dies (e.g., dies 120 and 122) are provided and electrically connected to package connection member 110 by conductive connection 123. In some embodiments, conductive connections 123 are disposed between the plurality of dies 120 and 122 and the rewiring layer RL13 of the interconnect structure 108 to provide electrical connection between the plurality of dies 120 and 122 and the interconnect structure 108. The conductive connection 123 may include a plurality of conductive bumps, for example, may be or include a plurality of micro-bumps (micro-bumps).

With continued reference to fig. 4E, in some embodiments, an encapsulation layer 126 is formed on a side of the interconnect structure 108 remote from the bridge die BD and the encapsulation layer 106 to surround and encapsulate the plurality of dies 120 and 122. The method of forming the encapsulation layer 126 may include forming an encapsulation material layer over the interconnect structure 108, the encapsulation material layer encapsulating sidewalls of the plurality of dies and surfaces thereof on a side away from the interconnect structure 108, and in some embodiments, optionally further performing a planarization process (e.g., a grinding process or a CMP process) on the encapsulation material layer to remove a portion of the encapsulation material layer and expose surfaces (not shown) of the plurality of dies on a side away from the interconnect structure 108.

In some embodiments, an encapsulation layer 126 is also formed between the plurality of dies 120 and 122 and the interconnect structure 108 to circumferentially encapsulate the plurality of conductive connections 123, but the disclosure is not limited thereto. In other embodiments, an underfill layer (un-rf il layer) is formed between the plurality of dies 120 and 122 and the interconnect structure 108 to surround the plurality of conductive connectors 123 prior to forming the encapsulation layer 126; thereafter, an encapsulation layer 126 is formed to encapsulate the plurality of dies 120 and 122 and the underfill layer.

Referring to fig. 4E and 4F, the carrier substrate 100, the dielectric layer PI, and the seed layer 102 are removed. To expose a surface of the conductive pillars 105 on a side away from the interconnect structures 108. For example, exposure of release layer 101 to light (e.g., with UV light or laser light) causes release layer 101 to decompose and lose its tackiness under the influence of light and heat, thereby freeing carrier substrate 100 from its overlying structure, after which dielectric layer PI and seed layer 102 may be removed by a grinding process and/or an etching process. In this embodiment, the conductive pillars 105 may be substantially free of seed layer as the seed layer 102 is removed. However, the disclosure is not limited thereto.

In some embodiments, a plurality of conductive connectors 130 are formed on a side of the package connection member 110 remote from the interconnect structure 108. Conductive connection 130 is connected to the re-routing structures in interconnect structure 108 through conductive posts 105 and is further electrically connected to the plurality of dies 120 and 122 through interconnect structure 108. The conductive connection 130 may include conductive bumps, such as controlled collapse chip connection (Controlled collapsed chip connection, C4) bumps, but the disclosure is not limited thereto. In some embodiments, additional interconnect structures including organic dielectric structures and additional re-routing structures may also be formed on the side of encapsulation layer 106 remote from interconnect structures 108 prior to forming conductive connections 130; thereafter, a plurality of conductive connection pieces 130 are formed on a side of the additional interconnection structure remote from the encapsulation layer 106, and the plurality of conductive connection pieces 130 are connected to the conductive pillars 105 through the additional heavy wiring structure.

Referring to fig. 4F, the package structure 200 is formed. In some embodiments, the package structure 200 may be connected to other package members by conductive connections 130. For example, referring to fig. 4F-4G, in some embodiments, the package structure 200 may be further connected to the package substrate 220 by the conductive connection 130, and the package structure 500 is formed. The package substrate 220 is disposed on a side of the package connection member 110 away from the dies 120 and 122, and the plurality of dies 120 and 122 are electrically connected to the package substrate 220 through the conductive connection 123, the interconnect structures 108 and the conductive pillars 105 in the package connection member 110, and the conductive connection 130.

In some embodiments, the package structure 500 further includes conductive connections 230 formed on a side of the package substrate 220 remote from the package connection members 110. The conductive connector 230 may be or include a solder Ball (BGA), such as a ball grid array (ball grid array), but the disclosure is not limited thereto. In some embodiments, the package structure 500 may be further connected to other external components, such as a printed circuit board, through the conductive connection 230. For example, the package structure 500 may be mounted on a printed circuit board, which may be disposed on a side of the package substrate 220 remote from the package connection members 110, and the conductive connection 230 is disposed between the package substrate 220 and the printed circuit board to provide electrical connection between the package structure 500 and the printed circuit board.

Fig. 5A-5B illustrate methods of forming a package structure 200' according to further embodiments of the present disclosure. Referring to fig. 4E and 5A, in some embodiments, after removing carrier substrate 100, release layer 101, and seed layer 102 from the structure of fig. 4E to expose conductive pillars 105, bridge die BD, passive device die PD, and encapsulation layer 106, a planarization process (e.g., including a grinding process and/or a CMP process) may also be performed from the side of bridge die BD remote from interconnect structure 108 and dies 120 and 122 to remove substrate 80 of bridge die BD and expose interconnect structure 88 of bridge die BD. In some embodiments, the planarization process also removes portions of the encapsulation layer 106, passive device die PD, and conductive pillars 105 that are located on the sides of the substrate 80 bridging the die BD in a direction parallel to the major surfaces of the dies 120 and 220.

In some embodiments, as shown in fig. 5A, after the planarization process, the surfaces of interconnect structure 88 (e.g., organic dielectric structure OS 1), passive device die PD, conductive pillars 105, and encapsulation layer 106 on the side away from interconnect structure 108 and dies 120 and 122 are substantially flush with each other in a direction parallel to the major surfaces of dies 120 and 122.

Referring to fig. 5A and 5B, the conductive connection 130 is formed on a side of the conductive pillar 105 away from the interconnection structure 108, thereby forming a package structure 200'. In some embodiments, the package structure 200' may be further connected to other package components, such as the package substrate 220, by the conductive connection 130. The conductive connection 230 may be formed on a side of the package substrate 220 remote from the conductive connection 130, and thus the package structure 500'.

It should be understood that the above process of removing the substrate bridging the die is merely illustrative, and the embodiments of the present disclosure are not limited thereto. For example, in an alternative embodiment, the substrate 80 may be removed prior to mounting the bridge die BD to the carrier substrate 100 in the packaging process of fig. 4B, such that at the step of fig. 4B, the bridge die BD including the interconnect structure 88 but not the substrate 80 is mounted to the carrier substrate 100, thereby such that the bridge die BD does not include the substrate 80 in the final packaging structure 200'. For example, in the process of forming the bridge die BD of fig. 3A-3F, the substrate 80 is removed after the interconnect structure 88 is formed on the substrate 80 and before the dicing process, followed by the dicing process such that the formed bridge die BD does not include the substrate 80. In this embodiment, removing the substrate 80 may include forming a release layer on the substrate 80 prior to forming the organic dielectric layer 81, and after forming the interconnect structure 88, exposing the release layer to light to cause the release layer to decompose under the influence of light and lose its tackiness, thereby disengaging the substrate 80 from the interconnect structure 88; alternatively, the substrate 80 may be removed using a CMP or the like process.

In such embodiments, since the substrate 80 of the bridge die BD is eventually removed, the difference in thermal expansion coefficient between the bridge die BD and the encapsulation layer 106 may be further reduced, and thus the problem of package warpage or the like due to the thermal expansion coefficient mismatch between the bridge die BD and the encapsulation layer 106 may be further avoided. Also, in this embodiment, the material selection of the substrate 80 in the fabrication process of the bridge die BD of fig. 3A-3K may not take into account the impact on the subsequent packaging process, and thus the material selection is more free.

The following points need to be described:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A package structure, comprising:

a first die and a second die; and

a package connection member including a bridge die and an encapsulation layer, the package connection member being disposed on one side of the first die and the second die in a first direction perpendicular to a major surface of the first die and the second die and electrically connected to the first die and the second die,

wherein the bridge die comprises at least a first interconnect structure comprising a first organic dielectric structure and a first rerouting structure embedded in the first organic dielectric structure and configured to electrically connect the first die to the second die; and

the encapsulation layer is disposed on sides of the bridge die in a second direction parallel to the major surfaces of the first die and the second die and encapsulates at least sidewalls of the bridge die.

2. The package structure of claim 1, wherein the package connection member further comprises: and the conductive columns are positioned on the side edges of the bridging die in the first direction and laterally encapsulated by the encapsulation layer, wherein the conductive columns provide electrical connection between the first die and the second die and an external conductive connecting piece.

3. The package structure of claim 2, wherein the package connection member further comprises: and a second interconnect structure disposed between the bridge die, the encapsulation layer, the conductive pillars, and the first and second dies in the first direction, and the second interconnect structure comprising a second organic dielectric structure and a second redistribution structure embedded in the second organic dielectric structure, wherein the first and second dies are electrically connected to each other through a first portion of the second redistribution structure and the bridge die, and electrically connected to the conductive pillars through a second portion of the second redistribution structure.

4. The package structure of claim 3, wherein a pitch of a re-wiring layer in the first re-wiring structure is less than a pitch of a re-wiring layer in the second re-wiring structure.

5. The package structure of claim 1, wherein the first organic dielectric structure and the first re-wiring structure comprise at least one organic dielectric layer and at least one re-wiring layer stacked on top of each other, a first re-wiring layer of the at least one re-wiring layer comprises a seed layer and a conductive layer, and an orthographic projection of the seed layer on a major surface of the first organic dielectric structure in the first direction is within an orthographic projection of the conductive layer on the major surface of the first organic dielectric structure in the first direction.

6. The package structure of claim 5, wherein in the second direction, sidewalls of the seed layer are laterally recessed relative to sidewalls of the conductive layer.

7. The package structure of claim 5, wherein the conductive layer has sidewalls in contact with the at least one organic dielectric layer.

8. The package structure of claim 1, wherein

The first organic dielectric structure includes a first organic dielectric layer and a second organic dielectric layer;

the first rerouting structure includes an initial rerouting layer and a first rerouting layer, the initial rerouting layer being embedded in the first organic dielectric layer, and the first rerouting layer extending through the first organic dielectric layer to connect to the initial rerouting layer;

the first redistribution layer includes a via portion in the first organic dielectric layer and a trace portion in the second organic dielectric layer, wherein a major surface of the second organic dielectric layer is closer to the first die and the second die than a major surface of the trace portion of the second redistribution layer.

9. The package structure of claim 1, wherein the organic dielectric structure comprises a polymeric material.

10. The package structure of claim 1, wherein the encapsulation layer comprises an organic dielectric material.

11. The package structure of claim 1, wherein a surface of the first interconnect structure of the bridge die remote from the first die and the second die is flush with a surface of the encapsulation layer remote from the first die and the second die in the second direction.

12. The package structure of claim 1, wherein the bridge die further comprises a substrate located on a side of the first interconnect structure remote from the first die and the second die, and a portion of the encapsulation layer is located on a side of the substrate in the second direction.

13. The package structure of claim 12, wherein the substrate comprises a semiconductor substrate or an insulating substrate.

14. The package structure of claim 1, further comprising:

and the passive device die is embedded in the packaging connecting member, is arranged side by side with the bridging die in the second direction, is laterally encapsulated by the encapsulating layer, and is electrically connected with at least one of the first die and the second die.

15. The package structure of claim 14, wherein the passive device die comprises a deep trench capacitor.

16. The package structure of any of claims 1-15, further comprising:

the conductive connecting piece is arranged on one side of the packaging connecting member, which is far away from the first die and the second die, and is electrically connected to the first die and the second die through the packaging connecting member; and

the packaging substrate is arranged on one side, far away from the packaging connecting member, of the conductive connecting piece and is electrically connected to the first die and the second die through the conductive connecting piece and the packaging connecting member.

17. A method for forming a package structure includes:

providing a first die and a second die; and

forming a package connection member to be electrically connected to the first die and the second die, the package connection member being disposed on one side of the first die and the second die in a first direction perpendicular to main surfaces of the first die and the second die, wherein forming the package connection member includes:

forming a bridge die, the bridge die including at least a first interconnect structure including a first organic dielectric structure and a first rerouting structure embedded in the first organic dielectric structure and configured to electrically connect the first die to the second die; and

An encapsulation layer is formed on the sides of the bridge die in a second direction parallel to the major surfaces of the first and second die to encapsulate the sidewalls of the bridge die.

18. The method of forming a package structure of claim 17, wherein forming the bridge die comprises: providing a substrate; and forming the first interconnection structure on the substrate, wherein forming the first interconnection structure comprises:

forming an initial organic dielectric layer on the substrate, and forming an initial rerouting layer on a side of the initial organic dielectric layer remote from the substrate;

forming a first organic dielectric layer having an opening on a side of the initial organic dielectric layer and the initial re-wiring layer away from the substrate, the opening exposing a portion of a surface of the initial re-wiring layer away from the substrate;

forming a seed layer on the first organic dielectric layer, and the seed layer filling into the opening to contact the initial redistribution layer;

forming a conductive layer on a first portion of the seed layer; and

a second portion of the seed layer not covered by the conductive layer is removed, and the remaining first portion of the seed layer and the conductive layer constitute a first rerouting layer electrically connected to the initial rerouting layer.

19. The method of forming a package structure of claim 18, wherein forming the conductive layer on the first portion of the seed layer comprises:

forming a patterned mask layer having a mask opening over the seed layer to cover the second portion of the seed layer and the mask opening exposing the first portion of the seed layer; and

the conductive layer is formed on the first portion of the seed layer in the mask opening.

20. The method of claim 19, wherein removing the second portion of the seed layer not covered by the conductive layer comprises:

removing the patterned mask layer; and

and taking the conductive layer as an etching mask, and carrying out an etching process on the seed crystal layer.

21. The method of forming a package structure of claim 18, further comprising:

the substrate of the bridge die is removed and the first interconnect structure and the encapsulation layer of the bridge die are made to have surfaces that are flush with each other in the second direction on a side away from the first die and the second die.

22. The method of forming a package structure of claim 17, wherein forming the package connection member further comprises:

Before forming the encapsulation layer, forming a conductive pillar, wherein the conductive pillar is disposed at a side of the bridge die in the second direction, and the encapsulation layer is formed to also encapsulate a sidewall of the conductive pillar.

23. The method of forming a package structure of claim 22, wherein forming the package connection member further comprises:

forming a second interconnect structure on a side of the bridge die, the conductive pillars, and the encapsulation layer proximate to the first die and the second die, the second interconnect structure including a second organic dielectric structure and a second redistribution structure embedded in the second organic dielectric structure, wherein the first die and the second die are electrically connected to the bridge die and the conductive pillars through the second redistribution structure.

24. The method of forming a package structure of claim 17, wherein prior to forming the encapsulation layer, further comprising:

a passive device die is provided, the passive device die and the bridge die being disposed side-by-side in the second direction, and the encapsulation layer being formed to also encapsulate sidewalls of the passive device die.

25. The method of forming a package structure of claim 17, further comprising:

Forming a conductive connection on a side of the package connection member remote from the first die and the second die; and

and electrically connecting the conductive connecting piece to the packaging substrate.