CN116055243A - Method for controlling system address mapping of power semiconductor wire bonding machine - Google Patents
Method for controlling system address mapping of power semiconductor wire bonding machine Download PDFInfo
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- CN116055243A CN116055243A CN202211180603.5A CN202211180603A CN116055243A CN 116055243 A CN116055243 A CN 116055243A CN 202211180603 A CN202211180603 A CN 202211180603A CN 116055243 A CN116055243 A CN 116055243A
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- 238000013507 mapping Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/25—Mapping addresses of the same type
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Control By Computers (AREA)
Abstract
The invention provides a method for controlling system address mapping of a power semiconductor wire bonding machine, which comprises the following steps: s1: searching a mapping address, and searching the mapping address needing to be written with data through an address bus; s2: analyzing the mapping address, analyzing the mapping address searched in the step S1, and further determining the address of the control card where data need to be written; s3: and (2) writing data, and writing related data through a data bus and a control bus according to the control card address analyzed in the step (S2). The method for mapping the address of the power semiconductor wire bonding machine control system directly carries out global address operation when the remote control card is operated, and can be mapped to an actual register of a final control card through hardware.
Description
Technical Field
The invention relates to the technical field of semiconductor encapsulation, in particular to a method for mapping an address of a control system of a power semiconductor wire bonding machine.
Background
The production process of the power semiconductor product is divided into three processes of design, manufacture and seal test, and the main processing technology in the seal test production link is divided into Diebond and wire bond; wire bonding is mainly aimed at welding a thick aluminum wire (100-500 um) to a welding point of a chip and a lead frame under the action of external force by using an ultrasonic mechanism; the wire bonding machine needs to control 17 motors, 58 input/output circuits, at least 4 analog input circuits and 4 analog output circuits simultaneously in a full-speed working state.
The traditional communication has a corresponding unique address on each terminal control device, and when the communication protocol frame is written in the address of the target device, the read-write operation can be carried out on the target device.
Disclosure of Invention
The invention aims to provide a method for controlling system address mapping of a power semiconductor wire bonding machine, which can directly communicate with a terminal control card and is convenient and simple to set through address mapping.
Embodiments of the present invention are implemented as follows:
the embodiment of the invention provides a method for controlling system address mapping of a power semiconductor wire bonding machine, which comprises the following steps:
s1: lookup mapping address
Searching a mapping address to be written with data through an address bus;
s2: analyzing mapped addresses
Analyzing the mapping address searched in the step S1, and further determining the address of the control card where data need to be written;
s3: writing data
And (2) writing related data through the data bus and the control bus according to the control card address analyzed in the step (S2).
Optionally, the address bus is 32 bits, the data bus is 32 bits, and the control bus is 8 bits.
Optionally, the 32 bits of the address bus are divided into the upper 16 bits of the address bus and the lower 16 bits of the address bus.
Optionally, the data bus 32 bits are actual read-write data, and specific read-write operations are controlled by a control bus.
Alternatively, the address bus high 16 bits address can be set on the remote card, the address bus low 16 bits being used to select the actual registers in the terminals.
Optionally, in step S2, only the high 16 bits of the address bus are the same as the high 16 bits set on the terminal card, and the remote terminal card will respond to the read/write operation.
Alternatively, the number of the control cards can be controlled to be 0x 0000-0 xffff, 65536 in total, and the number of the address mappings in each card can be 0x 0000-0 xffff, 65536 in total.
Alternatively, the addresses can map registers 0x00000000 to 0 xffffffffff bytes of data in total.
Optionally, the address in the address bus can directly perform read-write operation to the 32-bit address through the IPC controller, and directly communicate with and are set by the terminal control card through address mapping.
Optionally, the mapping address searched in the step S1 is a unique identification address respectively provided by a plurality of distributed control cards communicating with the industrial control host.
The beneficial effects of the embodiment of the invention include: the embodiment of the invention provides a method for controlling system address mapping by a power semiconductor wire bonding machine, which is characterized in that 32 bits of an address bus are divided into high 16 bits of the address bus and low 16 bits of the address bus, the high 16 bits of the address bus are set on a remote card, a remote terminal card is controlled to respond and perform read-write operation, when the remote control card is operated, global addresses are directly performed to perform operation, the global addresses can be mapped onto an actual register of a final control card through hardware, the global addresses can be directly communicated and set with the terminal control card through address mapping, and an industrial control host can be respectively communicated with a plurality of control cards through address mapping, so that a plurality of devices can be simultaneously controlled to work.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below. Thus, the following detailed description of the embodiments of the invention is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a method for controlling system address mapping of a power semiconductor wire bonding machine, which comprises the following steps:
s1: lookup mapping address
Searching a mapping address to be written with data through an address bus;
s2: analyzing mapped addresses
Analyzing the mapping address searched in the step S1, and further determining the address of the control card where data need to be written;
s3: writing data
And (2) writing related data through the data bus and the control bus according to the control card address analyzed in the step (S2).
As an embodiment of the present invention, the address bus is 32 bits, the data bus is 32 bits, and the control bus is 8 bits.
As one embodiment of the present invention, the 32 bits of the address bus are divided into the upper 16 bits of the address bus and the lower 16 bits of the address bus.
As one embodiment of the invention, the data bus 32 bits are the actual read-write data, and the specific read-write operation is controlled by the control bus.
As one embodiment of the invention, the address of the upper 16 bits of the address bus can be set on the remote card, the lower 16 bits of the address bus being used to select the actual registers within the terminals.
As an implementation mode of the invention, in the step S2, only the high 16 bits of the address bus are the same as the high 16 bits arranged on the terminal card, the remote terminal card can respond to the read-write operation, and the specific function descriptions of the address bus, the data bus and the control bus are shown in the following table:
and (C) a first table.
As one embodiment of the invention, the number of the address mappable control cards is 0x 0000-0 xffff, 65536 in total, and the number of address mappable cards in each card is 0x 0000-0 xffff, 65536 in total.
As an embodiment of the present invention, the addresses can map the registers 0x00000000 to 0xffffffff bytes of data in total.
As one implementation mode of the invention, the address in the address bus can be directly read and written to a 32-bit address through the IPC controller, and is directly communicated with and set by the terminal control card through address mapping, when the host writes data 0x12345678 into the mapping address 0x12000010, the upper 16 bits of the address are 0x1200, the lower 16 bits are 0x0010, which means that the address 0x0010 is written into the control card set as 0x1200, and 4 bytes of data are 0x12345678.
It should be noted that the invention is a method for mapping addresses of a control system of a power semiconductor wire bonding machine, which divides 32 bits of an address bus into high 16 bits of the address bus and low 16 bits of the address bus, and sets the high 16 bits of the address bus on a remote card to control a remote terminal card to respond and perform read-write operation.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for controlling system address mapping of a power semiconductor wire bonding machine, comprising the steps of:
s1: lookup mapping address
Searching a mapping address to be written with data through an address bus;
s2: analyzing mapped addresses
Analyzing the mapping address searched in the step S1, and further determining the address of the control card where data need to be written;
s3: writing data
And (2) writing related data through the data bus and the control bus according to the control card address analyzed in the step (S2).
2. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 1 wherein: the address bus is 32 bits, the data bus is 32 bits, and the control bus is 8 bits.
3. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 1 wherein: the 32 bits of the address bus are divided into the upper 16 bits of the address bus and the lower 16 bits of the address bus.
4. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 1 wherein: the 32 bits of the data bus are actual read-write data, and specific read-write operation is controlled by the control bus.
5. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 3 wherein: the address of the upper 16 bits of the address bus can be set on the remote card, the lower 16 bits of the address bus being used to select the actual register in the terminal.
6. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 5 wherein: in the step S2, only the high 16 bits of the address bus are the same as the high 16 bits set on the terminal card, and the remote terminal card will respond to the read-write operation.
7. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 1 wherein: the number of the control cards can be mapped to 0x 0000-0 xffff, 65536 in total, and the number of the address mappings in each card is 0x 0000-0 xffff, 65536 in total.
8. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 7 wherein: the addresses can map the registers 0x00000000 to 0 xffffffffff bytes of data in total.
9. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 1 wherein: the address in the address bus can be directly read and written to the 32-bit address through the IPC controller, and is directly communicated with and set by the terminal control card through address mapping.
10. A method of controlling system address mapping for a power semiconductor wire bonding machine as claimed in claim 1 wherein: the mapping address searched in the step S1 is a unique identification address respectively provided by a plurality of distributed control cards communicating with the industrial control host.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211180603.5A CN116055243A (en) | 2022-09-27 | 2022-09-27 | Method for controlling system address mapping of power semiconductor wire bonding machine |
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| CN202211180603.5A CN116055243A (en) | 2022-09-27 | 2022-09-27 | Method for controlling system address mapping of power semiconductor wire bonding machine |
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2022
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