CN116054573A

CN116054573A - Protection circuit of booster circuit, booster device and electronic equipment

Info

Publication number: CN116054573A
Application number: CN202310107986.1A
Authority: CN
Inventors: 于欣然; 赵新江
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2023-01-31
Filing date: 2023-01-31
Publication date: 2023-05-02

Abstract

The utility model provides a boost circuit's protection circuit, booster unit and electronic equipment, belongs to electron technical field. In the protection circuit, the switch control circuit is configured to transmit a switch control signal to the switch circuit based on a potential of an intermediate node of the booster circuit. The bias circuit is used for transmitting a bias signal to the switch circuit based on an input signal provided by an input end of the boost circuit. The switch circuit is used for transmitting a protection control signal to the protection control terminal based on the switch control signal and the bias signal. Since the switch control signal is related to the potential of the intermediate node and the bias signal is related to the input signal, the protection control signal can be related to the potential of the intermediate node and the input signal. Furthermore, when the boost circuit is short-circuited, the potential of the intermediate node can be controlled, the current on the inductor can be slowly reduced, the self-adaptive current limiting during the short circuit is realized, and meanwhile, the occurrence of overvoltage is avoided. The protection of the internal devices of the booster circuit can be realized, and the working safety of the booster circuit is ensured to be better.

Description

Protection circuit of booster circuit, booster device and electronic equipment

Technical Field

The disclosure relates to the field of electronic technology, and in particular, to a protection circuit of a booster circuit, a booster device and electronic equipment.

Background

A boost (boost) circuit is a circuit that boosts an input voltage received at an input terminal so that an output voltage at an output terminal is greater than the input voltage. Boost circuits are commonly used to couple and power loads.

In the related art, a booster circuit generally includes: a switching circuit and a charge-discharge circuit. The charge-discharge circuit generally includes: inductance and capacitance, a switching circuit generally includes: a plurality of switching tubes, or a switching tube and a diode. And the charge-discharge circuit is respectively coupled with the input end, the output end and the ground end. The switch circuit is coupled with the charge-discharge circuit, the output end and the ground end respectively. The switch circuit is used for controlling the on-off state between the charge-discharge circuit and the ground terminal so as to enable the charge-discharge circuit to perform charge-discharge actions, thereby realizing boosting treatment on input voltage and enabling output voltage to be larger than the input voltage.

However, once the boost circuit is shorted (e.g., shorted on the output side), a large short-circuit current is generated, and thus internal devices (e.g., switching tubes) are damaged, which results in poor working safety.

Disclosure of Invention

The protection circuit, the boosting device and the electronic equipment of the boosting circuit are provided, and the problem that the working safety of the boosting circuit in the related technology is poor can be solved. The technical scheme is as follows:

In one aspect, a protection circuit of a boost circuit is provided, wherein the boost circuit is respectively coupled with an input end, an intermediate node, a protection control end, an output end and a pull-down power supply end; the protection circuit includes: a switch control circuit, a bias circuit and a switch circuit;

the switch control circuit is respectively coupled with the intermediate node, the pull-down power supply end and the control end of the switch circuit, and is used for transmitting a switch control signal to the control end of the switch circuit based on the potential of the intermediate node and the pull-down power supply signal provided by the pull-down power supply end;

the bias circuit is respectively coupled with the input end, the pull-down power supply end and the input end of the switch circuit, and is used for transmitting bias signals to the input end of the switch circuit based on the input signals provided by the input end and the pull-down power supply signals;

the output end of the switch circuit is coupled with the protection control end, and the switch circuit is used for transmitting a protection control signal to the protection control end based on the switch control signal received by the control end and the bias signal received by the input end, so as to instruct the boost circuit to control the on-off of the intermediate node and the output end.

Optionally, the bias circuit includes a first bias sub-circuit, a first switch control sub-circuit, and a switch sub-circuit;

the first bias sub-circuit is coupled with the pull-down power supply end and the first switch control sub-circuit respectively, and is used for receiving a first bias power supply signal and generating a first bias current for the first switch control sub-circuit based on the first bias power supply signal and the pull-down power supply signal;

the first switch control sub-circuit is further coupled to the input terminal and the control terminal of the switch sub-circuit, respectively, and is configured to transmit a switch signal to the control terminal of the switch sub-circuit based on the input signal and the first bias current;

the input end of the switch sub-circuit is coupled with the pull-down power supply end, the output end of the switch sub-circuit is coupled with the input end of the switch circuit, and the switch sub-circuit is used for transmitting a bias signal to the input end of the switch circuit based on the switch signal and the pull-down power supply signal.

Optionally, the first bias sub-circuit includes: a first switching transistor, a second switching transistor, and a first current source;

The input end of the first current source is used for receiving the first bias power supply signal, and the output end of the first current source is respectively coupled with the grid electrode of the first switch transistor, the first pole of the first switch transistor and the grid electrode of the second switch transistor;

the gate of the first switching transistor is coupled to the gate of the second switching transistor, the second pole of the first switching transistor and the second pole of the second switching transistor are both coupled to the pull-down power supply terminal, and the first pole of the second switching transistor is coupled to the coupling nodes of the first switching control sub-circuit and the switching sub-circuit.

Optionally, the first switch control sub-circuit includes: a plurality of third switching transistors connected in series;

among the plurality of third switching transistors connected in series, a first pole of the third switching transistor at one end is coupled with the input end, and a second pole of the third switching transistor at the other end is coupled with the control end of the switching sub-circuit and the first bias sub-circuit respectively;

in every two third switching transistors connected in series, the first pole of one third switching transistor is coupled with the second pole of the other third switching transistor;

And, for each third switching transistor, a gate of the third switching transistor is coupled to a first pole of the third switching transistor.

Optionally, the first switch control sub-circuit includes: and three third switching transistors connected in series.

Optionally, the first switch control sub-circuit includes: a first zener diode;

the positive electrode of the first zener diode is respectively coupled with the control end of the switch sub-circuit and the first bias sub-circuit, and the negative electrode of the first zener diode is coupled with the input end.

Optionally, the switch sub-circuit includes: a fourth switching transistor;

the grid electrode of the fourth switching transistor is coupled with the switch control sub-circuit, the first electrode of the fourth switching transistor is coupled with the pull-down power supply end, and the second electrode of the fourth switching transistor is coupled with the input end of the switching circuit.

Optionally, the bias circuit further includes:

a first capacitor connected in series between the input terminal and the control terminal of the switch sub-circuit;

a first resistor connected in series between the input terminal of the switching sub-circuit and the pull-down power supply terminal;

and the anode of the unidirectional conductive diode is coupled with the control end of the switch sub-circuit and the coupling node of the first capacitor, and the cathode of the unidirectional conductive diode is coupled with the output end of the switch sub-circuit.

Optionally, the switch control circuit includes: a second bias subcircuit and a second switch control subcircuit;

the second bias sub-circuit is coupled with the pull-down power supply end and the second switch control sub-circuit respectively, and is used for receiving a second bias power supply signal and generating a second bias current for the second switch control sub-circuit based on the second bias power supply signal and the pull-down power supply signal;

the second switch control sub-circuit is further coupled to the intermediate node and a control terminal of the switch circuit, respectively, and is configured to transmit a switch control signal to the control terminal of the switch circuit based on the potential of the intermediate node and the second bias current.

Optionally, the second bias sub-circuit includes: a fifth switching transistor, a sixth switching transistor, and a second current source;

the input end of the second current source is used for receiving the second bias power supply signal, and the output end of the second current source is respectively coupled with the grid electrode of the fifth switching transistor, the first pole of the fifth switching transistor and the grid electrode of the sixth switching transistor;

The gate of the fifth switching transistor is coupled to the gate of the sixth switching transistor, the second pole of the fifth switching transistor and the second pole of the sixth switching transistor are both coupled to the pull-down power supply terminal, and the first pole of the sixth switching transistor is coupled to the second switch control sub-circuit and the coupling node of the switching circuit.

Optionally, the second switch control sub-circuit includes: a second zener diode;

the positive electrode of the second zener diode is respectively coupled with the control end of the switch circuit and the second bias sub-circuit, and the negative electrode of the second zener diode is coupled with the intermediate node.

Optionally, the switch control circuit further includes:

a second capacitor connected in series between the intermediate node and the control terminal of the switching circuit;

a second resistor connected in series between the intermediate node and the output of the switching circuit;

and a third capacitor connected in series between the intermediate node and the protection control terminal.

Optionally, the switching circuit includes: a seventh switching transistor;

the gate of the seventh switching transistor is coupled to the switch control circuit, the first pole of the seventh switching transistor is coupled to the bias circuit, and the second pole of the seventh switching transistor is coupled to the protection control terminal.

In another aspect, there is provided a boosting device including: a booster circuit, and a protection circuit as described in the above aspect;

the boost circuit is respectively coupled with an input end, an intermediate node, a protection control end, an output end, a pull-down power end, a boost control end and a charge-discharge node, and is used for controlling the on-off of the charge-discharge node and the pull-down power end based on a boost control signal provided by the boost control end, regulating the potential of the intermediate node based on the potential of the charge-discharge node, controlling the on-off of the intermediate node and the output end based on a protection control signal provided by the protection control end, and controlling the potential of the charge-discharge node and the output end based on an input signal provided by the input end and a pull-down power signal provided by the pull-down power end;

the protection circuit is coupled with the intermediate node, the input terminal, the pull-down power supply terminal and the protection control terminal, respectively, and is used for transmitting a protection control signal to the protection control terminal based on the potential of the intermediate node, the input signal and the pull-down power supply signal.

In yet another aspect, an electronic device is provided, the electronic device including: a load, and a boosting device as described in the other aspect above;

In the boosting device, an input end of a boosting circuit is coupled with a power supply end, an output end of the boosting circuit is coupled with the load, and the boosting circuit is used for boosting a power supply signal provided by the power supply end to the input end and then transmitting the power supply signal to the load.

In summary, the beneficial effects brought by the technical solution provided by the embodiments of the present disclosure at least may include:

a protection circuit of a booster circuit, a booster device and an electronic device are provided. The protection circuit comprises a switch control circuit, a bias circuit and a switch circuit. The switch control circuit is coupled with the intermediate node coupled with the boost circuit and the control end of the switch circuit respectively. The bias circuit is coupled to the input terminal of the boost circuit and the input terminal of the switch circuit, respectively. The output end of the switch circuit is coupled with the protection control end coupled with the boost circuit. The switch control circuit is used for transmitting a switch control signal to a control end of the switch circuit based on the potential of the intermediate node. The bias circuit is used for transmitting a bias signal to the input end of the switch circuit based on the input signal provided by the input end. The switch circuit is used for transmitting a protection control signal to the protection control terminal based on the switch control signal and the bias signal. Since the switch control signal is related to the potential of the intermediate node and the bias signal is related to the input signal provided at the input terminal, it is known that the protection control signal transmitted to the protection control terminal may be related to the potential of the intermediate node and the potential of the input signal. Furthermore, when the boost circuit is short-circuited, the potential of the intermediate node can be controlled, and the current on the inductor and the potential on the intermediate node can be slowly reduced, so that the self-adaptive current limiting during short-circuit is realized, and meanwhile, the occurrence of overvoltage is avoided. Therefore, the protection of the internal devices of the booster circuit can be realized, and the working safety of the booster circuit is ensured to be better.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a boost circuit in the related art;

fig. 2 is a schematic diagram of a structure of another boost circuit in the related art;

fig. 3 is a schematic structural diagram of a protection circuit of a boost circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a protection circuit of another boost circuit provided in an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a protection circuit of a further boost circuit provided in an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a protection circuit of a further boost circuit provided in an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a protection circuit of a further boost circuit provided in an embodiment of the present disclosure;

FIG. 8 is a timing diagram of the operation of a protection circuit provided by an embodiment of the present disclosure;

Fig. 9 is a schematic structural diagram of a boosting device according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of another boost device provided in an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

On the basis of the background, fig. 1 shows a schematic circuit structure of a conventional booster circuit. As shown in fig. 1, the booster circuit includes: an inductor L0, an N-type switching transistor T1, a diode D0 (e.g., schottky diode), and a capacitor C0. Alternatively, the N-type switching transistor T1 may be an N-type metal oxide semiconductor (metal oxide Semiconductor, MOS) transistor, that is, the N-type switching transistor T1 may be an NMOS switching transistor, which is described as an example in the following embodiments.

Wherein, two ends of the inductance L0 may be coupled (i.e., electrically connected) to the input terminal Vin and the charge-discharge node Lx, respectively. The gate of the N-type switching transistor T1 may be coupled to the switch control terminal Ndriver, the first pole of the N-type switching transistor T1 may be coupled to the charge/discharge node Lx, and the second pole of the N-type switching transistor T1 may be coupled to the pull-down power terminal V1 (e.g., the ground terminal GND). The anode of the diode D0 may be coupled to the charge-discharge node Lx, and the cathode of the diode D0 may be coupled to the output terminal Vout. Both ends of the capacitor C0 may be coupled to the output terminal Vout and the pull-down power terminal V1, respectively. Based on the structure, when the N-type switching tube T1 is turned on based on the switching control signal of the effective potential provided by the switching control terminal Ndriver, the input terminal Vin can form a path through the inductor L0 and the N-type switching tube T1 to the ground GND, so as to charge the inductor L0 and store energy. When the N-type switching tube T1 is turned off based on a switching control signal of an invalid potential provided by the switching control terminal Ndriver, the current on the inductor L0 is not suddenly changed to 0, the inductor L0 starts to discharge and release energy, and the capacitor C0 is charged after passing through the diode D0, so that the output voltage of the output terminal Vout is greater than the input voltage provided by the input terminal Vin, and the boosting purpose is achieved. Furthermore, fig. 1 also schematically shows a load coupled to the output Vout, denoted by a resistor Rload. The boosted output voltage may be provided to the load to reliably power the load.

In the embodiment of the present disclosure, the effective potential and the ineffective potential only represent that the potential of the signal has 2 state quantities, and do not represent that the effective potential or the ineffective potential has a specific value. Of the first and second poles of the switching tube, one pole may be referred to as a source and the other pole may be referred to as a drain.

However, it has been found that when the boost circuit shown in fig. 1 is short-circuited (generally referred to as a short-circuit at load Rload), short-circuit protection cannot be achieved, and the short-circuit current is generally large. In addition, since the diode D0 cannot be completely turned off like a switching tube, the output terminal Vout cannot be reliably set to 0. Typically, after the input terminal Vin is powered up, the output terminal Vout is no longer 0. Based on this, a fuse is added on the output terminal Vout side, so that protection is achieved by fusing the fuse when a short circuit occurs. However, this approach has the disadvantage of requiring the addition of external devices (i.e., fuses) to achieve protection, inconvenient miniaturization of the volume, and inability to be integrated with the circuit. And when the output end Vout has a large parasitic capacitance, continuous large current may exist on the freewheeling path, which may cause the fuse to blow, thus the fuse cannot be normally started, and the use range of the output capacitance is limited. Based on this, the embodiment of the disclosure provides a new protection circuit of a boost circuit to realize better short-circuit protection.

First, referring to fig. 2, the boost circuit provided in the embodiment of the present disclosure may be coupled to the input terminal Vin, the intermediate node Vx, the protection control terminal Vcontrol, the output terminal Vout, and the pull-down power supply terminal V1, respectively. In addition, the boost circuit may be coupled to the charge-discharge node Lx, the switch control terminal Ndriver, and the switch control terminal Pdriver, respectively. In contrast to the structure shown in fig. 1, the boost circuit has the diode D0 replaced by two PMOS switching transistors T2 and T3 back to back, and the other structure is unchanged. On this basis, the booster circuit shown in fig. 2 may also be referred to as a back-to-back PMOS booster circuit.

The gate of the PMOS switching tube T2 may be coupled to the switch control terminal Pdriver, the first pole of the PMOS switching tube T2 may be coupled to the charge-discharge node Lx, and the second pole of the PMOS switching tube T2 may be coupled to the intermediate node Vx. The gate of the PMOS switch transistor T3 may be coupled to the switch control terminal Vcontrol, the second pole of the PMOS switch transistor T3 may be coupled to the intermediate node Vx, and the first pole of the PMOS switch transistor T3 may be coupled to the output terminal Vout. And, there is a parasitic diode between the first pole and the second pole of the PMOS switching transistor T2 and the PMOS switching transistor T3, which are respectively identified as D01 and D02 in the figure.

In the normal boost operation, the PMOS switching transistor T3 may be normally open, i.e., the intermediate node Vx and the output terminal Vout may be normally on. Then, the PMOS switching tube T2 may be turned on based on a switching control signal of an effective potential provided by the switch control terminal Pdriver, so that the charge-discharge node Lx is turned on with the intermediate node Vx, and further, the current on the inductor L0 is reliably discharged to the capacitor C0 through the PMOS switching tube T2 and the PMOS switching tube T3, so as to achieve the boosting purpose. During short circuit, a switch control signal with an invalid potential can be provided to the switch control terminal Vcontrol, so that the PMOS switch tube T3 is turned off, and electric leakage is prevented.

At present, the potential of the switch control signal provided by the switch control terminal Vcontrol is generally pulled up to be equal to the potential of the intermediate node Vx, so that the PMOS switch tube T3 is turned off, but this causes the current on the inductor L0 to have no path, so that the intermediate node Vx is overvoltage. If the PMOS switching transistor T3 is not controlled to turn off, the current cannot be limited as in the conventional boost circuit shown in fig. 1.

To this end, with continued reference to fig. 3, the disclosed embodiment provides a new protection circuit, which can provide a suitable switch control signal to the switch control terminal Vcontrol when a short circuit occurs, so as to avoid overvoltage of the intermediate node Vx, and also serve the purpose of limiting current. As shown in fig. 3, the protection circuit includes: a switch control circuit 01, a bias circuit 02 and a switch circuit 03.

The switch control circuit 01 is coupled to the intermediate node Vx, the pull-down power supply terminal V1, and the control terminal of the switch circuit 03, respectively. The switch control circuit 01 is configured to transmit a switch control signal to a control terminal of the switch circuit 03 based on the potential of the intermediate node Vx and a pull-down power supply signal provided by the pull-down power supply terminal V1. In this way, the switch control signal transmitted to the control terminal of the switch circuit 03 can be correlated with the potential of the intermediate node Vx.

The bias circuit 02 is coupled to the input terminal Vin, the pull-down power terminal V1, and the input terminal of the switching circuit 03, respectively. The bias circuit 02 is configured to transmit a bias signal to an input terminal of the switching circuit 03 based on an input signal provided at the input terminal Vin and a pull-down power supply signal. In this way, the bias signal transmitted to the input terminal of the switching circuit 03 can be correlated with the potential of the input signal supplied from the input terminal Vin.

The output of the switching circuit 03 is coupled to a protection control terminal Vcontrol. The switch circuit 03 is configured to transmit a protection control signal to the protection control terminal Vcontrol based on the switch control signal received by the control terminal and the bias signal received by the input terminal, so as to instruct the boost circuit shown in fig. 2 to control the on-off of the intermediate node Vx and the output terminal Vout. Because the switch control signal is related to the potential of the intermediate node Vx, the bias signal is related to the potential of the input signal provided by the input terminal Vin, it is known that the protection control signal provided to the protection control terminal Vcontrol may be related to the potential of the intermediate node Vx and/or the potential of the input signal provided by the input terminal Vin, so that when the boost circuit is shorted, the potential of the intermediate node Vx can be controlled, the current on the inductance L0 can be slowly reduced, the potential on the intermediate node Vx is also slowly reduced, and the adaptive current limiting during the short circuit is realized, and meanwhile, the occurrence of overvoltage is avoided.

In summary, the embodiments of the present disclosure provide a protection circuit of a boost circuit, a boost device, and an electronic device. The protection circuit comprises a switch control circuit, a bias circuit and a switch circuit. The switch control circuit is coupled with the intermediate node coupled with the boost circuit and the control end of the switch circuit respectively. The bias circuit is coupled to the input terminal of the boost circuit and the input terminal of the switch circuit, respectively. The output end of the switch circuit is coupled with the protection control end coupled with the boost circuit. The switch control circuit is used for transmitting a switch control signal to a control end of the switch circuit based on the potential of the intermediate node. The bias circuit is used for transmitting a bias signal to the input end of the switch circuit based on the input signal provided by the input end. The switch circuit is used for transmitting a protection control signal to the protection control terminal based on the switch control signal and the bias signal. Since the switch control signal is related to the potential of the intermediate node and the bias signal is related to the input signal provided at the input terminal, it is known that the protection control signal transmitted to the protection control terminal may be related to the potential of the intermediate node and the potential of the input signal. Furthermore, when the boost circuit is short-circuited, the potential of the intermediate node can be controlled, and the current on the inductor and the potential on the intermediate node can be slowly reduced, so that the self-adaptive current limiting during short-circuit is realized, and meanwhile, the occurrence of overvoltage is avoided. Therefore, the protection of the internal devices of the booster circuit can be realized, and the working safety of the booster circuit is ensured to be better.

Fig. 4 is a schematic structural diagram of another protection circuit according to an embodiment of the present disclosure. As shown in fig. 4, the bias circuit 02 in the protection circuit may include a first bias sub-circuit 021, a first switch control sub-circuit 022, and a switch sub-circuit 023.

The first bias subcircuit 021 may be coupled to the pull-down power supply terminal V1 and the first switch control subcircuit 022, respectively. The first bias subcircuit 021 may be configured to receive a first bias power supply signal and to generate a first bias current for the first switch control subcircuit 022 based on the first bias power supply signal and a pull-down power supply signal.

The first switch control sub-circuit 022 may also be coupled to the input terminal Vin and the control terminal of the switch sub-circuit 023, respectively. The first switch control sub-circuit 022 may be used to transmit a switch signal to a control terminal of the switch sub-circuit 023 based on the input signal and the first bias current.

An input terminal of the switching sub-circuit 023 may be coupled to the pull-down power supply terminal V1, and an output terminal of the switching sub-circuit 023 may be coupled to an input terminal of the switching circuit 03. The switching sub-circuit 023 may be used to transmit a bias signal to the input of the switching circuit 03 based on the switching signal and the pull-down power signal.

Fig. 5 is a schematic structural diagram of yet another protection circuit provided in an embodiment of the present disclosure. As shown in fig. 5, the switch control circuit 01 may include: a second bias subcircuit 011 and a second switch control subcircuit 012.

The second bias subcircuit 011 may be coupled to the pull-down power supply terminal V1 and the second switch control subcircuit 012, respectively. The second bias subcircuit 011 may be configured to receive a second bias power signal and to generate a second bias current for the second switch control subcircuit 012 based on the second bias power signal and the pull-down power signal.

The second switch control subcircuit 012 may also be coupled with the intermediate node Vx and the control terminal of the switch circuit 03, respectively. The second switch control sub-circuit 012 may be used to transmit a switch control signal to the control terminal of the switch circuit 03 based on the potential of the intermediate node Vx and the second bias current.

Fig. 6 is a schematic structural diagram of still another protection circuit according to an embodiment of the present disclosure. As shown in fig. 6, the first bias subcircuit 021 may include: a first switching transistor M1, a second switching transistor M2 and a first current source I1.

The input terminal of the first current source I1 is configured to receive a first bias power signal, and the output terminal of the first current source I1 may be coupled to the gate of the first switching transistor M1, the first pole of the first switching transistor M1, and the gate of the second switching transistor M2, respectively.

The gate of the first switching transistor M1 may be coupled to the gate of the second switching transistor M2, the second pole of the first switching transistor M1 and the second pole of the second switching transistor M2 may be both coupled to the pull-down power supply terminal V1, and the first pole of the second switching transistor M2 may be coupled to the coupling nodes of the first switching control sub-circuit 022 and the switching sub-circuit 023.

Optionally, as an alternative implementation, as can be seen with continued reference to fig. 6, the first switch control sub-circuit 022 described in the embodiments of the present disclosure may include: a plurality of third switching transistors M3 connected in series.

Among the plurality of third switching transistors M3 connected in series, a first pole of the third switching transistor M3 at one end is coupled to the input terminal Vin, and a second pole of the third switching transistor M3 at the other end is coupled to the control terminal of the switching sub-circuit 023 and the first bias sub-circuit 021, respectively.

Of every two third switching transistors M3 in series, the first pole of one third switching transistor M3 is coupled to the second pole of the other third switching transistor M3.

And, for each third switching transistor M3, the gate of the third switching transistor M3 is coupled to the first pole of the third switching transistor M3.

By way of example, the first switch control sub-circuit 022 shown in fig. 6 includes: three third switching transistors M3 in series, identified as M3-1, M3-2 and M3-3, respectively.

The first pole of the third switching transistor M3-1 is coupled to the input terminal Vin, the second pole of the third switching transistor M3-1 is coupled to the gate of the third switching transistor M3-1 and the first pole of the third switching transistor M3-2, the second pole of the third switching transistor M3-2 is coupled to the gate of the third switching transistor M3-2 and the first pole of the third switching transistor M3-3, and the second pole of the third switching transistor M3-3 is coupled to the gate of the third switching transistor M3-3 and the control terminal of the switching sub-circuit 023.

Alternatively, as another alternative implementation, referring to the schematic structure of the further protection circuit shown in fig. 7, the first switch control sub-circuit 022 may include: a first zener diode Zd1.

The positive electrode of the first zener diode Zd1 may be coupled to the control terminal of the switching sub-circuit 023 and the first bias sub-circuit 021, respectively, and the negative electrode of the first zener diode Zd1 may be coupled to the input terminal Vin.

Optionally, as can be seen with continued reference to fig. 6 and 7, the switch sub-circuit 023 described in the embodiments of the present disclosure may include: fourth switching transistor M4.

The gate of the fourth switching transistor M4 may be coupled to the switch control sub-circuit 021, the first pole of the fourth switching transistor M4 may be coupled to the pull-down power supply terminal V1, and the second pole of the fourth switching transistor M4 may be coupled to the input terminal of the switching circuit 03. Accordingly, it can be seen that the gate of the fourth switching transistor M4 is the control terminal of the switching sub-circuit 023, the first pole of the fourth switching transistor M4 is the input terminal of the switching sub-circuit 023, and the second pole of the fourth switching transistor M4 is the output terminal of the switching sub-circuit 023. And, in the structure shown in fig. 6, the gate of the fourth switching transistor M4 may be coupled to the second pole of the third switching transistor M3-3. In the structure shown in fig. 7, the gate of the fourth switching transistor M4 may be coupled to the anode of the first zener diode Zd1.

Taking the structure shown in fig. 6 as an example, assuming that the gate-source voltage difference Vgs of each third switching transistor M3 is equal to the gate-source voltage difference Vgs of the fourth switching transistor M4, it can be known that the bias signal Vbias transmitted by the bias circuit 02 to the switching circuit 03 may be: v_vin-Vgs 3_m3+vgs_m4=v_vin-2 Vgs. Taking the configuration shown in fig. 7 as an example, it is known that the bias signal Vbias transmitted from the bias circuit 02 to the switch circuit 03 may be: v_vin-v_zd1. Where v_vin refers to the potential of the input signal. V_zd1 refers to the voltage drop of the first zener diode Zd1.

Optionally, as can be seen with continued reference to fig. 6 and 7, the bias circuit 02 may further include:

a first capacitor C1 connected in series between the input terminal Vin and the control terminal of the switching sub-circuit 023.

A first resistor R1 connected in series between the input terminal of the switching sub-circuit 023 and the pull-down power supply terminal V1.

And a unidirectional conductive diode D1. The positive electrode of the unidirectional conductive diode D1 may be coupled to the control terminal of the switching sub-circuit 023 and the coupling node of the first capacitor C1, and the negative electrode of the unidirectional conductive diode D1 may be coupled to the output terminal of the switching sub-circuit 023.

The first capacitor C1 may be used to store the potential of the gate of the fourth switching transistor M4. The first resistor R1 may be used as a pull-down resistor to pull down the first pole of the fourth switching transistor M4 to ground. The unidirectional conductive diode D1 may be used to control unidirectional conductive characteristics between the gate and the second pole of the fourth switching transistor M4. This ensures that the fourth transistor M4 can be kept in an operating state even when the booster circuit is short-circuited, and is not damaged by the short circuit. The operational reliability of the protection circuit can be ensured.

Alternatively, as can be seen with continued reference to fig. 6 and 7, as with the first bias subcircuit 021, the second bias subcircuit 011 can include: a fifth switching transistor M5, a sixth switching transistor M6 and a second current source I2.

The input terminal of the second current source I2 may be configured to receive the second bias power signal, and the output terminal of the second current source I2 may be coupled to the gate of the fifth switching transistor M5, the first pole of the fifth switching transistor M5, and the gate of the sixth switching transistor M6, respectively.

The gate of the fifth switching transistor M5 may be coupled to the gate of the sixth switching transistor M6, the second pole of the fifth switching transistor M5 and the second pole of the sixth switching transistor M6 may be both coupled to the pull-down power supply terminal V1, and the first pole of the sixth switching transistor M6 may be coupled to the coupling node of the second switching control subcircuit 012 and the switching circuit 03.

Alternatively, as can be seen with continued reference to fig. 6 and 7, the second switch control subcircuit 012 may include: and a second zener diode Zd2.

The anode of the second zener diode Zd2 may be coupled to the control terminal of the switching circuit 03 and the second bias sub-circuit 011, respectively, and the cathode of the second zener diode Zd2 may be coupled to the intermediate node Vx.

On the basis, the switch control signal transmitted from the switch control circuit 01 to the switch circuit 03 may be: V_VxV_Zd2. Where V_Vx refers to the potential of the intermediate node Vx. V_zd2 refers to the voltage drop of the second zener diode Zd2.

Of course, like the first switch control sub-circuit 022, the second switch control sub-circuit 012 may also include a plurality of switch transistors connected in series between the intermediate node Vx and the control terminal of the switch circuit 03, and the series connection manner is the same as the third switch transistor M3 in the first switch control sub-circuit 022, which is not described herein again.

Optionally, as can be seen with continued reference to fig. 6 and 7, the switch control circuit 01 may further comprise:

a second capacitor C2 connected in series between the intermediate node Vx and the control terminal of the switching circuit 03.

A second resistor R2 connected in series between the intermediate node Vx and the output of the switching circuit 03.

And a third capacitor C3 connected in series between the intermediate node Vx and the protection control terminal Vcontrol.

The second capacitor C2 can be used to store the potential of the control terminal of the switching circuit 03. The third capacitor C3 may be used to store the potential of the protection control terminal Vcontrol. The second resistor R2 may act as a pull-up resistor pulling up the output of the switching circuit 03 to the intermediate node Vx. This also ensures that the switching circuit 03 can be kept in an operating state even when the boost circuit is short-circuited, and is not destroyed by the short circuit. The operational reliability of the protection circuit can be ensured.

Alternatively, as can be seen with continued reference to fig. 6 and 7, the switching circuit 03 may comprise: and a seventh switching transistor M7.

The gate of the seventh switching transistor M7 may be coupled to the switch control circuit 01, the first pole of the seventh switching transistor M7 may be coupled to the bias circuit 02, and the second pole of the seventh switching transistor M7 may be coupled to the protection control terminal Vcontrol. Accordingly, the gate of the seventh switching transistor M7 is the control terminal of the switching circuit 03, the first pole of the seventh switching transistor M7 is the input terminal of the switching circuit 03, and the second pole of the seventh switching transistor M7 is the output terminal of the switching circuit 03. And, in the structures shown in fig. 6 and 7, the gate of the seventh switching transistor M7 may be coupled with the anode of the second zener diode Zd2. The first pole of the seventh switching transistor M7 may be coupled with the second pole of the fourth switching transistor M4.

Taking the boost circuit shown in fig. 2 and the protection circuit shown in fig. 6 as examples, fig. 8 shows an operation timing chart. With reference to fig. 8, the working principle of the protection circuit provided by the embodiment of the disclosure is described as follows:

first, as described in the above embodiments, the switch control signal transmitted from the switch control circuit 01 to the control terminal of the switch circuit 03 (i.e., the gate of the seventh switch transistor M7) may be v_vx-v_zd2, i.e., the potential of the gate of the seventh switch transistor M7 is: V_VxV_Zd2. The bias signal transmitted by the bias circuit 02 to the input terminal of the switch circuit 03 (i.e., the first pole of the seventh switch transistor M7) may be v_vin-2Vgs, i.e., the potential of the first pole of the seventh switch transistor M7 is: V_Vin-2Vgs.

Second, during the start-up phase (i.e., the charging phase before discharging) of the boost circuit, the potential v_vx of the intermediate node Vx is lower than the potential v_vin of the input signal provided by the input terminal Vin by a voltage drop v_d01 of the body diode D01, i.e., v_vx=v_vin-v_d01, typically v_d01 is about 0.7 volts (V). And the voltage drop v_zd2 of the second zener diode Zd2 is typically about 5.5V. Therefore, it can be seen that at this stage, the potential vg_m7=v_vx-v_zd2 of the gate of the seventh transistor M7 is smaller than the potential v_vin-2Vgs of the first pole of the seventh transistor M7. That is, vg_M7=V_Vx-V_Zd < V_vin-2Vgs. Thus, the potential of the second pole of the seventh transistor M7 may be equal to the potential of the first pole of the seventh transistor M7. That is, the potential V_Vcontrol of the protection control signal transmitted by the switch circuit 03 to the protection control terminal Vcontrol may be V_vin-2Vgs. At this time, the starting surge (inrush) current of the boost circuit may be determined by the gate-source voltage difference vgs_t3 of the PMOS switching transistor T3. Vgs_t3=v_vcontrol-v_vx= (v_vin-2 Vgs) - (v_vin-v_d01) = - (2 Vgs-v_d01). Thus, the aim of controlling inrush current is achieved.

During the discharge phase, the potential v_vout of the output signal of the output terminal Vout may be greater than the potential v_vin of the input signal during normal boosting. At this time, the potential of the second pole of the seventh transistor M7 may be determined by the potential of the gate of the seventh transistor M7, that is, the potential v_vcontrol of the protection control signal transmitted to the protection control terminal Vcontrol may be determined by the potential v_vx of the intermediate node Vx. V_vcontrol=v_vx-v_zd2+vgs_t7, vgs_t7 refers to the gate-source voltage difference of the seventh transistor M7. In general, vgs_t7 is about 1V, then v_vcontrol=v_vx-5.5+1=v_vx-4.5. At this time, the PMOS switching transistor T3 may be fully turned on, so as to ensure that the intermediate node Vx and the output terminal Vout are reliably turned on, so that the potential v_vout of the output terminal Vout may be equal to the potential v_vx of the intermediate node Vx, i.e., so that v_vout=v_vx. Meanwhile, the protection control terminal Vcontrol can be used as a group signal of a high-voltage domain.

Once the short circuit occurs, as shown in fig. 8, the potential v_vout of the output signal output by the output terminal Vout, the potential v_vin of the input signal input by the input terminal Vin, and the potential v_vcontrol of the protection control signal provided by the protection control terminal Vcontrol are all pulled down instantaneously. At this time, the second pole of the seventh switching transistor M7 may still receive the bias signal: v_vin-2Vgs, and charges the PMOS switching transistor T3, i.e., the potential v_vcontrol=v_vin-2 Vgs of the protection control signal that the switching circuit 03 transmits to the protection control terminal Vcontrol. In addition, when the short circuit occurs, the switch control signals of the inactive potential shown in fig. 8 may be transmitted to the switch control terminals Ndriver and Pdriver, so that the NMOS switch tube T1 and the PMOS switch tube T2 are turned off. Further, the current I_L0 on the inductor L0 can charge the intermediate node Vx through the body diode D01. When the potential V_Vx of the intermediate node Vx is charged higher than V_Vin+V_D01, the current I_L0 on the inductor L0 can start to drop. On the basis of the potential rise of the intermediate node Vx, the gate-source voltage difference vgs_t3 of the PMOS switching transistor T3 can rise synchronously, and when the gate-source voltage difference vgs_t3 of the PMOS switching transistor T3 rises to a level such that all the current i_l0 on the inductor L0 flows through the PMOS switching transistor T3, the potential v_vx of the intermediate node Vx can stop rising. Since the potential v_vcontrol of the protection control signal has already been determined, the highest potential of the intermediate node Vx can also be controlled. Eventually, the current i_l0 on the inductance L0 may slowly decrease, while the potential v_vx of the intermediate node Vx may also slowly decrease. Thus, the self-adaptive current limiting during short circuit is realized, and overvoltage is avoided.

Based on the description of the embodiments, the protection circuit provided by the embodiment of the disclosure has a simple structure, can adaptively limit short-circuit current, limit startup inrush current, generate a group signal of a high-voltage domain, and has a wide application range. For example, it can be applied not only to the back-to-back asynchronous booster circuit shown in fig. 2, but also to the conventional asynchronous circuit shown in fig. 1. In the application in fig. 1, the PMOS switching transistor T3 may be directly connected in series between the diode D0 and the output terminal Vout, as in fig. 2. The coupling node between the PMOS switching transistor T3 and the cathode of the diode D0 is the intermediate node Vx.

Fig. 9 is a schematic structural diagram of a boosting device according to an embodiment of the disclosure. As shown in fig. 9, the boosting device includes: a booster circuit 10, and a protection circuit 00 as shown in any one of fig. 3 to 7.

As can be seen in fig. 2, the boost circuit 10 is coupled to the input terminal Vin, the intermediate node Vx, the protection control terminal Vcontrol, the output terminal Vout, the pull-down power supply terminal V1, the boost control terminal, and the charge-discharge node Lx, respectively. The boost control end includes: and the switch control terminals Pdriver and Ndriver. The boost circuit 10 is configured to control on/off of the charge/discharge node Lx and the pull-down power supply terminal V1 based on a boost control signal provided by the boost control terminal, adjust the potential of the intermediate node Vx based on the potential of the charge/discharge node Lx, control on/off of the intermediate node Vx and the output terminal Vout based on a protection control signal provided by the protection control terminal Vcontrol, and control the potentials of the charge/discharge node Lx and the output terminal Vout based on an input signal provided by the input terminal Vin and the pull-down power supply signal provided by the pull-down power supply terminal V1.

The protection circuit 00 is coupled to the intermediate node Vx, the input terminal Vin, the pull-down power supply terminal V1, and the protection control terminal Vcontrol, respectively. The protection circuit 00 is configured to transmit a protection control signal to the protection control terminal Vcontrol based on the potential of the intermediate node Vx, the input signal, and the pull-down power supply signal.

Taking the configuration of the booster circuit shown in fig. 2 and the configuration of the protection circuit shown in fig. 6 as an example, fig. 9 is taken as an example. Fig. 10 also shows a circuit schematic of a boosting device. Referring to fig. 10, it can be seen that the protection circuit 00 may be coupled to the protection control terminal Vcontrol of the boost circuit 10 through the seventh switching transistor M7 to provide the protection control terminal Vcontrol with a protection control signal related to the input signal provided by the input terminal Vin, so as to implement short-circuit protection of the boost circuit 10, and ensure better operation safety of the boost circuit 10.

Alternatively, in the embodiment of the present disclosure, the protection circuit 10 and the booster circuit 00 may be integrally provided, that is, provided on the same circuit board. Of course, in some other embodiments, the protection circuit 10 and the boost circuit 00 may be independent from each other, i.e. disposed on different circuit boards. Wherein the integrated arrangement may facilitate a volume minimization of the boost device relative to each other.

Fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 11, the electronic device includes: a load 100, and a boosting device 000 as shown in fig. 9 or 10.

As can be seen in fig. 9 and 10, in the boost device 000, an input terminal Vin of the boost circuit is coupled to the power supply terminal, and an output terminal Vout of the boost circuit is coupled to the load 100. The boost circuit is used for boosting the power signal provided by the power supply terminal to the input terminal Vout and transmitting the boosted power signal to the load 100.

Alternatively, the electronic device described in the embodiments of the present disclosure may be a display device including a display panel. By way of example, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a flexible display device, a television, a display and the like.

It is to be noted that the terminology used in the description of the embodiments of the present disclosure is for the purpose of explaining the examples of the present disclosure only and is not intended to limit the present disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed. "connected" or "coupled" refers to electrical connections.

"and/or" means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims

1. A protection circuit of a boost circuit, characterized in that the boost circuit is coupled to an input terminal (Vin), an intermediate node (Vx), a protection control terminal (Vcontrol), an output terminal (Vout) and a pull-down power supply terminal (V1), respectively; the protection circuit includes: a switch control circuit (01), a bias circuit (02) and a switch circuit (03);

the switch control circuit (01) is respectively coupled with the intermediate node (Vx), the pull-down power supply end (V1) and the control end of the switch circuit (03), and the switch control circuit (01) is used for transmitting a switch control signal to the control end of the switch circuit (03) based on the potential of the intermediate node (Vx) and the pull-down power supply signal provided by the pull-down power supply end (V1);

The bias circuit (02) is respectively coupled with the input end (Vin), the pull-down power end (V1) and the input end of the switch circuit (03), and the bias circuit (02) is used for transmitting bias signals to the input end of the switch circuit (03) based on the input signals provided by the input end (Vin) and the pull-down power signals;

the output end of the switch circuit (03) is coupled with the protection control end (Vcontrol), and the switch circuit (03) is used for transmitting a protection control signal to the protection control end (Vcontrol) based on the switch control signal received by a control end and the bias signal received by an input end so as to instruct the boost circuit to control the on-off of the intermediate node (Vx) and the output end (Vout).

2. The protection circuit according to claim 1, wherein the bias circuit (02) comprises a first bias subcircuit (021), a first switch control subcircuit (022) and a switch subcircuit (023);

the first bias sub-circuit (021) is coupled with the pull-down power supply terminal (V1) and the first switch control sub-circuit (022), respectively, the first bias sub-circuit (021) is used for receiving a first bias power supply signal and generating a first bias current for the first switch control sub-circuit (022) based on the first bias power supply signal and the pull-down power supply signal;

The first switch control sub-circuit (022) is further coupled to the input terminal (Vin) and a control terminal of the switch sub-circuit (023), respectively, the first switch control sub-circuit (022) being adapted to transmit a switch signal to the control terminal of the switch sub-circuit (023) based on the input signal and the first bias current;

the input end of the switch sub-circuit (023) is coupled with the pull-down power supply end (V1), the output end of the switch sub-circuit (023) is coupled with the input end of the switch circuit (03), and the switch sub-circuit (023) is used for transmitting a bias signal to the input end of the switch circuit (03) based on the switch signal and the pull-down power supply signal.

3. The protection circuit of claim 2, wherein the first bias subcircuit (021) comprises: a first switching transistor (M1), a second switching transistor (M2) and a first current source (I1);

the input end of the first current source (I1) is used for receiving the first bias power supply signal, and the output end of the first current source (I1) is respectively coupled with the grid electrode of the first switching transistor (M1), the first pole of the first switching transistor (M1) and the grid electrode of the second switching transistor (M2);

The gate of the first switching transistor (M1) is coupled to the gate of the second switching transistor (M2), the second pole of the first switching transistor (M1) and the second pole of the second switching transistor (M2) are both coupled to the pull-down power supply terminal (V1), and the first pole of the second switching transistor (M2) is coupled to the coupling nodes of the first switching control sub-circuit (022) and the switching sub-circuit (023).

4. The protection circuit of claim 2, wherein the first switch control sub-circuit (022) comprises: a plurality of third switching transistors (M3) connected in series;

-among said plurality of third switching transistors (M3) in series, a first pole of the third switching transistor (M3) at one end is coupled to said input terminal (Vin) and a second pole of the third switching transistor (M3) at the other end is coupled to a control terminal of said switching sub-circuit (023) and to said first biasing sub-circuit (021), respectively;

of every two third switching transistors (M3) in series, the first pole of one third switching transistor (M3) is coupled to the second pole of the other third switching transistor (M3);

and, for each third switching transistor (M3), the gate of the third switching transistor (M3) is coupled to the first pole of the third switching transistor (M3).

5. The protection circuit of claim 4, wherein the first switch control sub-circuit (022) comprises: and three third switching transistors (M3) connected in series.

6. The protection circuit of claim 2, wherein the first switch control sub-circuit (022) comprises: a first zener diode (Zd 1);

the positive pole of the first zener diode (Zd 1) is respectively coupled with the control end of the switch sub-circuit (023) and the first bias sub-circuit (021), and the negative pole of the first zener diode (Zd 1) is coupled with the input end (Vin).

7. The protection circuit according to claim 2, wherein the switching sub-circuit (023) comprises: a fourth switching transistor (M4);

the grid electrode of the fourth switching transistor (M4) is coupled with the switch control sub-circuit (021), the first electrode of the fourth switching transistor (M4) is coupled with the pull-down power supply end (V1), and the second electrode of the fourth switching transistor (M4) is coupled with the input end of the switching circuit (03).

8. The protection circuit according to claim 2, wherein the bias circuit (02) further comprises:

a first capacitance (C1) connected in series between the input terminal (Vin) and the control terminal of the switching sub-circuit (023);

A first resistor (R1) connected in series between the input of the switching sub-circuit (023) and the pull-down power supply terminal (V1);

and a unidirectional conductive diode (D1), the positive electrode of the unidirectional conductive diode (D1) is coupled with the control end of the switch sub-circuit (023) and the coupling node of the first capacitor (C1), and the negative electrode of the unidirectional conductive diode (D1) is coupled with the output end of the switch sub-circuit (023).

9. The protection circuit according to any one of claims 1 to 8, wherein the switch control circuit (01) includes: a second bias sub-circuit (011) and a second switch control sub-circuit (012);

the second bias sub-circuit (011) is coupled with the pull-down power supply terminal (V1) and the second switch control sub-circuit (012), respectively, the second bias sub-circuit (011) is configured to receive a second bias power supply signal and generate a second bias current for the second switch control sub-circuit (012) based on the second bias power supply signal and the pull-down power supply signal;

the second switch control sub-circuit (012) is further coupled to the intermediate node (Vx) and a control terminal of the switch circuit (03), respectively, the second switch control sub-circuit (012) being configured to transmit a switch control signal to the control terminal of the switch circuit (03) based on the potential of the intermediate node (Vx) and the second bias current.

10. The protection circuit of claim 9, wherein the second bias sub-circuit (011) comprises: a fifth switching transistor (M5), a sixth switching transistor (M6) and a second current source (I2);

the input end of the second current source (I2) is used for receiving the second bias power supply signal, and the output end of the second current source (I2) is respectively coupled with the grid electrode of the fifth switching transistor (M5), the first pole of the fifth switching transistor (M5) and the grid electrode of the sixth switching transistor (M6);

the gate of the fifth switching transistor (M5) is coupled to the gate of the sixth switching transistor (M6), the second pole of the fifth switching transistor (M5) and the second pole of the sixth switching transistor (M6) are both coupled to the pull-down power supply terminal (V1), and the first pole of the sixth switching transistor (M6) is coupled to the coupling node of the second switching control subcircuit (012) and the switching circuit (03).

11. The protection circuit according to claim 9, wherein the second switch control sub-circuit (012) comprises: a second zener diode (Zd 2);

the positive pole of the second zener diode (Zd 2) is respectively coupled with the control end of the switch circuit (03) and the second bias sub-circuit (011), and the negative pole of the second zener diode (Zd 2) is coupled with the intermediate node (Vx).

12. The protection circuit according to claim 9, wherein the switch control circuit (01) further comprises:

-a second capacitance (C2) connected in series between the intermediate node (Vx) and the control terminal of the switching circuit (03);

-a second resistor (R2) connected in series between the intermediate node (Vx) and the output of the switching circuit (03);

and a third capacitance (C3) connected in series between the intermediate node (Vx) and the protection control terminal (Vcontrol).

13. The protection circuit according to any one of claims 1 to 8, characterized in that the switching circuit (03) comprises: a seventh switching transistor (M7);

the gate of the seventh switching transistor (M7) is coupled to the switch control circuit (01), the first pole of the seventh switching transistor (M7) is coupled to the bias circuit (02), and the second pole of the seventh switching transistor (M7) is coupled to the protection control terminal (Vcontrol).

14. A boosting device, characterized in that the boosting device comprises: a boost circuit (10) and a protection circuit (00) according to any one of claims 1 to 13;

the boost circuit (10) is respectively coupled with an input end (Vin), an intermediate node (Vx), a protection control end (Vcontrol), an output end (Vout), a pull-down power supply end (V1), a boost control end and a charge-discharge node (Lx), and is used for controlling the on-off of the charge-discharge node (Lx) and the pull-down power supply end (V1) based on a boost control signal provided by the boost control end, regulating the potential of the intermediate node (Vx) based on the potential of the charge-discharge node (Lx), controlling the on-off of the intermediate node (Vx) and the output end (Vout) based on a protection control signal provided by the protection control end (Vcontrol), and controlling the potentials of the charge-discharge node (Lx) and the output end (Vout) based on an input signal provided by the input end (Vin) and a pull-down power supply signal provided by the pull-down power supply end (V1);

The protection circuit (00) is coupled to the intermediate node (Vx), the input terminal (Vin), the pull-down power supply terminal (V1), and the protection control terminal (Vcontrol), respectively, and is configured to transmit a protection control signal to the protection control terminal (Vcontrol) based on a potential of the intermediate node (Vx), the input signal, and the pull-down power supply signal.

15. An electronic device, the electronic device comprising: a load (100), and a boost device (000) as claimed in claim 14;

in the boosting device (000), an input end (Vin) of a boosting circuit is coupled with a power supply end, an output end (Vout) of the boosting circuit is coupled with the load (100), and the boosting circuit is used for boosting a power supply signal provided by the power supply end to the input end (Vout) and transmitting the power supply signal to the load (100).