CN116051710A - A shader architecture with texture unit and cache multiplexing - Google Patents

Abstract

The invention discloses a shader architecture in which texture units and caches are multiplexed. In the present invention, the multi-port cache internally maps the data of the entire memory space to different single-port caches according to the lower bits of the address, as shown in FIG. 3 , thereby providing multiple read interfaces. The requests of multiple ports are merged by the address merging unit, and the requests of each port are mapped to an internal single-port cache. After all the port request data are returned, the multi-port cache outputs the data. In the present invention, a unified shader architecture in which texture units and caches are multiplexed is proposed. The advantages of this architecture are: the architecture of the vertex shader and the pixel shader is consistent; no additional units are required to process different requests, which saves on-chip resources; the multi-port cache design improves the request efficiency of multiple parallel processing units.

Description

A shader architecture with texture unit and cache multiplexing

technical field

The invention belongs to the technical field of computer graphics, and specifically relates to a shader architecture for multiplexing texture units and caches.

Background technique

Shaders are used to implement image rendering, and are used to replace editable programs with fixed rendering pipelines. Among them, the VertexShader (vertex shader) is mainly responsible for the calculation of the geometric relationship of the vertex, and needs to access the vertex information; the PixelShader (pixel shader) is mainly responsible for the calculation of the source color, etc., and needs to access the texture information. Vertex data usually uses a cache to manage access, while texture information requires an additional texture unit (texture unit) to manage requests. In the usual architecture, cache and texture unit are two independent modules.

The US application published patent US202217583151A proposes a graphics processing system, including geometry processing logic, rasterization, and a shader (texture). Geometry processing logic uses cache to cache vertex data, while texture units get texture data directly from memory.

But this scheme provides a graphics processing system architecture, but only the pixel shader is programmable, the geometry stage uses a fixed pipeline, and the cache of the geometry stage is not shared with the pixel shader.

Contents of the invention

The object of the present invention is to provide a shader architecture in which texture units and caches are multiplexed in order to solve the above-mentioned problems.

The technical scheme adopted in the present invention is as follows: a shader architecture for multiplexing texture units and cache, the shader architecture for multiplexing texture units and cache includes: texture unit, shader architecture A private bus is used between the texture unit and the shader architecture connect.

In a preferred implementation manner, the operation flow of the shader architecture multiplexed by the texture unit and the cache includes the following steps:

S1: In the vertex coloring stage, request vertex data through the vertex bus;

S2: In the pixel coloring stage, texture data is requested through the texture bus.

In a preferred embodiment, in the step S1, in the vertex coloring stage, the shader directly requests vertex data through the vertex private bus request address. After the vertex request is sent to the texture unit, it is directly transparently transmitted to the cache. Cache directly returns data to the shader through the vertex private bus.

In a preferred embodiment, in the step S2, in the pixel coloring stage, the shader requests texture data by using texture coordinates and texture ids through a pixel private bus. After the texture request is sent to the texture unit, first obtain the texture information from the texture lookup table according to the texture id; then convert the request into an address according to the texture information and texture coordinates, and retrieve the data from the cache; after retrieving the data, decode according to the texture information , and finally returned to the shader through the bus.

In a preferred embodiment, the multi-port cache internally maps the data of the entire memory space into different single-port caches according to the lower bits of the address, as shown in FIG. 3 , thereby providing multiple read interfaces. The requests of multiple ports are merged by the address merging unit, and the requests of each port are mapped to an internal single-port cache. After all the port request data are returned, the multi-port cache outputs the data.

In summary, owing to adopting above-mentioned technical scheme, the beneficial effect of the present invention is:

In the present invention, a unified shader architecture in which texture units and caches are multiplexed is proposed. The advantages of this architecture are: the vertex shader and pixel shader have the same architecture; no additional units are required to process different requests, which saves on-chip resources; the multi-port cache design improves the request efficiency of multiple parallel processing units.

Description of drawings

Fig. 1 is a system frame diagram of the present invention;

Fig. 2 is a multi-port cache architecture diagram in the present invention;

FIG. 3 is a cache memory map in the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Referring to Figure 1-3,

Example:

A shader architecture multiplexing a texture unit and a cache, the shader architecture multiplexing a texture unit and a cache includes: a texture unit, shader architecture The texture unit and the shader architecture are connected by a private bus.

The operation flow of the shader architecture multiplexed by the texture unit and the cache includes the following steps:

S1: In the vertex coloring stage, request vertex data through the vertex bus;

S2: In the pixel coloring stage, texture data is requested through the texture bus.

In the step S1, in the vertex coloring stage, the shader directly requests vertex data through the vertex private bus request address. After the vertex request is sent to the texture unit, it is directly transparently transmitted to the cache. Cache directly returns data to the shader through the vertex private bus.

In the step S2, in the pixel coloring stage, the shader requests texture data through the pixel private bus using texture coordinates and texture id. After the texture request is sent to the texture unit, first obtain the texture information from the texture lookup table according to the texture id; then convert the request into an address according to the texture information and texture coordinates, and retrieve the data from the cache; after retrieving the data, decode according to the texture information , and finally returned to the shader through the bus.

The multi-port cache internally maps the data of the entire memory space into different single-port caches according to the lower bits of the address, as shown in FIG. 3 , thereby providing multiple read interfaces. The requests of multiple ports are merged by the address merging unit, and the requests of each port are mapped to an internal single-port cache. After all the port request data are returned, the multi-port cache outputs the data.

In the present invention, a unified shader architecture in which texture units and caches are multiplexed is proposed. The advantages of this architecture are: the vertex shader and pixel shader have the same architecture; no additional units are required to process different requests, which saves on-chip resources; the multi-port cache design improves the request efficiency of multiple parallel processing units.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be described in the foregoing embodiments Modifications are made to the recorded technical solutions, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (5)

1. A loader architecture for multiplexing a texture unit with a cache is characterized in that: the loader architecture for multiplexing the texture unit and the cache comprises: the texture unit and the loader architecture are connected by adopting a private bus.

2. The loader architecture for multiplexing a texture unit with cache as recited in claim 1, wherein: the operation flow of the loader architecture for multiplexing the texture unit and the cache comprises the following steps:

s1, in the vertex dyeing stage, vertex data is requested through a vertex bus;

s2, in the pixel dyeing stage, texture data is requested through a texture bus.

3. The loader architecture for multiplexing texture units with cache as recited in claim 2, wherein: in the step S1, in the vertex dyeing stage, the dyeing device requests the vertex data directly by using the address through the vertex private bus; after the vertex request is sent to the texture unit, the vertex request is directly transmitted to the cache; the Cache returns the data to the stainer directly through the vertex private bus.

4. The loader architecture for multiplexing texture units with cache as recited in claim 2, wherein: in the step S2, in the pixel dyeing stage, the stainer requests texture data by using texture coordinates and texture ids through a pixel private bus; after a texture request is sent to a texture unit, firstly, texture information is obtained from a texture lookup table according to texture id; then converting the request into an address according to texture information and texture coordinates, and retrieving data from the cache; and after retrieving the data, decoding according to the texture information, and finally returning the data to the dyeing machine through a bus.

5. The loader architecture for multiplexing texture units with cache as recited in claim 2, wherein: the data in the whole memory space is mapped into different single-port caches according to the low-order address, as shown in fig. 3, so that a plurality of read interfaces are provided; the requests of a plurality of ports are combined through an address combining unit, and the requests of each port are mapped to a single-port cache inside; after all the port request data are returned, the multi-port cache outputs the data.

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