CN116048893A

CN116048893A - Method for testing optical fiber bus interface and related equipment

Info

Publication number: CN116048893A
Application number: CN202211667167.4A
Authority: CN
Inventors: 刘瀛; 韩兵兵; 张来园; 张燕琴; 赵芸卿; 高昊; 杨与争; 张铖林; 朱方
Original assignee: Daotech Technology Co ltd
Current assignee: Daotech Technology Co ltd
Priority date: 2022-12-22
Filing date: 2022-12-22
Publication date: 2023-05-02
Anticipated expiration: 2042-12-22
Also published as: CN116048893B

Abstract

The application provides a test method of an optical fiber bus interface and related equipment. The method comprises the following steps: in response to receiving a test request for the optical fiber bus interface, uploading at least one data packet to be transmitted to a temporary memory through an upper computer; reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into a corresponding receiving interface in response to the non-empty state in the temporary memory; responding to the data writing of the data packet to be transmitted to a corresponding receiving interface, and acquiring transmission parameters; and according to the transmission parameters, completing the test of the optical fiber bus interface. In addition, because the plurality of test IP cores are arranged, the pressure test can be carried out on a large amount of data loads, and compared with the existing test method, the pressure test is more convenient.

Description

Method for testing optical fiber bus interface and related equipment

Technical Field

The present disclosure relates to the field of optical fiber communications technologies, and in particular, to a method and an apparatus for testing an optical fiber bus interface.

Background

With the continuous development of technologies such as spacecraft control systems, sensors and the like, aerospace electronic equipment increasingly tends to be highly integrated, intelligent and information comprehensive, and the transmission quantity of information on an arrow is greatly increased. The new generation rocket control system is more dependent on high bandwidth, strong real-time and open data communication at any time to perform multiparty data comprehensive processing so as to improve the control performance, and along with the development of high-speed optical fiber bus technology, a data flow test method meeting the type of optical fiber bus needs to be designed.

Conventional testing methods use one or more peer-to-peer communication nodes to simulate a command-responsive testing method for testing. The test mode has the following problems that can not be solved:

NC testing requires the deployment of a peer NT node and NT testing requires the deployment of a peer NC node. Meanwhile, long messages and short messages need to be distinguished, corresponding test nodes are selected according to matching and configuration of opposite ends, and traditional control equipment does not have the capability of configuring multi-type data stream NC or NT nodes. At present, in the field of GLink fiber testing, similar testing equipment does not exist.

Fiber optic buses are typically used for networking, while in networking testing, multiple NC or NT nodes are typically used, and it is often difficult to configure the various nodes independently for each network.

With a single command response mode, it is difficult to test the data flow traffic of the bus under a large data load.

Disclosure of Invention

In view of the foregoing, an objective of the present application is to provide a method for testing an optical fiber bus interface and related apparatus.

Based on the above purpose, the present application provides a method for testing an optical fiber bus interface, which is applied to a testing device, wherein the device comprises an upper computer, a temporary memory and a receiving interface;

the method comprises the following steps:

in response to receiving a test request for the optical fiber bus interface, uploading at least one data packet to be transmitted to a temporary memory through an upper computer; reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into a corresponding receiving interface in response to the non-empty state in the temporary memory;

responding to the data writing of the data packet to be transmitted to a corresponding receiving interface, and acquiring transmission parameters; and according to the transmission parameters, completing the test of the optical fiber bus interface.

In one possible implementation, the fiber bus interface includes: an intelligent node controller; the temporary memory includes: double rate synchronous dynamic random access memory DDR; the data packet to be transmitted comprises: long message data packet;

the uploading, by the upper computer, the at least one data packet to be transmitted to the temporary memory includes:

writing the data of the long message data packet into the DDR;

writing the obtained address and frame head of the long message data packet into a data buffer FIFO of a long message address management first-in first-out in the testing device.

In one possible implementation manner, the reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into the corresponding receiving interface in response to the non-empty state in the temporary memory includes:

reading the address of the long message data packet in the long message address management FIFO in response to the DDR being in a non-empty state;

reading the data of the data packet to be transmitted from the DDR according to the read address of the long message data packet;

and transmitting the data of the data packet to be transmitted read from the DDR to the intelligent node controller in response to the receiving FIFO of the intelligent node controller of the testing device is not full and the acquired address of the current DDR is smaller than the packet tail address of the long message data packet.

In one possible implementation, the fiber bus interface includes: an intelligent node controller; the temporary memory includes: the first intelligent node controller sends a first-in first-out data buffer FIFO in a short message; the data packet to be transmitted comprises: short message data packet;

and transmitting the short message data packet to the first intelligent node controller short message sending FIFO through an upper computer.

responding to the state that the first intelligent node controller short message sending FIFO is not empty, writing the short message data packet into a second intelligent node controller short message sending FIFO, and receiving a feedback information packet corresponding to the broken insurance data packet;

and writing the feedback information packet into a short message receiving FIFO of the intelligent node controller, and transmitting the feedback information to an upper computer through direct data storage.

In one possible implementation, the fiber bus interface includes: an intelligent node terminal; the temporary memory includes: double rate synchronous dynamic random access memory DDR and long message address management FIFO; the data packet to be transmitted comprises: long message data packet;

and responding to the intelligent node terminal receiving the long message data packet, storing data in the long message data packet into the DDR, and writing frame header information of the long message data packet into the long message address management FIFO.

reading the long message address in the long message address management FIFO when the long message address management FIFO is in a non-empty state;

and reading the long message data packet from the DDR according to the read long message address, and sending the long message data packet to the upper computer through direct data storage.

In one possible implementation, the fiber bus interface includes: an intelligent node terminal; the temporary storage includes: the intelligent node terminal sends a sub-address space in a short message; the data packet to be transmitted comprises: short message data packet;

and the upper computer transmits the short message data packet to the short message sending sub-address space of the intelligent node terminal through direct data storage.

transmitting the frame header of the short message data packet to the intelligent node terminal in response to receiving a data processing request sent by an intelligent node controller corresponding to the intelligent node terminal;

judging the transmission direction of the short message data packet according to the frame header;

and writing the short message data packet into a corresponding receiving interface according to the transmission direction.

Based on the same inventive concept, the embodiment of the application also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the method for testing the fiber bus interface according to any one of the above when executing the program.

From the above, it can be seen that, in response to receiving a test request for the optical fiber bus interface, the test method and the related device for an optical fiber bus interface provided by the present application upload at least one data packet to be transmitted to the temporary memory through the upper computer; reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into a corresponding receiving interface in response to the non-empty state in the temporary memory; responding to the data writing of the data packet to be transmitted to a corresponding receiving interface, and acquiring transmission parameters; and according to the transmission parameters, completing the test of the optical fiber bus interface. By designing a new test method, a plurality of test nodes are integrated in one test IP core, each node can flexibly select various node types, and in addition, because the plurality of test IP cores are arranged, the pressure test can be carried out on a large number of data loads, and compared with the existing test method, the pressure test is more convenient.

Drawings

In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a flow chart of a testing method of an optical fiber bus interface according to an embodiment of the present application;

fig. 2 is a schematic diagram of an IP core in a test apparatus according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a testing method according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a module B according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a smart nt short message sub-address controller according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

As described in the background section, with the continuous development of technologies such as spacecraft control systems, sensors, etc., space electronic devices increasingly tend to be highly integrated, intelligent, and information comprehensive, and the transmission amount of information on an arrow is greatly increased. The new generation rocket control system is more dependent on high bandwidth, strong real-time and open data communication at any time to perform multiparty data comprehensive processing so as to improve the control performance, and along with the development of high-speed optical fiber bus technology, a data flow test method meeting the type of optical fiber bus needs to be designed.

In view of the foregoing, embodiments of the present application provide a method for testing an optical fiber bus interface and related devices, in response to receiving a test request for the optical fiber bus interface, uploading, by an upper computer, at least one data packet to be transmitted to a temporary memory; reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into a corresponding receiving interface in response to the non-empty state in the temporary memory; responding to the data writing of the data packet to be transmitted to a corresponding receiving interface, and acquiring transmission parameters; and according to the transmission parameters, completing the test of the optical fiber bus interface. In addition, the test method of the embodiment of the application can carry out pressure test on a large number of data loads because the plurality of test IP cores are arranged, and compared with the existing test method, the pressure test method of the embodiment of the application is more convenient and effective.

The technical solutions of the embodiments of the present application are described in detail below by specific embodiments.

Referring to fig. 1, a method for testing an optical fiber bus interface according to an embodiment of the present application includes the following steps:

step S101, in response to receiving a test request for an optical fiber bus interface, uploading at least one data packet to be transmitted to a temporary memory through an upper computer; reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into a corresponding receiving interface in response to the non-empty state in the temporary memory;

step S102, responding to the data of the data packet to be transmitted and writing the data into a corresponding receiving interface, and acquiring transmission parameters; and according to the transmission parameters, completing the test of the optical fiber bus interface.

Referring to fig. 2, an IP core schematic diagram in a test apparatus according to an embodiment of the present application is shown.

As shown in fig. 2, in the IP core in the test apparatus in the embodiment of the present application, a module a for organizing and managing optical fiber nodes is described, where the module a is configured to configure various types of optical fiber GLink nodes into various different node types.

And a module B for describing how the test IP should describe the division and how to organize when testing the long message.

And a module C for describing how the test IP should describe the division and how to organize when testing the short message.

The module A, B, C, which is an integrally described IP core, may be instantiated in n shares, becoming IP 1-IPn.

The GLINK node is not a module described in the embodiment of the present application, and is used to refer to an arrow-mounted optical fiber bus node, where GLINK or GLINK refers to an arrow-mounted optical fiber bus in the embodiment.

The CPU module is not described herein and is used to describe the functionality of sending or receiving test IP processed data streams to or from a host computer via a high-speed backplane bus (e.g., PCIE bus). In this embodiment, the CPU module may include two DMA channels, where both DMA channels are data flow channels, and one of the two separate DMA channels is used when testing long messages, and the other one of the two separate DMA channels is used when testing short messages.

The interface module describes how the test IP core performs configuration description on the fiber bus interface node, and comprises the following steps: during power-on reset, testing the processing method of the IP to the external optical fiber GLINK node; testing the description of IP control and address mapping modes; test IP control register interface description.

With respect to the description of the test IP control and address mapping modes, specifically, when the external optical fiber node inputs an n-bit address bus, the IP is always mapped in units of 16-bit words, and the n-bit address bus can address the memory space of 2 nKB. Furthermore, the stack pointer and switch data field pointer used by the fiber nodes in different NC/NT modes, the test IP core always corresponds to a 16-bit address space. Therefore, when the test IP is different from the access address of the external fiber node, the necessary shift operation should be taken for the corresponding offset address.

Referring to fig. 3, a schematic structural diagram of a test method according to an embodiment of the present application is shown in reference to step S101.

Specifically, in fig. 3, the module B is the position of long packets NC, NT in the data stream communication, the asynchronous FIFO is used to calibrate the clock domain crossing of the transmission data packet, the two sending controllers and the two receiving controllers are used to adjust the format of the transmission data packet to adapt to the transmission of the data, smartNC SFIFO indicates the sending FIFO of the intelligent node controller, smartNT SFIFO indicates the sending FIFO of the intelligent node terminal, smartNC RFIFO indicates the receiving FIFO of the intelligent node controller, smartNT RFIFO indicates the receiving FIFO of the intelligent node terminal, and smart0 indicates the intelligent node, and the module B and the module C in fig. 3 correspond to the module B and the module C in fig. 2.

Referring to fig. 4, a schematic structural diagram of a module B of the present application is shown.

Module B is depicted as various functional components shown in fig. 4. Comprising the following steps:

DDR and read-write controller thereof; DDR read-write arbitration request controller; the long message address manager (address management FIFO) stores long message data including transmitted test data and received test data messages in the DDR memory, and the present embodiment describes a message format of the transmitted test data and a received test data message format.

In this embodiment, 1 to n address management registers need to be described in the long message test IP, and may be implemented by using FIFO or BRAM technology. The address management register is used for indicating a data stream data storage start address, a data stream data storage termination address and a data stream data transmission start address and a data stream data transmission termination address.

Module C in fig. 3 depicts a short message test IP core.

The short message address management module allocates and manages the space size occupied by the sub-addresses for the intelligent NT. The size of the space occupied by each sub-address can be freely distributed within a certain range. The short message address management module may allocate up to 32 sub-addresses per intelligent NT.

In a possible embodiment, 2 GLINK nodes are instantiated within a single board FPGA, each node containing 4 samrtNC+4 smart NTs. Wherein each of the smart nc and smart nt may be configured in either a long message mode or a short message mode.

Referring to fig. 5, a schematic diagram of a smart nt short message sub-address controller according to an embodiment of the present application is shown.

The address management allocation module interface axi-lite interface can dynamically set the allocation IP number of each sub-address controller. And a start address and a stop address allocated in the memory for each sub-address, the size of each sub-address being arbitrarily allocated within the memory range.

Write address request arbiter. The method comprises the steps of simultaneously comparing the sub-address IP numbers to be written with each sub-address IP number, outputting a comparison result in a single-hot code mode, and connecting a corresponding sub-address controller with a BRAM write controller according to an output arbitration result.

The Bram write controller writes fifo data entered by the axis port into the corresponding location of Bram. The write address of Bram is provided by the corresponding sub-address controller.

Read address request arbiter. The sub-address IP numbers to be read are compared with the sub-address IP numbers at the same time, the comparison result is output in a single-hot code mode, and the corresponding sub-address controller is connected with the BRAM read controller according to the output arbitration result.

The Bram read controller reads the content at the corresponding position of the Bram and outputs the content to the AXIS interface for the next stage. The read address of Bram is provided by the corresponding sub-address controller.

The sub-address controller provides the current writing address and reading address for each sub-address according to the starting address and the ending address output by the address management distribution module, and outputs the empty and full marks of the messages in the sub-address, the number of stored messages, the residual space and the like.

In a possible embodiment, when testing the smartNC interface, the software needs to be initialized first:

initializing NC big data stream configuration registers, setting typical transmission bandwidth, maximum load capacity of FC frames, exchange command stack depth initiated by big data NC, exchange transmission priority, long/short message mode, retransmission enabling and retransmission times in short message mode and the like; the stack description block is only used for state detection and fault diagnosis of the large data stream transmission process, and a large RAM space is not required to be allocated; recommending to set the bit value of a command stack depth register to be '00', corresponding to 64 exchanges, occupying 1KB of memory space; the user can enable the command stack in the debugging mode, and can select to close the command stack function in the normal working mode;

initializing a SmartNC timeout setting register;

initializing SmartNC command stack pointer (memory offset address is 0x0108/0x0109/0x010a/0x010 b);

initializing a terminal ID configuration register and setting a node ID;

initializing a function configuration register, and configuring parameters such as fiber channel enabling, ring network access function, bandwidth allocation of different priority transmission and the like;

initializing and setting a SMARTNC long message controller, and distributing corresponding DDR storage space. Initializing corresponding smartNC short message sending and receiving FIFO.

Initializing a working mode configuration register and enabling a corresponding path SmartNC.

In allocating memory space for use by the stack, it should be ensured that SmartNC stack space does not overlap with memory space allocated by control flow NC, control flow NT, and other paths SmartNC.

When testing long message data transmission, firstly, an IDLE state is entered, and after the initialization operation (such as writing CFG1, CFG2 and CFG 3) of image/video equal-size data transmission is completed, the operation jumps to a WR_DDR state.

Further, in the wr_ddr state, data is written into the DDR according to a data packet frame header transmitted to the board card by the DMA of the host computer, where the frame header of the data packet includes a long message node corresponding to the packet, a long message type, a packet of the long message, whether the packet is a long message header packet, and other contents, and writing corresponding storage address and frame header information such as length into the long message address management FIFO, and after writing a packet of the long message, clearing an empty signal fifo_empty of the corresponding long message address management FIFO. It should be noted that, the frame header of the data packet transmitted to the board card through DMA further includes corresponding identification information, the data packet is judged according to the identification information, whether the data packet is a long message or a short message is judged, the data packet is placed in a corresponding channel according to the judging result, and which IP core the data packet belongs to is judged to be managed, and finally the data packet is stored in a corresponding position.

Further, when the empty signal fifo_empty of the long message address management FIFO is zero and there is a long message sending data request, the rd_ddr state is entered, information such as an address in the FIFO is read out, and corresponding output is read out to the corresponding SMART FIFO according to the address information in the DDR. If the first packet data is the first packet data, jumping to a TRANS_RESET state; otherwise, directly jump to the SMARTNC_FIFO_WR.

Further, in the trans_reset state, an effective RESET signal smart_trans_reset of one clock cycle width is output, the smart transfer procedure is RESET, and the interface signal smart_trans_idle is waited for 1.

In the trans_trig state, a positive pulse having a width of one clock cycle is output through the smart_trans_trig signal, and the transmission process of the current frame is started.

Further, in the smart_fifo_wr state, the output of the corresponding long message address management FIFO is queried, and if the corresponding current DDR address is smaller than the tail address and the smart receive FIFO fast full signal smart_intf_tx_fifo_afull is invalid, the DDR data is read and written into the smart interface FIFO. If the smart nc transmits the idle signal smart_trans_idle valid (i.e., the transmission normally ends); or the long message address management FIFO displays the address round overflow of the long message allocation (namely, the large data receiving overflow caused by lower transmission allocation bandwidth) and jumps to the ERR_PROC state.

Further, in the err_proc state, according to the current value of rd_ping_fifo_sel, completing the read operation of the corresponding long message address management FIFO until the FIFO outputs the first packet corresponding to a frame of message; the IDLE state is skipped and the next large data transmission is started.

It should be noted that in the process of transmitting the long message information to the upper computer through DMA, a frame header of a byte needs to be added to the long message information, and the frame header can distinguish the address source of the long message information, so as to facilitate the identification and recording of the upper computer. The above steps are applicable to the following long and short messages and to different smart interfaces, and therefore will not be repeated in the following embodiments.

It should be noted that, in general, long message data is generally common data, such as video, and short message data is generally instruction data.

When transmitting short message data, the upper computer transmits a SMARTNC short message data packet to be transmitted to the SMARTNC short message transmission FIFO through DMA. The FIFO may temporarily store a plurality of smart nc short message messages.

When the SMARTNC short message sending FIFO is not empty, starting a SMARTNC short message sending state machine, carrying out transmission resetting and transmission starting on the SMARTNC, and writing a complete short message from the SMARTNC interface written in the sending FIFO; and opens the smartNC to receive the message status.

And writing the short message received by the smart NC into a smart NC short message receiving FIFO, and transmitting the short message to an upper computer through DMA. And completing one complete smartNC short message transmission.

In a possible embodiment, when testing the smart nt interface, the software needs to be initialized first:

initializing a big data NT stream configuration register and setting a long/short message working mode; in the short message mode, the ID number of the paired SmartNC and the number of the paired SmartNC also need to be initialized.

Initializing a terminal ID configuration register and setting a node ID.

Initializing a function configuration register, and configuring parameters such as fiber channel enabling, ring network access function, bandwidth allocation of different priority transmission and the like.

Initializing a SMART short message address controller, and distributing corresponding space for the needed short message sub-address. Initializing a SMART long message controller, and distributing corresponding DDR space for the SMART long message receiving long message. The corresponding smart nt short message receive FIFO is reset.

The operating mode configuration register is initialized and the corresponding path SmartNT is enabled.

When testing long message data transmission, firstly entering an IDLE state, when the long message receiving FIFO has data, analyzing a data head, adding information such as ID of the long message and the like, and jumping to a WR_DDR state;

in the WR_DDR state, reading data in a long message receiving FIFO into the DDR, writing corresponding storage addresses, frame header information such as length and the like into a long message address management FIFO, and resetting a null signal fifo_empty of the corresponding long message address management FIFO after writing one packet of long message;

in the RD_DDR state, when the empty signal fifo_empty of the long message address management FIFO is non-zero, reading out information such as addresses in the FIFO, reading out corresponding output from the DDR according to the address information into the DMA sending FIFO, and storing the data into a memory of an upper computer for data transmission. The upper computer stores the corresponding output to the corresponding position of the hard disk.

And when testing the short message data, the upper computer transmits the SMART short message data packet to be transmitted to the SMART short message transmitting sub-address space through DMA.

After the smart receives the data processing request from the NC, the data frame header is transferred to the smart receive FIFO, and the data transfer direction is determined according to the frame header.

If the transmission direction is NC to NT, continue reading the data of the interface, and transmit the data to the smart NT receive FIFO. When the smart NT reception FIFO contains at least one complete packet, the data is transferred to the host computer by DMA. Complete the complete smartNT short message receiving and transmitting once.

And if the transmission direction is NT to NC, reading out a frame of the data packet in the corresponding sub-address, and writing the data packet into a smart NT transmission interface. And simultaneously transmitting the frame header information in the smart NT receiving FIFO to the upper computer through DMA. And completing one complete smartNT short message sending transmission.

As can be seen from the above embodiments, in the method for testing an optical fiber bus interface according to the embodiments of the present application, in response to receiving a test request for an optical fiber bus interface, at least one data packet to be transmitted is uploaded to a temporary memory through an upper computer; reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted into a corresponding receiving interface in response to the non-empty state in the temporary memory; responding to the data writing of the data packet to be transmitted to a corresponding receiving interface, and acquiring transmission parameters; and according to the transmission parameters, completing the test of the optical fiber bus interface. In addition, the test method of the embodiment of the application can carry out pressure test on a large number of data loads because the plurality of test IP cores are arranged, and compared with the existing test method, the pressure test method of the embodiment of the application is more convenient and effective.

It should be noted that, the method of the embodiments of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the methods of embodiments of the present application, and the devices may interact with each other to complete the methods.

It should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Based on the same inventive concept, the application also provides an electronic device corresponding to the method of any embodiment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the method for testing the optical fiber bus interface according to any embodiment when executing the program.

Fig. 6 shows a more specific hardware architecture of an electronic device according to this embodiment, where the device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 implement communication connections therebetween within the device via a bus 1050.

The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.

The Memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 1020 may store an operating system and other application programs, and when the embodiments of the present specification are implemented in software or firmware, the associated program code is stored in memory 1020 and executed by processor 1010.

The input/output interface 1030 is used to connect with an input/output module for inputting and outputting information. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.

Communication interface 1040 is used to connect communication modules (not shown) to enable communication interactions of the present device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).

Bus 1050 includes a path for transferring information between components of the device (e.g., processor 1010, memory 1020, input/output interface 1030, and communication interface 1040).

It should be noted that although the above-described device only shows processor 1010, memory 1020, input/output interface 1030, communication interface 1040, and bus 1050, in an implementation, the device may include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.

The electronic device of the foregoing embodiment is configured to implement the testing method of the corresponding optical fiber bus interface in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and/or the like which are within the spirit and principles of the embodiments are intended to be included within the scope of the present application.

Claims

1. The test method of the fiber bus interface is applied to a test device, and the device comprises an upper computer, a temporary memory and a receiving interface;

the method comprises the following steps:

2. The method of claim 1, wherein the fiber bus interface comprises: an intelligent node controller; the temporary memory includes: double rate synchronous dynamic random access memory DDR; the data packet to be transmitted comprises: long message data packet;

writing the data of the long message data packet into the DDR;

3. The method of claim 2, wherein the reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted to the corresponding receiving interface in response to the temporary memory being in a non-empty state comprises:

4. The method of claim 1, wherein the fiber bus interface comprises: an intelligent node controller; the temporary memory includes: the first intelligent node controller sends a first-in first-out data buffer FIFO in a short message; the data packet to be transmitted comprises: short message data packet;

5. The method of claim 4, wherein the reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted to the corresponding receiving interface in response to the temporary memory being in a non-empty state comprises:

6. The method of claim 1, wherein the fiber bus interface comprises: an intelligent node terminal; the temporary memory includes: double rate synchronous dynamic random access memory DDR and long message address management FIFO; the data packet to be transmitted comprises: long message data packet;

7. The method of claim 6, wherein the reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted to the corresponding receiving interface in response to the temporary memory being in a non-empty state comprises:

8. The method of claim 1, wherein the fiber bus interface comprises: an intelligent node terminal; the temporary storage includes: the intelligent node terminal sends a sub-address space in a short message; the data packet to be transmitted comprises: short message data packet;

9. The method of claim 8, wherein the reading the data of the data packet to be transmitted in the temporary memory and writing the data of the data packet to be transmitted to the corresponding receiving interface in response to the temporary memory being in a non-empty state comprises:

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 9 when the program is executed by the processor.