CN116048887A - Chip verification method, device, system, electronic equipment and storage medium - Google Patents

Abstract

The embodiment of the invention discloses a chip verification method, device, system, electronic equipment, and storage medium, which relate to the technical field of electronic design automation and can facilitate defect detection while giving full play to the large-scale and fast verification advantages of a hardware verification platform. The method is based on a hardware verification platform, including: running a hardware simulation program of the chip to be verified; sending behavior information and behavior result information of the chip to be verified during program operation to the software verification platform according to a preset strategy, so that the The software verification platform performs a verification review on the chip to be verified according to the behavior information and the behavior result information. The invention is applicable to various chip verifications.

Description

A chip verification method and device, system, electronic equipment, storage medium

technical field

The invention relates to the field of computers, in particular to a chip verification method and device, system, electronic equipment, and storage medium.

Background technique

With the development and scale of integrated circuits, verification has gradually become one of the biggest challenges in SOC (System on Chip, System on Chip) development.

The traditional software verification method (simulation) can cover the verification of the chip module level very comprehensively, and the controllability is also very high. However, as the complexity of the chip increases, the time spent using software simulation tools to simulate the overall chip operation will increase accordingly, and the time to find corner case bugs will increase exponentially.

In order to solve this verification problem, there is a hardware emulation (emulation) technology, that is, to speed up the verification speed through a hardware accelerator (emulator), FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), etc. Specifically, emulation can transplant the circuit design to be verified on the hardware accelerator and develop a verification platform, so as to achieve a simulation speed of several kilohertz to several megahertz, which is up to 100,000 times faster than traditional software simulation tools.

The introduction of the Emulator solves the problems of slow test speed and small scale of test instructions when the chip is tested on a large scale before tape-out. However, compared with traditional verification simulation, many detection methods in hardware simulation, such as checker (checkpoint), monitor ( monitor) etc. cannot be synthesized into a specific circuit, therefore, there are few error detection methods available in hardware simulation, and it is difficult to find some design defects of the chip to be verified.

Contents of the invention

In view of this, embodiments of the present invention provide a chip verification method and device, system, electronic equipment, and computer-readable storage medium, which can facilitate defect detection while giving full play to the advantages of large-scale and fast verification of a hardware verification platform.

In the first aspect, embodiments of the present invention provide a chip verification method based on a hardware verification platform, including: running a hardware simulation program of the chip to be verified; The behavior information and behavior result information in, so that the software verification platform performs verification review on the chip to be verified according to the behavior information and the behavior result information.

In one embodiment, the sending the behavior information and behavior result information of the chip to be verified to the software verification platform during program execution according to a preset policy includes: the execution of each instruction in the hardware emulation program ends Afterwards, the behavior information and behavior result information of the chip to be verified during program running are sent to the software verification platform.

In an implementation manner, the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information.

In one embodiment, the memory access information of the instruction includes at least one of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, memory access information lost due to an abnormal situation , Memory information updated due to speculative execution of instructions.

In one embodiment, the actual execution order of the instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order corresponds to the actual execution order of the instructions in the hardware emulation program the actual memory access sequence; the sending to the software verification platform the behavior information and behavior result information of the chip to be verified during the program operation includes: the actual memory access sequence corresponding to the actual execution sequence of the instruction, and the instruction Sequence adjustment information is sent to the software verification platform; or, according to the actual execution order of the instructions and the order adjustment information of the instructions, the specified execution sequence of the instructions is determined, and the specified memory access sequence corresponding to the specified execution sequence is sent to the The software verification platform sends.

In one embodiment, the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the clock frequency of the first processor core is the same as the clock frequency of the The clock frequency of the second processor core is different; the access sequence of the at least two processor cores to the memory is an access sequence based on the respective clocks of the processor cores; the sending of the chip to be verified to the software verification platform is in the process of program operation The behavior information and behavior result information include: sending the access sequence based on the respective clocks of the processor cores and the clock difference of each processor core to the software verification platform, or, according to the clock difference of each processor core, Synchronize based on the access sequence of the respective clocks of the processor cores to obtain a synchronization sequence, and send the synchronization sequence to the software verification platform.

In one embodiment, before sending the behavior information and behavior result information of the chip to be verified to the software verification platform according to the preset strategy, the method further includes: determining the behavior information and the Whether the instruction corresponding to the behavior result information is a predictively executed instruction; in response to the fact that the instruction is a predictively executed instruction, determine whether the prediction of the predictively executed instruction is successful; according to the preset strategy, send the described The behavior information and behavior result information of the chip to be verified during program operation include: if the prediction is successful, send the behavior information and the behavior result information to the software verification platform; The platform sends the behavior information and the behavior result information.

In one embodiment, the behavior result information includes at least one of the following: fixed-point register information after the instruction exits, floating-point register information after the instruction exits, and status register information after the instruction exits.

In one embodiment, after running the hardware simulation program of the chip to be verified, before sending the behavior information and behavior result information of the chip to be verified to the software verification platform according to the preset policy, the The method further includes: when executing each instruction in the hardware emulation program, obtaining the behavior information of the instruction; after executing each instruction in the hardware emulation program, obtaining the behavior result information corresponding to the instruction ; According to a preset protocol, generating a verification data packet from the behavior information and the behavior result information; the sending the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform includes: sending the behavior information to the software verification platform; The software verification platform sends the verification data packet.

In one embodiment, the sending to the software verification platform the behavior information and behavior result information of the chip to be verified during program operation includes: sending the software verification platform through DPI (Direct Programming Interface, direct programming interface) Behavior information and behavior result information of the chip to be verified during program operation.

In the second aspect, the embodiment of the present invention also provides a chip verification method based on a software verification platform, including: receiving behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform; Running the reference model corresponding to the chip to be verified according to the behavior information to obtain corresponding model result information; performing verification review on the chip to be verified according to the behavior result information and the model result information.

In one embodiment, the receiving the behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform includes: receiving the verification data packet sent by the hardware verification platform, the verification data The packet is generated from the behavior information and the behavior result information according to a preset protocol; the verification data packet is parsed to obtain the behavior information and the behavior result information.

In one embodiment, the running the reference model corresponding to the chip to be verified according to the behavior information includes: restoring the behavior information to the behavior sequence of the chip to be verified through a preset script; using the behavior Sequences drive the reference model to run.

In one embodiment, the verification review of the chip to be verified according to the behavior result information and the model result information includes: comparing the behavior result information with the model result information; The comparison result determines whether the chip to be verified passes the verification.

In one embodiment, the comparison result is that the verification of the chip to be verified fails, and the method further includes: performing defect inspection on the chip to be verified according to the comparison result.

In an implementation manner, the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information.

In one embodiment, the memory access information of the instruction includes at least one of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, memory access information lost due to an abnormal situation . The memory information updated due to the predictive execution of instructions; before performing verification review on the chip to be verified according to the behavior result information and the model result information, the method further includes: according to the memory access information Detecting whether the chip to be verified has a cache coherency defect and/or a memory coherency defect.

In one embodiment, the actual execution order of the instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order corresponds to the actual execution order of the instructions in the hardware emulation program the actual memory access sequence; the detecting whether the chip to be verified has a cache coherency defect and/or a memory consistency defect according to the memory access information includes: according to the instruction received in advance from the hardware verification platform According to the actual execution order of the instruction and the order adjustment information of the instruction, determine the specified execution sequence of the instruction; according to the specified memory access sequence corresponding to the specified execution sequence of the instruction, detect whether the chip to be verified has a cache coherency defect and/or or a memory consistency bug.

In one embodiment, the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the clock frequency of the first processor core is the same as the clock frequency of the The clock frequency of the second processor core is different; the access order of the at least two processor cores to the memory is based on the access order of the respective clocks of the processor cores; and according to the memory access information, it is detected whether the chip to be verified is The existence of cache coherency defects and/or memory consistency defects includes: according to the clock differences of the processor cores, synchronizing the access orders based on the respective clocks of the processor cores to obtain a synchronization order; according to the synchronization order, detecting all Describe whether the chip to be verified has cache coherency defects and/or memory coherency defects.

In the third aspect, the embodiment of the present invention also provides a chip verification device, including: a first operating unit, configured to run a hardware simulation program of the chip to be verified; a sending unit, according to a preset policy, to send the Behavior information and behavior result information of the chip to be verified during program operation, so that the software verification platform performs verification review on the chip to be verified according to the behavior information and the behavior result information.

In one embodiment, the sending unit is specifically configured to send the behavior information and Behavior Outcome Information.

In an implementation manner, the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information.

In one embodiment, the memory access information of the instruction includes at least one of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, memory access information lost due to an abnormal situation , Memory information updated due to speculative execution of instructions.

In one embodiment, the actual execution order of the instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order corresponds to the actual execution order of the instructions in the hardware emulation program the actual memory access sequence; the sending unit is specifically configured to: send the actual memory access sequence corresponding to the actual execution sequence of the instruction and the order adjustment information of the instruction to the software verification platform; or, according to the The actual execution sequence of the instructions and the sequence adjustment information of the instructions determine the specified execution sequence of the instructions, and send the specified memory access sequence corresponding to the specified execution sequence to the software verification platform.

In one embodiment, the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the clock frequency of the first processor core is the same as the clock frequency of the The clock frequency of the second processor core is different; the access order of the at least two processor cores to the memory is an access order based on the respective clocks of the processor cores; the sending unit is specifically used to: The access sequence of the respective clocks and the clock difference of each processor core are sent to the software verification platform, or, according to the clock difference of each processor core, the access sequence based on the respective clocks of the processor cores is synchronized to obtain the synchronization sequence , sending the synchronization sequence to the software verification platform.

In one embodiment, the device further includes: a first determination unit, configured to determine the behavior information and behavior result information of the chip to be verified during program execution before sending the behavior information and behavior result information of the chip to be verified to the software verification platform according to a preset policy. Whether the instruction corresponding to the behavior information and the behavior result information is a predictively executed instruction; a second determining unit is configured to determine whether the predictively executed instruction is predicted to be successful in response to the instruction being a predictively executed instruction; The sending unit is specifically used to: send the behavior information and the behavior result information to the software verification platform if the prediction is successful; refuse to send the behavior information and the behavior result information to the software verification platform if the prediction fails Information about the outcome of the behavior described above.

In one embodiment, the behavior result information includes at least one of the following: fixed-point register information after the instruction exits, floating-point register information after the instruction exits, and status register information after the instruction exits.

In one embodiment, the device further includes: a first acquiring unit, configured to send the hardware simulation program of the chip to be verified to the software verification platform according to a preset strategy after running the hardware simulation program of the chip to be verified. Before the behavior information and behavior result information in operation, when executing each instruction in the hardware emulation program, obtain the behavior information of the instruction; the second acquisition unit, when executing each instruction in the hardware emulation program Afterwards, the behavior result information corresponding to the instruction is obtained; the generation unit is used to generate a verification data packet from the behavior information and the behavior result information according to a preset protocol; the sending unit is specifically used to send the software The verification platform sends the verification data packet.

In one embodiment, the sending unit is specifically configured to send behavior information and behavior result information of the chip to be verified during program execution to the software verification platform through DPI.

In the fourth aspect, the embodiment of the present invention further provides a chip verification device, including: a receiving unit, configured to receive behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform; The second operating unit is configured to run the reference model corresponding to the chip to be verified according to the behavior information to obtain corresponding model result information; the review unit is configured to process the pending chip according to the behavior result information and the model result information Verify the chip for verification review.

In one embodiment, the receiving unit includes: a receiving module, configured to receive a verification data packet sent by a hardware verification platform, where the verification data packet is generated from the behavior information and the behavior result information according to a preset protocol; An analysis module, configured to analyze the verification data packet to obtain the behavior information and the behavior result information.

In one embodiment, the second operating unit includes: a restore module, configured to restore the behavior information to the behavior sequence of the chip to be verified through a preset script; a driver module, configured to use the behavior sequence Drive the reference model to run.

In one embodiment, the review unit includes: a comparison module, configured to compare the behavior result information with the model result information; a determination module, configured to determine the chip to be verified according to the comparison result Whether the verification is passed.

In one embodiment, the comparison result is that the verification of the chip to be verified fails; the device further includes: a troubleshooting unit, configured to perform defect troubleshooting on the chip to be verified according to the comparison result.

In an implementation manner, the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information.

In one embodiment, the memory access information of the instruction includes at least one of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, memory access information lost due to an abnormal situation . The memory information updated due to the predictive execution of the instruction; the device further includes: a detection unit, used to check the chip to be verified according to the The memory access information is used to detect whether the chip to be verified has a cache coherency defect and/or a memory consistency defect.

In one embodiment, the actual execution order of the instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order corresponds to the actual execution order of the instructions in the hardware emulation program The actual memory access sequence; the detection unit includes: a sequence determination module, which is used to determine the specified execution of the instruction according to the actual execution sequence of the instruction and the order adjustment information received from the hardware verification platform in advance Sequence; the first detection module is configured to detect whether the chip to be verified has a cache coherency defect and/or a memory consistency defect according to the specified memory access sequence corresponding to the specified execution sequence of the instructions.

In one embodiment, the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the clock frequency of the first processor core is the same as the clock frequency of the The clock frequency of the second processor core is different; the access order of the at least two processor cores to the memory is based on the access order of the respective clocks of the processor cores; the detection unit includes: a clock synchronization module, for according to each processor The clock difference of the core is to synchronize the access sequence based on the respective clocks of the processor cores to obtain a synchronization sequence; the second detection module is used to detect whether there is a cache consistency defect and a cache consistency defect in the chip to be verified according to the synchronization sequence. /or memory consistency flaws.

In the fifth aspect, the embodiments of the present invention also provide a chip verification system, including a hardware verification platform and a software verification platform; the hardware verification platform communicates with the software verification platform through a preset interface; wherein, the hardware verification platform The platform is used to execute any chip verification method based on the hardware verification platform provided by the embodiments of the present invention, and the software verification platform is used to execute any chip verification method based on the software verification platform provided by the embodiments of the present invention.

In the sixth aspect, the embodiment of the present invention also provides an electronic device, including: a casing, at least one processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the casing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to each circuit or device of the above-mentioned electronic equipment; the memory is used to store the executable program code; the at least one processor reads the executable program code stored in the memory to run a program corresponding to the executable program code, for executing any chip verification method provided by the embodiments of the present invention.

In the seventh aspect, the embodiments of the present invention also provide a computer-readable storage medium, the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors , so as to implement any chip verification method provided by the embodiments of the present invention.

The chip verification method and device, system, electronic equipment, and computer-readable storage medium provided by the embodiments of the present invention can combine a hardware verification platform with a software verification platform. On the one hand, the simulation of the chip to be verified can be run on the hardware verification platform. program, so as to realize large-scale and rapid verification of the chip to be verified. On the other hand, the behavior information and behavior result information of the chip to be verified in the hardware verification can be sent to the software verification platform, so that the software verification platform can perform software verification of the same behavior of the chip to be verified. In this way, the various and perfect defect detection methods in the software verification method can be used to check the defects in the chips to be verified. Therefore, it is possible to facilitate defect detection while giving full play to the large-scale and rapid verification advantages of the hardware verification platform.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a flow chart of a chip verification method provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a processor core and memory in an embodiment of the present invention;

Fig. 3 is another flow chart of the chip verification method provided by the embodiment of the present invention;

FIG. 4 is a detailed flowchart of a chip verification method provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a chip verification device provided by an embodiment of the present invention;

FIG. 6 is another schematic structural diagram of a chip verification device provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a chip verification system provided by an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention.

Detailed ways

Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

In order to enable those skilled in the art to better understand the technical conception, implementation and beneficial technical effects of the embodiments of the present invention, the following specific examples will be described in detail.

As mentioned in the background technology, although the hardware emulation technology solves the problems of slow test speed and small scale of test instructions when the chip is tested on a large scale before tape-out, compared with the traditional software simulation verification (simulation), the hardware Many detection methods in simulation, such as checker, monitor, etc., cannot be synthesized into specific circuits. Therefore, there are few defect detection methods available in hardware simulation, and it is difficult to find some design defects of the chip to be verified.

In order to make up for the above deficiencies, when using the hardware simulation acceleration platform for large-scale CPU testing, CPU verification engineers can add some self-checking test cases when generating test CPU direct/random test cases, such as CRC (Cyclic Redundancy Check, Cyclic redundancy check) comparison, running the same program multiple times to see if the results are consistent, adding "pass" (pass), "failed" (failed) program segment characterization tests are executed according to the design of the verification engineer, etc. However, although this solves the problem of error detection to a certain extent, it is difficult to grasp the verification granularity when writing self-verification test cases. If the verification granularity is coarse, some errors of the chip to be verified may be covered up. It cannot be verified. If the granularity is finer, the test case is likely to be terminated due to various subtle problems, resulting in the inability to run to completion, and thus unable to play a verification role.

In addition, with the gradual popularity of UVM (Universal Verification Methodology, Universal Verification Methodology), there is also a solution to build host UVM on the hardware emulator emulator, that is, run the emulation program of the chip to be verified on the hardware emulator, and Communicate at the transaction level with the host UVN. In this way, the hardware simulation can reuse the checker and monitor developed by the host UVM software verification platform simulation, so as to achieve the purpose of verification. However, the emulation program of the software verification platform and the emulation program of the hardware verification platform run simultaneously, and the two emulation programs maintain transaction-level communication, so that the running speed of the hardware emulation is limited by the emulation speed of the software emulation.

In addition, engineers can also let the hardware emulation accelerator report whether there is an assertion trigger (assertion trigger) that meets the conditions during operation. However, this approach is similar to white-box testing, which requires verification engineers to judge in advance the possible conditions of the problematic test points. However, since the extreme defects of the CPU are often verified through random instruction sequences, it is difficult for verification engineers to judge in advance and add corresponding assertions.

In order to make full use of the large-scale and fast verification advantages of the hardware verification platform and facilitate defect detection, the inventor found in the research that the hardware verification platform can be combined with the software verification platform. Verify the simulation program of the chip, so as to realize the large-scale and fast verification of the chip to be verified. On the other hand, the behavior information and behavior result information of the chip to be verified in the hardware verification can be sent to the software verification platform, so that the software verification platform can also verify the chip to be verified. Behaviors are verified in software, so that various and complete defect detection methods in software verification methods can be used to troubleshoot defects in chips to be verified.

In order to enable those skilled in the art to better understand the technical concepts, implementations and beneficial effects of the embodiments of the present invention, specific examples are described below in detail.

In the first aspect, the embodiments of the present invention provide a method for chip verification, which can facilitate defect detection while giving full play to the large-scale and fast verification advantages of a hardware verification platform.

As shown in Figure 1, the chip verification method provided by the embodiment of the present invention is based on a hardware verification platform, and the method may include:

S11, running a hardware emulation program of the chip to be verified;

In the embodiment of the present invention, the hardware verification platform may be a platform that uses hardware circuits or hardware devices to simulate circuits or functional modules in the chip to be verified. The chip to be verified is on the hardware verification platform, specifically, it may refer to the chip to be verified simulated on the hardware verification platform. In this step, run the hardware simulation program of the chip to be verified, that is, use the hardware verification platform to simulate various structures and functions of the chip to be verified, and run various test cases on the simulated chip to be verified. Since the hardware verification platform has a higher operating speed than the software verification platform, large-scale test cases can be quickly run on the hardware verification platform to efficiently verify all aspects of the chip to be verified.

Optionally, in the embodiment of the present invention, the chip to be verified may include various functions and various types of integrated circuits, for example, various application-specific integrated circuits, processors, and the like.

S12. According to the preset strategy, send the behavior information and behavior result information of the chip to be verified during the program operation to the software verification platform, so that the software verification platform can make the The chip to be verified is verified and reviewed.

In the embodiment of the present invention, after the hardware verification platform runs the hardware simulation program, on the one hand, the corresponding hardware verification results can be obtained; on the other hand, the behavior information and behavior result information of the chip to be verified in the hardware simulation program can be sent to the software verification platform Send to enable the software verification platform to perform a verification review. A software verification platform may refer to a verification platform running on a host. The software verification platform can be realized based on multiple programming languages. For example, in one embodiment of the present invention, the software verification platform can be realized based on C language.

The preset strategy may include the timing of sending behavior information and behavior result information to the software verification platform, and may also include the information structure and organizational form of the behavior information and behavior result information. Wherein, the behavior information may refer to which or what kind of operations are performed during the running of the program, and the behavior result information may refer to what results or effects are produced by these operations.

In the embodiment of the present invention, the timing of sending behavior information and behavior result information can be various, both can be sent multiple times in batches during the running of the hardware emulation program, or can be sent collectively after the hardware emulation program is running, so as to The software verification platform can perform verification review on the chip to be verified according to the behavior information and the behavior result information. Optionally, in an embodiment of the present invention, the verification review can be offline, that is, the hardware verification platform can continue to perform subsequent simulation verification operations without waiting for the verification review result of the software verification platform, thereby further improving verification. efficiency. In another embodiment of the present invention, the verification review can also be online, that is, the hardware verification platform can wait for the verification review result of the software verification platform, and determine whether to continue the subsequent hardware simulation verification operation according to the verification review result. In this way, although some verification speed will be sacrificed in the process of waiting for the software verification platform, since the software verification platform in the embodiment of the present invention is not a complex verification system based on traditional UVM, it is aimed at the corresponding behavior information and The behavior result information is verified and reviewed, and the structure and procedures are more streamlined. Therefore, the software verification speed is still greatly improved compared with the traditional UVM, so that while improving the verification efficiency, problems of the chip to be verified can be found in time without the need for follow-up Then, a large number of verifications are performed, which effectively saves verification resources.

Optionally, the information structure and organization form of behavior information and behavior result information can also be various. That is to obtain and count which operations and results are involved in the execution of each instruction, and send the behavior information and behavior result information corresponding to each instruction to the software verification platform. In another embodiment of the present invention, the behavior information and behavior result information may also be acquired and counted in units of clock cycles, that is, the behavior information and behavior result information are acquired and counted once in each clock cycle. In a specific implementation, the behavior information and the behavior result information may be stored in the same file or in different files, which is not limited in this embodiment of the present invention.

In the chip verification method provided by the embodiments of the present invention, the hardware verification platform can run the hardware simulation program of the chip to be verified, and send the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform according to the preset strategy so that the software verification platform performs a verification review on the chip to be verified according to the behavior information and the behavior result information. In this way, the hardware verification platform can be combined with the software verification platform. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby realizing large-scale and fast verification of the chip to be verified. The behavior information and behavior result information of the chip to be verified are sent to the software verification platform, so that the software verification platform can verify the same behavior of the chip to be verified in software, so that the various and perfect defect detection methods in the software verification method can be used to troubleshoot the pending defects. To verify the defects in the chip, it is possible to make full use of the large-scale and rapid verification advantages of the hardware verification platform, and at the same time facilitate defect detection.

Specifically, in an embodiment of the present invention, the behavior information of the chip to be verified during program execution may include one or more of the following: instruction exit information, instruction memory access information, and instruction interruption information. Wherein, the exit information of the instruction may indicate that the execution of an instruction is completed, and the memory access information of the instruction may indicate that an instruction has a memory access operation, such as reading memory or writing memory, etc., wherein the memory may include memory and/or various levels of cache. Exemplarily, a structural diagram of a processor core and a memory of a chip to be verified may be shown in FIG. 2 . The interrupt information of an instruction may indicate that the execution of an instruction has generated an interrupt. These behavioral information can be obtained by reading the corresponding logic unit in the hardware emulation chip to be verified. For example, actual memory access behavior information during instruction execution can be extracted from the LSU (memory read/write unit), or interrupt information can be obtained from the interrupt processing unit.

Among the various behavior information of the instruction, the memory access information of the instruction involves the interaction between the processor and the memory. Based on this, in one embodiment of the present invention, when verifying the chip to be verified, the memory access information of the instruction can be used to Verify whether the chips to be verified have memory coherency defects and/or cache coherency defects.

Specifically, in an embodiment of the present invention, the memory access information of the instruction may include one or more of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, The memory access information lost due to the situation, and the memory information updated due to the speculative execution of the instruction. All these factors may affect the memory access of the processor core of the chip to be verified in the hardware verification platform. In order for the software verification platform to verify and review the chip to be verified according to the behavior information and behavior result information sent by the hardware verification platform, in the embodiment of the present invention, the above memory access information can be used to accurately restore the relationship between each processor core and memory. The interactive process, so that the software verification platform can simulate the interactive process, so as to verify the memory consistency and/or cache consistency of the chips to be verified.

Further, with the development of computer technology, when executing instructions, the processor can not only execute the instructions in the original prescribed order, but also disrupt the prescribed order of the instructions to perform out-of-order execution and/or predictive execution. Correspondingly, in out-of-order execution and/or speculative execution, the interaction between the processor and the memory during the execution of each instruction is also involved. In this case, in order to enable the software verification platform to verify and review the memory consistency and/or cache consistency of the chip to be verified, in the embodiment of the present invention, the hardware verification platform and/or software verification platform can combine out-of-order execution and /or the predicted execution order is restored to the original specified execution sequence of the instruction, and then the software verification platform conducts verification review according to the restored specified execution sequence. In order to make each instruction correspond to its own memory access information, the memory access information is also adjusted along with the adjustment of the execution order of the instructions.

For example, in one embodiment of the present invention, the actual execution order of instructions in the hardware simulation program of the chip to be verified may include out-of-order execution and/or speculative execution; the access order of the memory by the at least one processor core is specifically is the actual memory access sequence corresponding to the actual execution sequence of the instructions in the hardware emulation program; based on this, in step S12, sending the behavior information and behavior result information of the chip to be verified to the software verification platform during program operation may specifically include : Send the actual memory access sequence corresponding to the actual execution sequence of the instructions, and the order adjustment information of the instructions to the software verification platform, so that the software verification platform determines the regulations of the instructions according to the actual memory access order and order adjustment information Executing the specified memory access sequence corresponding to the sequence, and performing a verification review on the memory consistency and/or cache consistency of the chip to be verified based on the specified memory access sequence.

Optionally, in another embodiment of the present invention, the hardware verification platform may also determine the specified execution sequence of the instructions according to the actual execution sequence of the instructions and the sequence adjustment information of the instructions, and convert the specified execution sequence to The corresponding specified memory access sequence is sent to the software verification platform, so that the software verification platform performs verification review on the memory consistency and/or cache consistency of the chip to be verified based on the specified memory access sequence.

In the embodiment of the present invention, in addition to the out-of-order execution and/or speculative execution of instructions will affect the verification review of the software verification platform, in a multi-core processor, if the clock frequencies of the cores of each processor are different, the software verification platform will also be affected. validation review for , and therefore require special handling.

For example, in one embodiment of the present invention, the number of processor cores of the chip to be verified is at least two, and there are at least one first processor core and one second processor core, the first processing The clock frequency of the processor core is different from the clock frequency of the second processor core; the access order of the at least two processor cores to the memory is based on the access order of the respective clocks of the processor cores; then based on this, in step S12 to The software verification platform sending the behavior information and behavior result information of the chip to be verified during program operation may include: sending the access sequence based on the respective clocks of the processor cores and the clock difference of each processor core to the software verification platform, so that the software The verification platform synchronizes the access sequence based on the respective clocks of the processor cores according to the clock difference of each processor core, and verifies memory consistency and/or cache consistency according to the synchronized access sequence.

Optionally, in another embodiment of the present invention, the hardware verification platform may also synchronize the access sequence based on the respective clocks of the processor cores according to the clock differences of the processor cores to obtain the synchronization sequence, and store the obtained The synchronization sequence is sent to the software verification platform.

The execution of the instruction will produce a certain result, and the corresponding behavior result information can be obtained. The behavior result information can be stored in various registers of the chip to be verified by hardware emulation and obtained and accessed. For example, in one embodiment of the present invention, the behavior result information of the chip to be verified during program execution may include one or more of the following: fixed-point register information after the instruction exits, floating-point register information after the instruction exits, instruction exit After the status register information and so on. When acquiring behavior result information, for example, fixed-point information of retire (exit) can be extracted from RT (complete exit unit), floating-point information can be extracted from FP (floating-point unit), and the like.

In order to obtain the above behavior information and behavior result information of the chip to be verified, in one embodiment of the present invention, a synthesizable monitor can be implemented based on systemverilog, which is used to collect the behavior information and behavior of the chip to be verified on the hardware verification platform result information.

After obtaining the behavior information and behavior result information of the chip to be verified during program operation, the behavior information and behavior result information of the chip to be verified during program operation can be sent to the software verification platform according to the preset strategy in step S12 . Specifically, in one embodiment of the present invention, according to a preset policy, sending the behavior information and behavior result information of the chip to be verified to the software verification platform during program execution may specifically include: After each instruction finishes running, send the behavior information and behavior result information of the chip to be verified during program running to the software verification platform. For example, after each CPU instruction finishes running, the behavior information and The behavior result information is transmitted to the software verification platform through the monitor. In this way, by acquiring and sending information on the operation and results of each instruction at the granularity of the instruction, the action and result of each instruction can be accurately grasped, and neither too much acquisition nor sending, and the intermediate process of instruction execution Information and redundant information will not omit important behavioral information and behavioral result information.

In order to improve the efficiency of information transmission, in one embodiment of the present invention, after the hardware simulation program of the chip to be verified is run in step S11, step S12 sends the information of the chip to be verified to the software verification platform according to the preset strategy when the program is running. Before the behavior information and behavior result information, the chip verification method provided by the embodiments of the present invention may also include: when executing each instruction in the hardware emulation program, obtaining the behavior information of the instruction; After each instruction in the program, the behavior result information corresponding to the instruction is obtained; according to the preset protocol, the behavior information and the behavior result information are generated into a verification data packet; based on this, step S12 sends to the software verification platform The behavior information and behavior result information of the chip to be verified during program running may specifically include: sending the verification data packet to the software verification platform.

In this embodiment, since various logic units and registers storing behavior information and behavior result information will be updated with the execution of the program, in order to obtain the behavior information and behavior result information of each instruction, an appropriate timing can be selected To obtain behavioral information and behavioral result information. For example, in this embodiment, it is selected to obtain corresponding behavior information when each instruction is executed, and obtain corresponding behavior result information after each instruction is executed.

Considering the convenience of information transmission, in this embodiment, data encapsulation is also performed on the acquired behavior information and behavior result information, and the behavior information and behavior result information are generated into verification data packets according to the pre-agreed agreement with the software verification platform , and send a verification packet to the software verification platform. Optionally, these verification data packets can be sent after each instruction is finished, or can be sent in batches after several instructions are finished, or can be sent when the hardware verification platform is idle, or can be sent in the hardware emulation program of the hardware verification platform It is sent after the operation is completed, which is not limited in this embodiment of the present invention. Optionally, the behavior information and behavior result information may be encapsulated in the same verification data packet, or encapsulated in different verification data packets.

In a specific implementation, the behavior information and behavior result information of the chip to be verified during program running can be sent to the software verification platform through DPI or other available interfaces.

In addition, in one or more embodiments of the present invention, there may be speculative execution of instructions, but the behavior information and behavior result information corresponding to speculative execution cannot take effect immediately, and this predictive instruction must be determined according to the execution status of the preceding instruction Whether the execution is correct, that is, whether the prediction is successful. If the prediction is successful, the corresponding behavior information and behavior result information are valid and can be sent to the software verification platform. Otherwise, if the prediction fails, the corresponding behavior information of the prediction instruction Behavior information and behavior result information are both invalid, therefore, refuse to send to the software verification platform, and the prediction instruction must be re-executed.

For example, in one embodiment of the present invention, before step S12 sends the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform according to the preset policy, the embodiment of the present invention provides The chip verification method may further include: determining whether the instruction corresponding to the behavior information and the behavior result information is a speculatively executed instruction; in response to the fact that the instruction is a speculatively executed instruction, determining whether the prediction of the speculatively executed instruction is successful ; Based on this, step S12 sends the behavior information and behavior result information of the chip to be verified to the software verification platform according to the preset strategy during program operation. Specifically, it may include: in the case of successful prediction, sending the software verification platform. Behavior information and the behavior result information; when the prediction fails, refuse to send the behavior information and the behavior result information to the software verification platform.

Correspondingly, the embodiment of the present invention also provides a chip verification method based on a software verification platform, which can facilitate defect detection while giving full play to the large-scale and rapid verification advantages of the hardware verification platform.

As shown in Figure 3, the chip verification method provided by the embodiment of the present invention is based on a software verification platform, and the method may include:

S21. Receive behavior information and behavior result information of the chips to be verified running on the hardware verification platform sent by the hardware verification platform;

In the embodiment of the present invention, the software verification platform may refer to a verification platform running on a host. The hardware verification platform may be a platform that uses hardware circuits or hardware devices to simulate circuits or functional modules in the chip to be verified.

The software verification platform can receive the behavior information and behavior result information sent by the hardware verification platform, and the chips to be verified during the hardware verification, and store the behavior information and behavior result information as files, so that the software can be run on the software verification platform. Validation review process. Optionally, the behavior information and behavior result information can be stored in the same file or in different files.

Since the hardware verification platform has a higher operating speed than the software verification platform, large-scale test cases can be quickly run on the hardware verification platform to efficiently verify all aspects of the chip to be verified. But because there are relatively few related means for locating, searching and analyzing defects in the hardware verification platform, in this step, the software test platform can receive the information sent by the hardware verification platform and the chips to be verified run on the hardware verification platform. Behavior information and behavior result information, so as to trigger the software verification platform to verify and review the relevant behaviors and behavior results on the hardware verification platform. Wherein, the behavior information may refer to which or what kind of operations are specifically performed during the running of the hardware simulation program on the side of the hardware verification platform, and the behavior result information may refer to what results or effects are produced by these operations.

S22. Run the reference model corresponding to the chip to be verified according to the behavior information to obtain corresponding model result information;

After receiving the behavior information from the hardware verification platform, in this step, the software verification platform can run a preset reference model corresponding to the chip to be verified according to the behavior information, and calculate the behavior information based on the reference model Corresponding model result information. That is to say, in this step, software simulation can be used to calculate what result the behavior information will produce, and to obtain model result information.

Wherein, the reference model may refer to using software to simulate various logics and functions of the chip to be verified, so as to verify the correctness of the chip to be verified. Since various defect detection methods can be flexibly set in the software verification method, for example, detection methods such as checker and monitor in UVM can be set in the software verification method, so it can effectively make up for the deficiency of the hardware verification platform.

S23. Perform verification review on the chip to be verified according to the behavior result information and the model result information.

In this step, according to the behavior result information sent by the hardware verification platform and the model result information calculated by the software verification platform based on the behavior information, the chip to be verified can be verified and reviewed, that is, to determine whether the chip to be verified is defective, and if there is a defect, It is also possible to further perform positioning analysis on defects, etc.

In the chip verification method provided by the embodiments of the present invention, the software verification platform can receive the behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform, and run the pending chip according to the behavior information. Verifying the reference model corresponding to the chip, obtaining the corresponding model result information, and performing verification review on the chip to be verified according to the behavior result information and the model result information. In this way, the hardware verification platform can be combined with the software verification platform. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby realizing large-scale and fast verification of the chip to be verified. The platform receives the behavior information and behavior result information of the chip to be verified in the hardware verification, and verifies the same behavior of the chip to be verified on the software verification platform, so that it can use the various and perfect defect detection methods in the software verification method to troubleshoot the chip to be verified Therefore, while giving full play to the large-scale and rapid verification advantages of the hardware verification platform, it is convenient for defect detection.

Specifically, in step S21, the specific form of the behavior information and behavior result information received by the software verification platform can be pre-agreed by the software verification platform and the hardware verification platform, as long as the two parties can identify the behavior information and behavior result information. For example, in one embodiment of the present invention, receiving the behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform may specifically include: receiving the verification data packet sent by the hardware verification platform, The verification data packet is generated from the behavior information and behavior result information according to a preset protocol; the verification data packet is analyzed to obtain the behavior information and the behavior result information. Optionally, the behavior information and behavior result information may be encapsulated in the same verification data packet, or encapsulated in different verification data packets.

After the software verification platform receives the above behavior information and behavior result information, it can run the reference model corresponding to the chip to be verified according to the behavior information. Optionally, in one embodiment of the present invention, the reference model can be run offline, that is, the hardware verification platform can continue to perform subsequent simulation verification operations without waiting for the verification review result of the software verification platform, thereby further improving verification efficiency . In another embodiment of the present invention, the reference model can also be run online, that is, the hardware verification platform can wait for the verification review result of the software verification platform, and determine whether to continue the subsequent hardware simulation verification operation according to the verification review result, thereby Compared with the existing technology, the verification efficiency can be improved, and the problem of the chip to be verified can be found in a timely manner, without the need for a large number of subsequent verifications, effectively saving verification resources.

Specifically, in one embodiment of the present invention, in step S22, running the reference model corresponding to the chip to be verified according to the behavior information may specifically include: restoring the behavior information to the to-be-verified chip through a preset script A behavior sequence of the chip; using the behavior sequence to drive the operation of the reference model. Optionally, behavior information may exist in various forms such as text and tables. In order for the software verification platform to run the reference model corresponding to the chip to be verified according to the behavior information, the behavior information can be further processed. For example, the behavior information can be restored to the behavior sequence of the chip to be verified. The first operation, the second operation at the second moment, etc., so that the reference model corresponding to the chip to be verified can perform simulation calculations according to a series of behaviors in the behavior sequence, and obtain the model result information corresponding to the behavior information. Optionally, the behavior sequence can be based on any format or language that the software verification platform can recognize, for example, it can be based on the Verilog language.

After the model result information is obtained, the chip to be verified can be verified and rechecked in step S23 according to the behavior result information and the model result information. Specifically, the verification review operation may include: comparing the behavior result information with the model result information; and determining whether the chip to be verified passes the verification according to the comparison result. For example, if the comparison result is: the behavior result information is consistent with the model result information, it means that for the same chip behavior, the results obtained by hardware verification and software verification are consistent, so it can be determined that the verification of the chip to be verified has passed; if the comparison The result is: if the behavior result information is inconsistent with the model result information, it means that for the same chip behavior, the results obtained by hardware verification and software verification are inconsistent, so it can be determined that the verification of the chip to be verified has not passed (ie, verification failed).

Further, in one embodiment of the present invention, if the comparison result shows that the verification of the chip to be verified fails, the chip verification method provided by the embodiment of the present invention may further include: according to the comparison result, Verify the chip for defect troubleshooting. That is to say, for a chip that fails verification, the chip verification method provided by the embodiment of the present invention can also use various defect detection tools and means built in the software verification platform to analyze the cause of the failure and help users find the cause of the verification failure. chip defects, so that users can modify the chip design accordingly to overcome the defects.

Furthermore, in addition to detecting whether the chip to be verified has passed the verification according to the behavior result information and the model result information, in the embodiment of the present invention, the behavior information can also be used to verify whether the chip to be verified has defects. For example, in an embodiment of the present invention, the behavior information received by the software verification platform may include one or more of the following: instruction exit information, instruction memory access information, and instruction interruption information. And when the behavior information includes the memory access information of the instruction, the memory access information can also be used to verify the memory consistency and/or cache consistency of the chip to be verified.

For example, in one embodiment of the present invention, the memory access information of the instruction may include one or more of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, The memory access information lost due to the situation, the memory information updated due to the predictive execution of the instruction; then, before performing verification review on the chip to be verified according to the behavior result information and the model result information, the embodiment of the present invention The provided chip verification method may further include: according to the memory access information, detecting whether the chip to be verified has a cache consistency defect and/or a memory consistency defect. That is to say, in the case of multi-core shared memory or multi-thread shared memory, each processor core or different threads of the same processor core need to abide by the preset memory access rules. If the memory access rules are not followed, there will be There may be a problem of inconsistency in reading data in the same memory unit by multiple processor cores, or inconsistency in the cache data of the same memory unit in caches of different processor cores. In this embodiment, the software verification platform can determine whether the chip to be verified has memory consistency and/or cache consistency defects according to whether the above memory access information conforms to preset memory access rules.

For example, in one embodiment of the present invention, the actual execution order of the instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order of the memory by the at least one processor core It may be the actual memory access sequence corresponding to the actual execution sequence of the instructions in the hardware emulation program; then based on this, according to the memory access information, detect whether the chip to be verified has cache consistency defects and/or memory consistency The defect may specifically include: determining the specified execution sequence of the instructions according to the actual execution sequence of the instructions received from the hardware verification platform in advance and the sequence adjustment information of the instructions; A memory access sequence is specified, and whether there is a cache consistency defect and/or a memory consistency defect in the chip to be verified is detected.

In the embodiment of the present invention, in addition to the out-of-order execution and/or speculative execution of instructions will affect the verification review of the software verification platform, in a multi-core processor, if the clock frequencies of the cores of each processor are different, the software verification platform will also be affected. validation review for , and therefore require special handling.

For example, in one embodiment of the present invention, the number of processor cores of the chip to be verified is at least two, and there are at least one first processor core and one second processor core, the first processing The clock frequency of the processor core is different from the clock frequency of the second processor core; the access order of the at least two processor cores to the memory is based on the access order of the respective clocks of the processor cores; then based on this, according to the memory Accessing information, and detecting whether the chip to be verified has a cache consistency defect and/or a memory consistency defect may specifically include: synchronizing the access sequence based on the respective clocks of the processor cores according to the clock difference of each processor core, Obtaining a synchronization sequence; according to the synchronization sequence, detecting whether the chip to be verified has a cache consistency defect and/or a memory consistency defect.

The chip verification method provided by the embodiment of the present invention will be described in detail below through a specific embodiment.

As shown in Figure 4, the chip verification method provided by the embodiment of the present invention may include:

S301. Running a hardware simulation program of the chip to be verified on the hardware verification platform;

Wherein, the hardware verification platform may be based on a hardware emulation accelerator Emulator.

S302. When the hardware verification platform executes each instruction in the hardware emulation program, obtains the behavior information of the instruction;

Optionally, the behavior information of the instruction may include, for example, exit information of the instruction, memory access information of the instruction, and the like. Wherein, the memory access information of the instruction may include one or more of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, memory access information lost due to an abnormal situation, Memory information updated by speculative execution, etc.

S303. After executing each instruction in the hardware simulation program, the hardware verification platform acquires behavior result information corresponding to the instruction;

Optionally, the behavior result information may include fixed-point register information after the instruction exits, floating-point register information after the instruction exits, status register information after the instruction exits, and the like.

S304. The hardware verification platform generates a verification data packet from the behavior information and behavior result information according to a preset protocol;

Optionally, the hardware verification platform may first determine whether the instruction is a speculatively executed instruction, and in response to the instruction being a speculatively executed instruction, determine whether the prediction of the speculatively executed instruction is successful; if the prediction is successful, follow Preset agreement, generate verification data packets from behavior information and behavior result information, so as to send the behavior information and behavior result information to the software verification platform; in the case of prediction failure, refuse to generate verification information from the behavior information and behavior result information data pack.

S305. The hardware verification platform sends a verification data packet to the software verification platform through a direct programming interface;

S306. The software verification platform receives and parses the verification data packet, and obtains the behavior information and the behavior result information;

S307. The software verification platform detects whether the chip to be verified has a cache consistency defect and/or a memory consistency defect according to the memory access information in the behavior information;

S308. The software verification platform restores the behavior information to the behavior sequence of the chip to be verified through a preset script;

For example, the preset script can be, for example, a Python script.

S309. The software verification platform uses the behavior sequence to drive the reference model corresponding to the chip to be verified to run;

S310. The software verification platform compares the behavior result information with the model result information obtained by running the reference model;

S311. The software verification platform determines whether the chip to be verified passes the verification according to the comparison result;

S312. The software verification platform performs defect inspection on the chips to be verified that fail the verification.

Optionally, various debugging tools, such as software tools similar to monitor and checker, can be used to locate and analyze defects.

Correspondingly, in the third aspect, the embodiment of the present invention also provides a chip verification device, which can facilitate defect detection while giving full play to the large-scale and fast verification advantages of the hardware verification platform.

As shown in Figure 5, the chip verification device provided by the embodiment of the present invention may include:

The first running unit 41 is used to run a hardware emulation program of the chip to be verified;

The sending unit 42, according to a preset policy, sends the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform, so that the software verification platform The chip to be verified undergoes a verification review.

The chip verification device provided by the embodiment of the present invention can run the hardware simulation program of the chip to be verified, and send the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform according to the preset strategy, so that The software verification platform performs a verification review on the chip to be verified according to the behavior information and the behavior result information. In this way, the hardware verification platform can be combined with the software verification platform. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby realizing large-scale and fast verification of the chip to be verified. The behavior information and behavior result information of the chip to be verified are sent to the software verification platform, so that the software verification platform can verify the same behavior of the chip to be verified in software, so that the various and perfect defect detection methods in the software verification method can be used to troubleshoot the pending defects. To verify the defects in the chip, it is possible to make full use of the large-scale and rapid verification advantages of the hardware verification platform, and at the same time facilitate defect detection.

In one embodiment, the sending unit 42 can be specifically configured to send the behavior information and Behavior Outcome Information.

In an implementation manner, the behavior information may include at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information.

In one embodiment, the memory access information of the instruction includes at least one of the following: at least one processor core's access sequence to the memory, memory type, size of the accessed data, memory access information lost due to an abnormal situation , Memory information updated due to speculative execution of instructions.

In one embodiment, the actual execution order of the instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order corresponds to the actual execution order of the instructions in the hardware emulation program The actual memory access sequence of the instruction; the sending unit 42 is specifically configured to: send the actual memory access sequence corresponding to the actual execution sequence of the instruction and the order adjustment information of the instruction to the software verification platform; or, according to the instruction The actual execution sequence of the instruction and the sequence adjustment information of the instruction, determine the specified execution sequence of the instruction, and send the specified memory access sequence corresponding to the specified execution sequence to the software verification platform.

In one embodiment, the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the clock frequency of the first processor core is the same as the clock frequency of the The clock frequency of the second processor core is different; the access order of the at least two processor cores to the memory is based on the access order of the respective clocks of the processor cores; the sending unit 42 can be specifically used to: The clock access sequence and the clock difference of each processor core are sent to the software verification platform, or, according to the clock difference of each processor core, the access sequence based on the respective clocks of the processor cores is synchronized to obtain a synchronization sequence, Sending the synchronization sequence to the software verification platform.

In one embodiment, the device further includes: a first determination unit, configured to determine the behavior information and behavior result information of the chip to be verified during program execution before sending the behavior information and behavior result information of the chip to be verified to the software verification platform according to a preset policy. Whether the instruction corresponding to the behavior information and the behavior result information is a predictively executed instruction; a second determining unit is configured to determine whether the predictively executed instruction is predicted to be successful in response to the instruction being a predictively executed instruction; The sending unit is specifically used to: send the behavior information and the behavior result information to the software verification platform if the prediction is successful; refuse to send the behavior information and the behavior result information to the software verification platform if the prediction fails Information about the outcome of the behavior described above.

In one embodiment, the behavior result information includes at least one of the following: fixed-point register information after the instruction exits, floating-point register information after the instruction exits, and status register information after the instruction exits.

In one embodiment, the chip verification device may further include:

The first acquiring unit is configured to, after running the hardware emulation program of the chip to be verified, send the behavior information and behavior result information of the chip to be verified to the software verification platform according to the preset strategy, before executing When each instruction in the hardware emulation program, obtain the behavior information of the instruction;

The second acquiring unit, after executing each instruction in the hardware emulation program, acquires the behavior result information corresponding to the instruction;

A generating unit, configured to generate a verification data packet from the behavior information and the behavior result information according to a preset protocol;

The sending unit 42 is specifically configured to send the verification data packet to the software verification platform.

In one embodiment, the sending unit 42 is specifically configured to send the behavior information and behavior result information of the chip to be verified during program running to the software verification platform through the direct programming interface DPI.

Correspondingly, in the fourth aspect, the embodiments of the present invention further provide a chip verification device, which can facilitate defect detection while giving full play to the large-scale and fast verification advantages of the hardware verification platform.

As shown in Figure 6, the chip verification device provided by the embodiment of the present invention may include:

The receiving unit 51 is configured to receive behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform;

The second running unit 52 runs the reference model corresponding to the chip to be verified according to the behavior information to obtain corresponding model result information;

The review unit 53 is configured to perform a verification review on the chip to be verified according to the behavior result information and the model result information.

The chip verification device provided by the embodiment of the present invention can receive the behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform, and run the corresponding chip to be verified according to the behavior information. obtain the corresponding model result information, and perform a verification review on the chip to be verified according to the behavior result information and the model result information. In this way, the hardware verification platform can be combined with the software verification platform. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby realizing large-scale and fast verification of the chip to be verified. The platform receives the behavior information and behavior result information of the chip to be verified in the hardware verification, and verifies the same behavior of the chip to be verified on the software verification platform, so that it can use the various and perfect defect detection methods in the software verification method to troubleshoot the chip to be verified Therefore, while giving full play to the large-scale and rapid verification advantages of the hardware verification platform, it is convenient for defect detection.

In one embodiment, the receiving unit 51 may include:

A receiving module, configured to receive a verification data packet sent by a hardware verification platform, wherein the verification data packet is generated from the behavior information and the behavior result information according to a preset protocol;

An analysis module, configured to analyze the verification data packet to obtain the behavior information and the behavior result information.

In one embodiment, the second operating unit 52 may include:

A restore module, configured to restore the behavior information to the behavior sequence of the chip to be verified through a preset script;

A driving module, configured to use the behavior sequence to drive the reference model to run.

In one embodiment, the review unit 53 may include:

A comparison module, configured to compare the behavior result information with the model result information;

A determining module, configured to determine whether the chip to be verified has passed the verification according to the comparison result.

In one embodiment, the comparison result is that the verification of the chip to be verified fails; the device may further include: a troubleshooting unit, configured to perform defect troubleshooting on the chip to be verified according to the comparison result.

In an implementation manner, the behavior information may include at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information.

In one embodiment, the memory access information of the instruction may include at least one of the following: memory access order of at least one processor core, memory type, size of accessed data, memory access lost due to an abnormal situation information, memory information updated due to the predictive execution of instructions; the device also includes: a detection unit, used to check the chip to be verified according to the behavior result information and the model result information The memory access information detects whether there is a cache consistency defect and/or a memory consistency defect in the chip to be verified.

In one embodiment, the actual execution order of the instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order corresponds to the actual execution order of the instructions in the hardware emulation program The actual memory access sequence; the detection unit includes: a sequence determination module, which is used to determine the specified execution of the instruction according to the actual execution sequence of the instruction and the order adjustment information received from the hardware verification platform in advance Sequence; the first detection module is configured to detect whether the chip to be verified has a cache coherency defect and/or a memory consistency defect according to the specified memory access sequence corresponding to the specified execution sequence of the instructions.

In one embodiment, the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the clock frequency of the first processor core is the same as the clock frequency of the The clock frequency of the second processor core is different; the access order of the at least two processor cores to the memory is based on the access order of the respective clocks of the processor cores; the detection unit includes: a clock synchronization module, for according to each processor The clock difference of the core is to synchronize the access sequence based on the respective clocks of the processor cores to obtain a synchronization sequence; the second detection module is used to detect whether there is a cache consistency defect and a cache consistency defect in the chip to be verified according to the synchronization sequence. /or memory consistency flaws.

Correspondingly, in the fifth aspect, the embodiment of the present invention also provides a chip verification system. As shown in FIG. 7 , the system may include a hardware verification platform 61 and a software verification platform 62; The verification platform 62 is connected in communication; wherein, the hardware verification platform 61 is used to execute any chip verification method based on the hardware verification platform in the foregoing embodiments, and the software verification platform is used to execute any method based on the software verification platform in the foregoing embodiments. A chip verification method is used, so corresponding beneficial technical effects can also be achieved, which has been described in detail above and will not be repeated here.

In the sixth aspect, as shown in FIG. 8 , an embodiment of the present invention also provides an electronic device, including: a housing 100, at least one processor 110, a memory 120, a circuit board 130, and a power supply circuit 140, wherein the circuit board 130 Arranged inside the space enclosed by the casing 100, the processor 110 and the memory 120 are arranged on the circuit board 130; the power supply circuit 140 is used to supply power to each circuit or device of the above-mentioned electronic equipment; the memory 120 is used to store executable program codes The processor 110 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 120, so as to execute any chip verification method provided in the foregoing embodiments. For the specific execution process of the above steps by the processor 110 and the further steps executed by the processor 110 by running the executable program code, reference may be made to the description of the foregoing embodiments, and details are not repeated here.

In the seventh aspect, the embodiments of the present invention also provide a computer-readable storage medium, the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors , so as to implement any one of the chip verification methods provided in the foregoing embodiments. For the specific execution process of the above steps by the processor and the further steps executed by the processor by running the executable program code, reference may be made to the description of the foregoing embodiments, and details are not repeated here.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Each embodiment in this specification is described in a related manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.

In particular, as for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment.

For the convenience of description, the above devices are described by dividing their functions into various units/modules and describing them separately. Of course, when implementing the present invention, the functions of each unit/module can be implemented in one or more pieces of software and/or hardware.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented through computer programs to instruct related hardware, and the programs can be stored in a computer-readable storage medium. During execution, it may include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random AccessMemory, RAM), etc.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (41)

1. A chip verification method, characterized in that, based on a hardware verification platform, comprising: Run the hardware emulation program of the chip to be verified; According to the preset policy, send the behavior information and behavior result information of the chip to be verified to the software verification platform during the program operation, so that the software verification platform can perform the verification on the to-be-verified chip according to the behavior information and the behavior result information Chip verification review. 2. The method according to claim 1, wherein, according to a preset strategy, sending the behavior information and behavior result information of the chip to be verified to the software verification platform during program operation comprises: After each instruction in the hardware emulation program finishes running, the behavior information and behavior result information of the chip to be verified during program running are sent to the software verification platform. 3. The method according to claim 1, wherein the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information. 4. The method according to claim 3, wherein the memory access information of the instruction includes at least one of the following: at least one processor core access sequence to the memory, memory type, size of the accessed data, Memory access information lost due to exceptional conditions, memory information updated due to speculative execution of instructions. 5. The method according to claim 4, wherein the actual execution order of instructions in the hardware emulation program of the chip to be verified comprises out-of-order execution and/or predictive execution; the access order is the hardware emulation program The actual memory access sequence corresponding to the actual execution sequence of the instructions in ; The sending the behavior information and behavior result information of the chip to be verified during program running to the software verification platform includes: sending the actual memory access sequence corresponding to the actual execution sequence of the instructions and the order adjustment information of the instructions to the sending by the software verification platform; or, according to the actual execution sequence of the instructions and the order adjustment information of the instructions, determine the specified execution sequence of the instructions, and send the specified memory access sequence corresponding to the specified execution sequence to the software verification platform . 6. The method according to claim 4, wherein the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the first processing The clock frequency of the processor core is different from the clock frequency of the second processor core; the access sequence of the at least two processor cores to the memory is an access sequence based on the respective clocks of the processor cores; The sending the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform includes: Send the access sequence based on the respective clocks of the processor cores and the clock difference of each processor core to the software verification platform, or, according to the clock differences of each processor core, the access sequence based on the respective clocks of the processor cores The sequence is synchronized to obtain the synchronization sequence, and the synchronization sequence is sent to the software verification platform. 7. The method according to claim 1, wherein, before sending the behavior information and behavior result information of the chip to be verified to the software verification platform according to the preset strategy, the method further comprises : determining whether the instruction corresponding to the behavior information and the behavior result information is a speculatively executed instruction; in response to the instruction being a speculatively executed instruction, determining whether the speculatively executed instruction was predicted to succeed; The sending the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform according to the preset strategy includes: sending the behavior information and the behavior result information to the software verification platform if the prediction is successful. Result information; in the case of prediction failure, refusing to send the behavior information and the behavior result information to the software verification platform. 8. The method according to claim 1, wherein the behavior result information includes at least one of the following: The fixed-point register information after the instruction exits, the floating-point register information after the instruction exits, and the status register information after the instruction exits. 9. The method according to any one of claims 1 to 8, wherein after the hardware emulation program of the chip to be verified is run, the chip to be verified is sent to the software verification platform according to a preset strategy. Before the behavior information and behavior result information during program running, the method further includes: When executing each instruction in the hardware emulation program, obtain the behavior information of the instruction; After executing each instruction in the hardware emulation program, obtain behavior result information corresponding to the instruction; generating a verification data packet from the behavior information and the behavior result information according to a preset protocol; The sending the behavior information and behavior result information of the chip to be verified during program running to the software verification platform includes: sending the verification data packet to the software verification platform. 10. The method according to any one of claims 1 to 8, wherein the sending the behavior information and behavior result information of the chip to be verified to the software verification platform during program operation comprises: The behavior information and behavior result information of the chip to be verified during program operation are sent to the software verification platform through the direct programming interface DPI. 11. A chip verification method, characterized in that, based on a software verification platform, comprising: Receiving behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform; Running a reference model corresponding to the chip to be verified according to the behavior information to obtain corresponding model result information; Perform verification review on the chip to be verified according to the behavior result information and the model result information. 12. The method according to claim 11, wherein the behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the receiving hardware verification platform include: receiving a verification data packet sent by a hardware verification platform, wherein the verification data packet is generated from the behavior information and the behavior result information according to a preset protocol; Analyzing the verification data packet to obtain the behavior information and the behavior result information. 13. The method according to claim 11, wherein the running the reference model corresponding to the chip to be verified according to the behavior information comprises: Restoring the behavior information to the behavior sequence of the chip to be verified through a preset script; The operation of the reference model is driven by the behavior sequence. 14. The method according to claim 11, wherein, according to the behavior result information and the model result information, performing a verification review on the chip to be verified comprises: comparing the behavior result information with the model result information; Determine whether the chip to be verified has passed the verification according to the comparison result. 15. The method according to claim 14, wherein the comparison result is that the verification of the chip to be verified has failed, and the method further comprises: According to the comparison result, defect checking is performed on the chip to be verified. 16. The method according to claim 11, wherein the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information. 17. The method according to claim 16, wherein the memory access information of the instruction includes at least one of the following: at least one processor core access sequence to the memory, memory type, size of the accessed data, Memory access information lost due to abnormal conditions, memory information updated due to speculative execution of instructions; According to the behavior result information and the model result information, before performing verification review on the chip to be verified, the method further includes: According to the memory access information, it is detected whether the chip to be verified has a cache consistency defect and/or a memory consistency defect. 18. The method according to claim 17, wherein the actual execution order of instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order is the hardware emulation program The actual memory access sequence corresponding to the actual execution sequence of the instructions; The detecting whether the chip to be verified has a cache consistency defect and/or a memory consistency defect according to the memory access information includes: Determine the specified execution order of the instructions according to the actual execution order of the instructions received in advance from the hardware verification platform and the order adjustment information of the instructions; According to the specified memory access sequence corresponding to the specified execution sequence of the instructions, it is detected whether the chip to be verified has a cache consistency defect and/or a memory consistency defect. 19. The method according to claim 17, wherein the number of the processor cores is at least two, and at least one first processor core and one second processor core exist, and the first processing The clock frequency of the processor core is different from the clock frequency of the second processor core; the access sequence of the at least two processor cores to the memory is an access sequence based on the respective clocks of the processor cores; The detecting whether the chip to be verified has a cache consistency defect and/or a memory consistency defect according to the memory access information includes: According to the clock difference of each processor core, the access sequence based on the respective clocks of the processor cores is synchronized to obtain a synchronization sequence; According to the synchronization sequence, it is detected whether the chip to be verified has a cache consistency defect and/or a memory consistency defect. 20. A chip verification device, characterized in that it comprises: The first running unit is used to run a hardware emulation program of the chip to be verified; The sending unit sends the behavior information and behavior result information of the chip to be verified during program operation to the software verification platform according to a preset policy, so that the software verification platform performs The chip to be verified is verified and reviewed. 21. The device according to claim 20, wherein the sending unit is specifically configured to send the chip to be verified to the software verification platform after each instruction in the hardware emulation program finishes running. Behavior information and behavior result information during program running. 22. The device according to claim 20, wherein the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information. 23. The device according to claim 22, wherein the memory access information of the instruction includes at least one of the following: at least one processor core access sequence to the memory, memory type, size of the accessed data, Memory access information lost due to exceptional conditions, memory information updated due to speculative execution of instructions. 24. The device according to claim 23, wherein the actual execution order of instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order is the hardware emulation program The actual memory access sequence corresponding to the actual execution sequence of the instructions; The sending unit is specifically configured to: send the actual memory access sequence corresponding to the actual execution sequence of the instructions and the sequence adjustment information of the instructions to the software verification platform; or, according to the actual execution sequence of the instructions and The sequence adjustment information of instructions determines the specified execution sequence of the instructions, and sends the specified memory access sequence corresponding to the specified execution sequence to the software verification platform. 25. The device according to claim 23, wherein the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the first processing The clock frequency of the processor core is different from the clock frequency of the second processor core; the access sequence of the at least two processor cores to the memory is an access sequence based on the respective clocks of the processor cores; The sending unit is specifically used for: Send the access sequence based on the respective clocks of the processor cores and the clock difference of each processor core to the software verification platform, or, according to the clock differences of each processor core, the access sequence based on the respective clocks of the processor cores The sequence is synchronized to obtain the synchronization sequence, and the synchronization sequence is sent to the software verification platform. 26. The apparatus of claim 20, further comprising: The first determination unit is configured to determine the behavior information and the instruction corresponding to the behavior result information before sending the behavior information and behavior result information of the chip to be verified to the software verification platform during program operation according to a preset strategy Whether it is a speculatively executed instruction; a second determining unit, configured to determine whether the prediction of the speculatively executed instruction is successful in response to the instruction being a speculatively executed instruction; The sending unit is specifically used to: send the behavior information and the behavior result information to the software verification platform if the prediction is successful; refuse to send the behavior information and the behavior result information to the software verification platform if the prediction fails. Information about the result of the action. 27. The device according to claim 20, wherein the behavior result information includes at least one of the following: fixed-point register information after the instruction exits, floating-point register information after the instruction exits, and status register information after the instruction exits . 28. The apparatus of claims 20 to 27, further comprising: The first acquiring unit is configured to, after running the hardware emulation program of the chip to be verified, send the behavior information and behavior result information of the chip to be verified to the software verification platform according to the preset strategy, before executing When each instruction in the hardware emulation program, obtain the behavior information of the instruction; The second acquiring unit, after executing each instruction in the hardware emulation program, acquires the behavior result information corresponding to the instruction; A generating unit, configured to generate a verification data packet from the behavior information and the behavior result information according to a preset protocol; The sending unit is specifically configured to send the verification data packet to the software verification platform. 29. The device according to claims 20 to 27, wherein the sending unit is specifically configured to send behavior information and behavior results of the chip to be verified during program operation to the software verification platform through the direct programming interface DPI information. 30. A chip verification device, comprising: A receiving unit, configured to receive behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform; The second running unit runs the reference model corresponding to the chip to be verified according to the behavior information to obtain corresponding model result information; A review unit, configured to perform verification review on the chip to be verified according to the behavior result information and the model result information. 31. The device according to claim 30, wherein the receiving unit comprises: A receiving module, configured to receive a verification data packet sent by a hardware verification platform, wherein the verification data packet is generated from the behavior information and the behavior result information according to a preset protocol; An analysis module, configured to analyze the verification data packet to obtain the behavior information and the behavior result information. 32. The device according to claim 30, wherein the second operating unit comprises: A restore module, configured to restore the behavior information to the behavior sequence of the chip to be verified through a preset script; A driving module, configured to use the behavior sequence to drive the reference model to run. 33. The device according to claim 30, wherein the review unit comprises: A comparison module, configured to compare the behavior result information with the model result information; A determining module, configured to determine whether the chip to be verified has passed the verification according to the comparison result. 34. The device according to claim 33, wherein the comparison result is that the verification of the chip to be verified has failed; The device also includes: an inspection unit, configured to perform defect inspection on the chip to be verified according to the comparison result. 35. The device according to claim 30, wherein the behavior information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interruption information. 36. The device according to claim 35, wherein the memory access information of the instruction includes at least one of the following: at least one processor core access sequence to the memory, memory type, size of the accessed data, Memory access information lost due to abnormal conditions, memory information updated due to speculative execution of instructions; The device further includes: a detection unit, configured to detect whether the chip to be verified is There are cache coherency flaws and/or memory consistency flaws. 37. The device according to claim 36, wherein the actual execution order of instructions in the hardware emulation program of the chip to be verified includes out-of-order execution and/or predictive execution; the access order is the hardware emulation program The actual memory access sequence corresponding to the actual execution sequence of the instructions in ; The detection unit includes: A sequence determination module, configured to determine the specified execution sequence of the instructions according to the actual execution sequence of the instructions received in advance from the hardware verification platform and the sequence adjustment information of the instructions; The first detection module is configured to detect whether the chip to be verified has a cache coherency defect and/or a memory consistency defect according to a predetermined memory access sequence corresponding to the predetermined execution sequence of the instructions. 38. The device according to claim 36, wherein the number of the processor cores is at least two, and there is at least one first processor core and one second processor core, and the first processing The clock frequency of the processor core is different from the clock frequency of the second processor core; the access sequence of the at least two processor cores to the memory is an access sequence based on the respective clocks of the processor cores; The detection unit includes: A clock synchronization module, configured to synchronize the access sequences based on the respective clocks of the processor cores according to the clock differences of the processor cores to obtain a synchronization sequence; The second detection module is configured to detect whether the chip to be verified has a cache consistency defect and/or a memory consistency defect according to the synchronization order. 39. A chip verification system, characterized in that it includes a hardware verification platform and a software verification platform; the hardware verification platform communicates with the software verification platform through a preset interface; wherein the hardware verification platform is used to enforce rights The chip verification method according to any one of claims 1-10, the software verification platform is used to execute the chip verification method according to any one of claims 11-19. 40. An electronic device, characterized in that it comprises: a housing, at least one processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged in the circuit on board; a power supply circuit, used to supply power to each circuit or device of the above-mentioned electronic equipment; the memory is used to store executable program code; the at least one processor runs and executes by reading the executable program code stored in the memory The program corresponding to the program code is used to execute the chip verification method described in any one of claims 1-19. 41. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to realize the aforementioned rights The chip verification method described in any one of 1-19 is required.

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