CN116048233A - Power architecture, power monitoring method and device - Google Patents

Abstract

The embodiment of the invention provides a power supply architecture, a power supply monitoring method and a power supply monitoring device, which relate to the technical field of power supply design, wherein the power supply architecture comprises a voltage monitoring chip arranged on a back plate, and the voltage monitoring chip is connected with a baseboard management controller arranged on a main board; the voltage monitoring chip is used for monitoring the voltage of at least one hard disk slot on the backboard. Through the voltage monitoring chip arranged on the backboard, the voltage of the hard disk slot on the backboard can be monitored in real time, so that the failure rate of the disk failure of the storage system can be effectively reduced and user data can be effectively protected according to the monitored voltage of the hard disk slot, and the reliability of the whole machine of the server can be further improved.

Description

A power supply architecture, power supply monitoring method and device

technical field

Embodiments of the present invention relate to the technical field of power supply design, and in particular, relate to a power supply architecture, a power supply monitoring method, a power supply monitoring device, an electronic device, and a computer-readable storage medium.

Background technique

In recent years, with the development of 5G (5th Generation Mobile Communication Technology), cloud computing big data, and AI (Artificial Intelligence artificial intelligence) technology, a large amount of application data needs to be stored completely. These data include Hot data, warm data, cold data, and extremely cold data, among them, hot data has the highest frequency of operation, and extremely cold data has the lowest operation frequency. For these different types of data, device R&D manufacturers are required to manufacture highly reliable storage devices.

In the current traditional storage server design, there is a problem in the power structure of the hard disk that stores data, that is, all mechanical hard disks (Hard Disk Drive, HDD) and the disk array (Redundant Arrays of Independent Disks, Raid) controller have large data During fast interaction or burst (burst), the mechanical hard disk will draw a large current from the backplane, and then there will be a large voltage drop (rapid drop in voltage) between a single hard disk and the entire main circuit. In the simulation stage of the power supply engineer, This kind of real business scenario cannot be accurately achieved or infinitely approached. Therefore, if the power simulation margin of a single hard disk is insufficient, the designed server will sometimes have the risk of disk failure, which will cause certain damage to application data. , if the simulation margin of a single hard disk power supply is too large, then when all hard disks interact with the disk array controller at the same time with a burst of large data, the current consumed by all the hard disks will be very large, resulting in over-design, which will lead to The resettable fuse (electronic Fuse, eFuse for short) of the main circuit is too large in size, and the overall cost of hardware design increases. Based on this, this traditional power supply design architecture brings certain challenges to server system manufacturers.

Contents of the invention

Embodiments of the present invention provide a power supply framework, a power supply monitoring method, a power supply monitoring device, an electronic device, and a computer-readable storage medium, so as to solve or partially solve the mechanical hard disk and magnetic disk problems in the power supply design architecture. In the case of fast interaction of large data or sudden large voltage drop between array controllers, it may cause disk failure or damage to application data, as well as cost increase due to over-design of the architecture.

The embodiment of the present invention discloses a power architecture, including:

A voltage monitoring chip arranged on the backboard, the voltage monitoring chip is connected with a baseboard management controller arranged on the main board; the voltage monitoring chip is used for monitoring the voltage of at least one hard disk slot on the backboard.

Optionally, the backplane is also provided with a resettable fuse, and the resettable fuse is connected to the voltage regulation chip provided on the main board; it is used to send the voltage sent by the voltage regulation chip to the resettable fuse. Convert to the voltage required by the hard disk slot.

Optionally, the voltage monitoring chip is arranged next to the hard disk slot away from the resettable fuse on the backplane.

Optionally, the main board is further provided with a central processing unit, a platform controller and at least one flash memory particle connected in sequence.

Optionally, a disk array controller is also provided on the motherboard, the central processing unit is connected to the disk array controller through a first link, and the disk array controller is used to convert the first link to is a second link, and is connected to the hard disk in the hard disk slot through the second link.

Optionally, a power connector is further arranged on the backplane, and the power connector supplies power to the hard disk through the resettable fuse.

Optionally, the voltage of the hard disk slot is the working voltage of the hard disk in the hard disk slot.

The embodiment of the present invention also provides a power monitoring method, the method comprising:

Monitor the voltage of the hard disk slot through the voltage monitoring chip;

judging by the baseboard management controller whether to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller;

An instruction to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller is issued by the central processing unit.

Optionally, after the step of monitoring the voltage of the hard disk slot through the voltage monitoring chip, the method further includes:

When the voltage monitoring chip monitors that the voltage of the hard disk slot is lower than a preset voltage threshold, an interrupt signal is sent to the baseboard management controller through the voltage monitoring chip.

Optionally, the step of judging whether to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller through the baseboard management controller includes:

Sending a voltage request to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and using the voltage of the hard disk slot obtained by the baseboard management controller as a verification voltage;

judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage, so as to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller;

When the interrupt signal is not a false positive, it is determined to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller.

Optionally, the step of judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage includes:

If the verification voltage is less than a preset voltage threshold, it is determined that the interruption signal is not a false alarm.

Optionally, after the step of determining to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller when the interrupt signal is not a false positive, the method further includes:

The baseboard management controller sends an interrupt mode corresponding to the interrupt signal to the platform controller; wherein the interrupt mode is a mode of interrupting the interactive process between the hard disk in the hard disk slot and the disk array controller;

When the platform controller receives the interrupt mode, the platform controller reports the interrupt mode to the central processing unit.

Optionally, the step of sending instructions to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller through the central processing unit includes:

When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller so that the disk array controller interrupts the operation of the hard disk slot. Interaction process between hard disk and disk array controller.

Optionally, the central processing unit is provided with a computer management control program, and the computer management control program is used to issue an interrupt command corresponding to the interrupt mode to the disk array controller.

Optionally, the baseboard management controller is provided with firmware for the baseboard management controller, and the method further includes:

When the baseboard management controller runs the firmware of the baseboard management controller, the firmware monitors whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller.

Optionally, the method also includes:

setting a priority for the interrupt signal in firmware of the baseboard management controller;

When the baseboard management controller receives the interrupt signal, it processes the interrupt signal according to the priority.

Optionally, the method also includes:

If the interrupt signal is a false positive, re-execute the step of monitoring whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware.

Optionally, the interaction process between the hard disk in the hard disk slot and the disk array controller is data interaction between the disk array controller and the hard disk in the hard disk slot. After the instruction step of the hard disk of the hard disk slot and the interactive process of the disk array controller, the method also includes:

The data of the stop interaction between the disk array controller and the hard disk in the hard disk slot is stored in the disk array controller.

The embodiment of the present invention also provides a power monitoring device, which includes:

The voltage monitoring module is used to monitor the voltage of the hard disk slot through the voltage monitoring chip;

A process judging module, configured to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller through the baseboard management controller;

The instruction sending module is used to send an instruction to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller through the central processing unit.

Optionally, the device also includes:

A signal sending module, configured to send an interrupt signal to the baseboard management controller through the voltage monitoring chip when the voltage of the hard disk slot monitored by the voltage monitoring chip is lower than a preset voltage threshold.

Optionally, the process judging module is specifically used for:

Sending a voltage request to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and using the voltage of the hard disk slot obtained by the baseboard management controller as a verification voltage;

judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage, so as to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller;

When the interrupt signal is not a false positive, it is determined to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller.

Optionally, the device also includes:

A non-false alarm determining module, configured to determine that the interruption signal is not a false alarm if the verification voltage is lower than a preset voltage threshold.

Optionally, the device also includes:

An interrupt mode sending module, configured to send an interrupt mode corresponding to the interrupt signal to the platform controller through the baseboard management controller; wherein, the interrupt mode is to interrupt the interaction between the hard disk in the hard disk slot and the disk array controller the manner of the process;

The interrupt mode reporting module is configured to report the interrupt mode to the central processing unit through the platform controller when the platform controller receives the interrupt mode.

Optionally, the instruction issuing module is specifically used for:

When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller so that the disk array controller interrupts the operation of the hard disk slot. Interaction process between hard disk and disk array controller.

Optionally, the baseboard management controller is provided with firmware for the baseboard management controller, and the device further includes:

A signal monitoring module, configured to monitor whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware when the baseboard management controller is running the firmware of the baseboard management controller.

Optionally, the device also includes:

a priority setting module, configured to set the priority for the interrupt signal in the firmware of the baseboard management controller;

A signal processing module, configured to process the interrupt signal according to the priority when the baseboard management controller receives the interrupt signal.

Optionally, the device also includes:

A monitoring and re-executing module, configured to re-execute the step of monitoring whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware if the interrupt signal is a false positive.

Optionally, the interaction process between the hard disk in the hard disk slot and the disk array controller is data interaction between the disk array controller and the hard disk in the hard disk slot, and the device further includes:

The data storage module is configured to store in the disk array controller the data of the stop interaction between the disk array controller and the hard disk in the hard disk slot.

The embodiment of the present invention also discloses an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete mutual communication through the communication bus;

The memory is used to store computer programs;

The processor is used to implement the power monitoring method according to the embodiment of the present invention when executing the program stored in the memory.

The embodiment of the present invention also discloses a computer-readable storage medium, on which instructions are stored, and when executed by one or more processors, the processors execute the power monitoring method according to the embodiment of the present invention.

Embodiments of the present invention include the following advantages:

In the embodiment of the present invention, the power supply architecture includes a voltage monitoring chip arranged on the backplane, and the voltage monitoring chip is connected to a baseboard management controller arranged on the motherboard; the voltage monitoring chip is used to monitor the voltage of at least one hard disk slot on the backplane Voltage. In the embodiment of the present invention, the voltage of the hard disk slots on the backplane can be monitored in real time through the voltage monitoring chip on the backplane, which can effectively reduce the failure rate of disk failure in the storage system and effectively protect user data. The reliability of the whole server can be greatly improved, and at the same time, the architecture mentioned in the embodiment of the present invention is simple, easy to implement, high in realizability, and low in cost.

Description of drawings

FIG. 1 is one of a schematic diagram of a power supply architecture provided in an embodiment of the present invention;

Fig. 2 is a second schematic diagram of a power supply architecture provided in an embodiment of the present invention;

FIG. 3 is a flowchart of steps of a power monitoring method provided in an embodiment of the present invention;

FIG. 4 is a schematic flowchart of a power monitoring method provided in an embodiment of the present invention;

Fig. 5 is a structural block diagram of a power monitoring device provided in an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a computer-readable storage medium provided in an embodiment of the present invention;

Fig. 7 is a schematic diagram of a hardware structure of an electronic device implementing various embodiments of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present invention, some technical features involved in the embodiments of the present invention are explained below:

Baseboard Management Controller (BMC for short), which is a dedicated microcontroller embedded on the motherboard of a computer (usually a server), BMC is responsible for managing the interface between the system management software and the platform hardware.

Clock Generator (Clock Generator), which is a device or device that generates clock signals for synchronous sequential circuits.

A clock fanout (Clock buffer), which usually refers to a fanout buffer based on a non-PLL (Phase-locked loops phase-locked loop), is a device that generates multiple clock signals through frequency replication of one clock source signal , usually the clock fan-out also has the functions of clock distribution, format conversion and level conversion.

High-speed serial computer expansion bus (peripheral component interconnect express referred to as PCIE), which is a high-speed serial computer expansion bus standard, PCIE belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth, no Shared bus bandwidth mainly supports functions such as active power management, error reporting, end-to-end reliable transmission, hot swapping, and quality of service.

Firmware (firmware referred to as FW), which is a low-level software written in rewritable memory, runs the firmware to initialize the chip and its peripherals after the chip is powered on.

The central processing unit (Central Processing Unit referred to as CPU), as the computing and control core of the computer system, is the final execution unit of information processing and program operation.

Graphics Processing Unit (Graphics Processing Unit referred to as GPU), also known as display core, visual processor, display chip, is a special graphics processing unit on personal computers, workstations, game consoles and some mobile devices (such as tablets, smartphones, etc.) A microprocessor that does image and graphics-related operations.

Programmable gate array (Field Programmable Gate Array referred to as FPGA), which is a product of further development on the basis of programmable devices such as programmable array logic and general array logic. It appeared as a semi-custom circuit in the field of application-specific integrated circuits, which not only solved the shortcomings of custom circuits, but also overcome the shortcomings of the limited number of original programmable device gates.

System Management Bus (SMBUS for short), which is used for low-speed communication in mobile computers and desktop computer systems, hopes to control the devices on the motherboard through a cheap and powerful bus (composed of two lines) and collect relevant information.

As an example, in the current traditional storage server design, CPU and PCH (PlatformController Hub platform controller) are interconnected through DMI (Direct Media Interface Direct Media Interface) link, and PCH is connected through SPI (Serial Peripheral Interface) Interface) link and the first Flash (flash memory) particles are interconnected, the FW (firmware) of the BIOS (Basic Input Output System) is stored in the first flash memory particles, and the BMC (baseboard management controller) is also connected through the SPI The link is interconnected with the second flash memory particle, the FW (firmware) of the BMC is stored in the second flash memory particle, the CPU is interconnected with the Raid controller through the PCIE link, and the Raid controller can be used for protocol conversion, specifically, the PCIE The link is converted into a SAS/SATA (hard disk interface type) link, and then connected to the connector on the motherboard through the SAS/SATA link, and then connected to the connector on the backplane (Backplane) through the cable (cable), and finally Connect to the mechanical hard disk (HDD) on the backplane; the voltage regulation chip (VR Chip) on the motherboard can output P12V power to the connector on the motherboard, and then connect to the fuse (eFuse) on the backplane through a cable. The fuse can convert the P12V power to the P12V and P5V power required by the mechanical hard disk inserted in the slot on the backplane; at the same time, the BMC and PCH can be interconnected through the IPMI (Intelligent Platform Management Interface) link , BMC is connected to the connector on the motherboard through the I2C (Inter-Integrated Circuit bidirectional two-wire synchronous serial bus) link, and then connected to the fuse on the backplane through the cable, and the power supply of the main circuit on the backplane is controlled. voltage and current monitoring.

However, the power architecture of the backplane on this storage server is still in the development stage. Due to space issues in the chassis and on the backplane, the power connectors for transmitting P12V on the backplane are generally placed at both ends of the backplane. Then through the PCB (Process Control Block process management block) transmission, the mechanical hard disk on the slot is powered respectively. The specific voltage drop and current path on each slot are simulated in advance by the power engineer. In the current traditional storage server design , there is a problem in the power structure of the hard disk that stores data, that is: when all mechanical hard disks interact with the disk array controller quickly or suddenly, the mechanical hard disk will draw a large current from the backplane, and then a single hard disk and There will be a large voltage drop (rapid voltage drop) between the entire main circuit, and the simulation stage of the power supply engineer cannot accurately achieve or infinitely approach this real business scenario, so if the power supply simulation margin of a single hard disk Insufficient, it will lead to the risk of disk failure in the designed server at certain times, which will cause certain damage to application data. If the power simulation margin of a single hard disk is too large, then there will be large data between all hard disks and the disk array controller at the same time. When there is a sudden interaction of all hard disks, the current consumed by all the hard disks will be very large, resulting in over-design, which in turn leads to excessive selection of fuses for the main circuit, and an increase in the overall cost of hardware design. Based on this, this traditional power supply design architecture brings certain challenges to server system manufacturers.

In this regard, one of the core inventive points of the present invention is that the power supply architecture includes a voltage monitoring chip set on the backplane, and the voltage monitoring chip is connected to a baseboard management controller set on the mainboard, wherein the voltage monitoring chip is used to monitor the backplane voltage of at least one hard disk slot on the In the embodiment of the present invention, the voltage of the hard disk slots on the backplane can be monitored in real time through the voltage monitoring chip on the backplane, so that the disk failure of the storage system can be effectively reduced according to the real-time monitored voltage of the hard disk slots. The failure rate and effective protection of user data can further improve the reliability of the server as a whole. At the same time, the architecture mentioned in the embodiments of the present invention is simple, easy to implement, high in realizability, and low in cost.

Referring to FIG. 1 , it shows one of the schematic diagrams of a power supply architecture provided in an embodiment of the present invention; the power supply architecture includes a voltage monitoring chip arranged on a backplane, and the voltage monitoring chip and a baseboard management controller arranged on a mainboard connected; the voltage monitoring chip is used to monitor the voltage of at least one hard disk slot on the backboard.

Among them, the power supply architecture includes a mainboard and a backplane. The backplane is provided with a voltage monitoring chip, and the mainboard is provided with a baseboard management controller. The voltage monitoring chip is connected with the baseboard management controller provided on the mainboard. The voltage of at least one hard disk slot on the board.

For the voltage monitoring chip, it can be an ADC (Analog-to-digital converter analog-to-digital converter), which can be used to monitor the voltage of the hard disk slot; wherein, a mechanical hard disk can be inserted into the hard disk slot, and the voltage of the hard disk slot , which can be understood as the voltage of the mechanical hard disk on the hard disk slot during normal operation. For example, under normal circumstances, the voltage of the mechanical hard disk can be 12V or higher than 12V (such as 12.1V or 12.2V). It can be understood It is worth noting that those skilled in the art can adjust the voltage value for the normal operation of the mechanical hard disk according to the actual situation, which is not limited in the embodiment of the present invention.

As for the mechanical hard disk, it is a hard disk inserted into the hard disk slot on the backplane, which can be used for data interaction with the disk array controller.

Optionally, the backplane is also provided with a resettable fuse, and the resettable fuse is connected to the voltage regulation chip provided on the main board; it is used to send the voltage sent by the voltage regulation chip to the resettable fuse. Convert to the voltage required by the hard disk slot.

Among them, for the recoverable fuse, in the embodiment of the present invention, the fuse is a recoverable fuse (eFuse), which has high feasibility and low cost, and is different from the general fuse, which is blown after overcurrent , is not recoverable, so it has certain feasibility, and the fuse in the embodiment of the present invention is a recoverable fuse, and the recoverable fuse can be used to convert the voltage sent by the voltage regulation chip to the recoverable fuse into the power required by the hard disk slot . Wherein, the voltage required by the hard disk slot usually refers to the voltage of the mechanical hard disk on the hard disk slot when it is working normally. It can be understood that the voltage of the hard disk slot is the working voltage of the mechanical hard disk.

In a specific implementation, the backplane is also provided with a resettable fuse, which is connected to the voltage regulation chip arranged on the main board, and the resettable fuse is used to convert the voltage sent by the voltage regulation chip to the resettable fuse into the voltage required by the hard disk slot. required voltage.

Optionally, the voltage monitoring chip is arranged next to the hard disk slot away from the resettable fuse on the backplane.

In a specific implementation, the voltage monitoring chip is set next to the hard disk slot away from the resettable fuse on the backplane. A chip next to the slot, because the distance from the resettable fuse is the farthest, the voltage or current generated by the farthest hard disk slot will be relatively small, that is, the hard disk slot farthest from the resettable fuse If the operating voltage of the mechanical hard disk on the computer may be lower than the preset voltage threshold set by the voltage monitoring chip, the voltage drop generated by the hard disk slot will be the largest. Therefore, when the voltage monitoring chip detects that the operating voltage of the mechanical hard disk has When it is lower than the preset voltage threshold set by the voltage monitoring chip, other hard disk slots will also have this kind of voltage drop problem.

Optionally, the main board is further provided with a central processing unit, a platform controller and at least one flash memory particle connected in sequence.

Wherein, the flash memory particle may include a first flash memory particle and a second flash memory particle, wherein the platform controller is connected to the first flash memory particle, and the baseboard management controller is connected to the second flash memory particle.

Among them, the FW of the BIOS (firmware of the basic input and output system) is stored in the first flash memory particle, which can also be expressed as the FW of the PCH (firmware of the platform controller), wherein the function of the FW of the BIOS is to power on the system Finally, the underlying hardware is initialized, such as PCIE interface and link initialization, etc., and the BIOS shields the upper layer driver and the underlying hardware, so that the upper layer driver does not need to pay too much attention to the implementation details of the underlying hardware; secondly, in the second flash memory particle The FW of the BMC (the firmware of the baseboard management controller) is stored. The FW of the BMC refers to a package of the driver, the OS Kernel (operating system) and the application layer program that the BMC needs to run. The BMC is an embedded operating system. The function is to make the BMC run to perform the functions of the whole system management, such as fan cooling and so on. By using the firmware to complete the protection of the data, the reliability of the whole server is improved.

As for the central processing unit, it may be a CPU, which is the computing and control core of the computer system and the final execution unit for information processing and program operation. Among them, the platform controller (PCH) can mount some low-speed devices and some high-speed devices, and interconnect with the CPU through the DMI bus to control the timing of power-on and power-off, system management and other functions. Report to the OS (operating system operating system) running in the CPU.

Wherein, a computer management control program runs on the CPU, and the computer management control program can also be understood as an operating system, which can be an OS, and the OS can handle some high-level events. For example, the platform controller (PCH) can The event is reported to the OS running on the CPU in the form of a high-level interrupt, and the OS can process the event. It should be noted that maybe because the voltage of the hard disk slot farthest from the power connector on the back panel is or is about to drop out of the normal operating voltage range of the mechanical hard disk, the voltage of some other hard disk slots will also have the same problem. , so this event is the highest-level event and requires priority processing by the OS.

Optionally, a disk array controller is also provided on the motherboard, the central processing unit is connected to the disk array controller through a first link, and the disk array controller is used to convert the first link to is a second link, and is connected to the hard disk in the hard disk slot through the second link.

Wherein, the first link may be a PCIE link, and the second link may be a SAS/SATA (hard disk interface type) link. Usually, the SAS/SATA link is a link commonly used by mechanical hard disks.

In a specific implementation, the central processing unit is connected to the disk array controller through the first link, and the disk array controller is used to convert the first link into the second link, and connect the hard disk in the hard disk slot through the second link Specifically, the central processing unit is connected to the disk array controller through a PCIE link, and the disk array controller can convert the PCIE link into a SAS/SATA link, and then connect to the hard disk in the hard disk slot through the SAS/SATA link .

Optionally, a power connector is also provided on the backplane, and the power connector supplies power to the hard disk through a resettable fuse.

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present invention, an example is used to illustrate the following:

Referring to Figure 2, it shows the second schematic diagram of a power supply architecture provided in the embodiment of the present invention; as shown in Figure 2, compared with the traditional design scheme, in the power supply architecture mentioned in the present invention, the new parts are as follows: Assuming that the slot Slotn (hard disk slot n) in Figure 2 is the farthest away from the resettable fuse, the voltage drop in the slot Slotn is also the largest, and the new power architecture only needs to place a voltage monitoring chip next to the slot for Slotn The voltage of the slot is monitored. As can be seen from Figure 2, the power supply architecture includes a motherboard and a backplane. The motherboard includes a central processing unit, a platform controller, a baseboard management controller, a voltage regulator chip, a disk array controller, a voltage regulator chip and connectors, and the backplane includes multiple hard disks. The mechanical hard disk is inserted into the hard disk slot. In addition, the backplane also includes power connectors and connectors. Specifically, the voltage monitoring chip can be connected to the connector on the backplane through an I2C link, and further connected to the upstream The baseboard management controller chip on the motherboard, at the same time, the voltage monitoring chip can send a hardware init (interrupt) signal, connect the interrupt signal to the connector on the backplane, connect to the motherboard connector through a cable (cable), and then connect to the The baseboard management controller chip on the motherboard, the central processing unit and the platform controller are interconnected through the DMI link, the PCH is interconnected with the first flash memory particle through the SPI link, and the baseboard management controller is also connected with the second flash memory particle through the SPI link Interconnection, the central processing unit is interconnected with the disk array controller through the PCIE link, the disk array controller can be used to convert the PCIE link into a SAS/SATA link, and then connect to the connection on the motherboard through the SAS/SATA link Then connect to the connector on the backplane (Backplane) through the cable (cable), and finally connect to the mechanical hard disk on the backplane; the voltage regulation chip (VR Chip) on the motherboard can output P12V power to connect to the motherboard connector, and then connected to the recoverable fuse (eFuse) on the backplane through a cable, the fuse can convert the P12V power supply to the P12V and P5V power supply required by the mechanical hard disk inserted in the slot on the backplane; at the same time, the substrate The management controller and the platform controller can be interconnected through the IPMI (Intelligent Platform Management Interface Intelligent Platform Management Interface) link, and the baseboard management controller is connected to the connector on the motherboard through the I2C link, and then connected to the The fuse on the backplane monitors the voltage and current of the power supply of the main circuit on the backplane.

As for the voltage regulating chip, its main function is to convert a certain input voltage into an output voltage. For example, the voltage regulating chip converts P12V into P3V3.

In an embodiment of the present invention, the power supply architecture includes a voltage monitoring chip arranged on the backplane, the voltage monitoring chip is connected to a baseboard management controller arranged on the motherboard, and the voltage monitoring chip is used to monitor the voltage of at least one hard disk slot on the backplane. Voltage. In the embodiment of the present invention, the voltage of the hard disk slots on the backplane can be monitored in real time through the voltage monitoring chip on the backplane, which can effectively reduce the failure rate of disk failure in the storage system and effectively protect user data. The reliability of the whole server can be greatly improved, and at the same time, the architecture mentioned in the embodiment of the present invention is simple, easy to implement, high in realizability, and low in cost.

In addition, the voltage monitoring chip is a chip set next to the hard disk slot farthest from the resettable fuse. Since the distance from the resettable fuse is the farthest, the voltage distributed or generated by the hard disk slot farthest The current will be relatively small, that is, the operating voltage of the mechanical hard disk on the hard disk slot farthest from the recoverable fuse may be lower than the preset voltage threshold set by the voltage monitoring chip, and the voltage drop generated by the hard disk slot will be The biggest, therefore, when the voltage monitoring chip detects that the operating voltage of the mechanical hard disk is lower than the preset voltage threshold set by the voltage monitoring chip, other hard disk slots will also have this kind of voltage drop problem, so there is no need to pass the voltage The monitoring chip monitors the voltage of each hard disk slot, which can quickly find problems and save the time of finding problems.

Referring to FIG. 3 , it shows a flow chart of the steps of a power monitoring method provided in an embodiment of the present invention, which may specifically include the following steps:

Step 301, monitor the voltage of the hard disk slot through the voltage monitoring chip;

For the voltage monitoring chip, it can be an ADC (Analog-to-digital converter), which can be used to monitor the voltage of the hard disk slot.

Wherein, a mechanical hard disk can be inserted into the hard disk slot, and the mechanical hard disk is a hard disk inserted into the hard disk slot on the backplane, which can be used for data interaction with the disk array controller.

As for the voltage of the hard disk slot, it can be understood as the voltage of the mechanical hard disk on the hard disk slot when it is working normally. For example, under normal circumstances, the voltage of the mechanical hard disk can be 12V or higher than 12V (such as 12.1V or 12.2V), it can be understood that those skilled in the art can adjust the voltage value for the normal operation of the mechanical hard disk according to the actual situation, which is not limited in the embodiment of the present invention.

In a specific implementation, the voltage of the hard disk slot can be monitored through a voltage monitoring chip.

Step 302, judge through the baseboard management controller whether to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller;

As for the interactive process, it is a process of data interaction between the hard disk in the hard disk slot and the disk array controller.

In a specific implementation, the baseboard management controller may determine whether to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller.

In step 303, the central processing unit issues an instruction to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller.

As for the central processing unit, it may be a CPU, which is the computing and control core of the computer system and the final execution unit for information processing and program operation. Among them, the platform controller (PCH) can mount some low-speed devices and some high-speed devices, and interconnect with the CPU through the DMI bus to control the timing of power-on and power-off, system management and other functions. Report to the OS running on the CPU.

A computer management control program runs on the CPU, wherein the computer management control program can also be understood as an operating system, which can be an OS, and the OS can handle some high-level events. For example, the platform controller can process events in high-level The level interrupt is reported to the OS running on the CPU, and the OS can process the event. It should be noted that maybe because the voltage of the hard disk slot farthest from the power connector on the back panel is or is about to drop out of the normal operating voltage range of the mechanical hard disk, the voltage of some other hard disk slots will also have the same problem. , so this event is the highest-level event and requires priority processing by the OS.

In the embodiment of the present invention, the voltage of the hard disk slot is monitored by the voltage monitoring chip, the baseboard management controller judges whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller, and the interrupt hard disk slot is issued by the central processing unit. Instructions for the interaction process of the hard disk and disk array controller. In the embodiment of the present invention, the voltage of the hard disk slot is monitored by the voltage monitoring chip, and the baseboard management controller judges whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller, and the interrupt hard disk is issued by the central processing unit. The instruction of the interactive process between the hard disk in the slot and the disk array controller can quickly interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller, effectively reducing the failure of the storage system due to the voltage drop during the data interaction process. The problem of increased data rate can be effectively protected, and the reliability of the whole server can be further improved. At the same time, the architecture mentioned in the embodiment of the present invention is simple, easy to implement, high in realizability, and low in cost.

In an optional embodiment, after the step of monitoring the voltage of the hard disk slot through the voltage monitoring chip, the method further includes:

When the voltage monitoring chip monitors that the voltage of the hard disk slot is lower than a preset voltage threshold, an interrupt signal is sent to the baseboard management controller through the voltage monitoring chip.

As for the preset voltage threshold, it can be understood as the preset voltage threshold set by the voltage monitoring chip. Under normal circumstances, when the voltage monitoring chip sets the preset voltage threshold, it is usually set slightly higher than the mechanical hard disk in normal operation. The voltage at this time, for example, can be set to be slightly higher than P12V and P5V. It should be noted that the preset voltage threshold set by the voltage monitoring chip is usually set slightly higher than the voltage of the mechanical hard disk during normal operation. After setting the voltage threshold, the voltages of P12V and P5V in the hard disk slot or slot farthest from the fuse are temporarily still within the voltage range for the mechanical hard disk to work normally. The voltage of the remote hard disk slot will drop out of the normal working voltage range of the mechanical hard disk, and the voltage threshold set by the voltage monitoring chip is slightly higher than the normal working voltage of the mechanical hard disk. During the fast interaction of data, the voltage drops rapidly. During this period, the firmware of the baseboard management controller and the platform controller need to do some operations to protect the data integrity.

In the specific implementation, when there is a data burst or large data interaction between the disk array controller and the mechanical hard disk, there will definitely be a voltage drop as described above, that is, the voltage of the mechanical hard disk will drop rapidly. However, because the preset voltage threshold of the voltage monitoring chip is slightly higher, before the voltage of the mechanical hard disk drops below the normal working voltage, the voltage monitoring chip sends an interrupt signal to the baseboard management controller, and then the baseboard management control The controller and the platform controller combine with the disk array controller to protect the data to a certain extent.

In one example, assume that the minimum voltage for the normal operation of the mechanical hard disk is 11.4V, and data will be lost when it is lower than 11.4V, and then the normal working voltage of the mechanical hard disk is 12V or slightly higher than 12V (such as 12.2V), etc., assuming Set the preset voltage threshold of the voltage monitoring chip (ADC) to 11.6V. When there is fast interaction of large data between the mechanical hard disk and the Raid controller, the voltage of the mechanical hard disk will drop from 12V or 12.2V to 11.6V At V, the ADC will send an interrupt signal to the BMC, and then the voltage of the mechanical hard disk will continue to drop from 11.6V, but before it drops to 11.4V, the data has been protected.

Among them, the impedance of the copper skin between the power connector on the backplane and the backplane is fixed. When a sudden large current passes through, a voltage drop will occur. For the voltage drop, it is a voltage In the case of rapid decline, when there is a burst of burst (burst) large amounts of data read and write, the mechanical hard disk needs a lot of current, which will cause a voltage drop. It should be noted that during normal data exchange or non-burst data, there is usually no voltage drop.

It should be noted that the voltage monitoring chip is usually set next to the hard disk slot farthest from the fuse. Since the distance from the fuse is the farthest, the voltage distributed by the hard disk slot farthest or The generated current will be relatively small, so the operating voltage of the mechanical hard disk on the hard disk slot farthest from the fuse may be lower than the preset voltage threshold set by the voltage monitoring chip, so the voltage drop generated by the hard disk slot will be Most importantly, when the voltage monitoring chip detects that the operating voltage of the mechanical hard disk is lower than the preset voltage threshold set by the voltage monitoring chip, other hard disk slots will also have such voltage drop problems.

Wherein, for the interrupt signal, it may be an interrupt sent by the voltage monitoring chip to the baseboard management controller when the voltage monitoring chip detects that the operating voltage of the mechanical hard disk on the hard disk slot is lower than the preset voltage threshold set by the voltage monitoring chip. The data exchange signal between the mechanical hard disk and the disk array controller.

Optionally, the baseboard management controller is provided with firmware for the baseboard management controller, and the method further includes:

When the baseboard management controller runs the firmware of the baseboard management controller, the firmware monitors whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller.

Among them, the firmware of the baseboard management controller refers to a package of drivers, operating systems and application layer programs for the baseboard management controller to run. The baseboard management controller is an embedded operating system whose main function is to enable the baseboard management controller to It runs to manage the whole system, such as fan cooling; in the embodiment of the present invention, the firmware of the baseboard management controller is used to monitor whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller.

In a specific implementation, when the baseboard management controller runs the firmware of the baseboard management controller, the firmware monitors whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller.

In the embodiment of the present invention, when the voltage of the hard disk slot monitored by the voltage monitoring chip is lower than a preset voltage threshold, an interrupt signal is sent to the baseboard management controller through the voltage monitoring chip.

Optionally, the step of judging whether to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller through the baseboard management controller includes:

Sending a voltage request to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and using the voltage of the hard disk slot obtained by the baseboard management controller as a verification voltage;

judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage, so as to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller;

When the interrupt signal is not a false positive, it is determined to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller.

Wherein, the voltage request is a request sent by the baseboard management controller to the voltage monitoring chip. The request is used to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, that is, the voltage of the hard disk in the hard disk slot. Further, the baseboard management The voltage of the hard disk slot obtained by the controller is used as the verification voltage; wherein, the verification voltage is used to judge whether the interrupt signal sent by the voltage monitoring chip is a false positive to judge whether to interrupt the interaction between the hard disk in the hard disk slot and the disk array controller process.

Optionally, if the verification voltage is less than a preset voltage threshold, it is determined that the interruption signal is not a false alarm.

As for the preset voltage threshold, it can be understood as the preset voltage threshold set by the voltage monitoring chip. Under normal circumstances, when the voltage monitoring chip sets the preset voltage threshold, it is usually set slightly higher than the mechanical hard disk in normal operation. The voltage at this time, for example, can be set to be slightly higher than P12V and P5V. It should be noted that the preset voltage threshold set by the voltage monitoring chip is usually set slightly higher than the voltage of the mechanical hard disk during normal operation. After setting the voltage threshold, the voltages of P12V and P5V in the hard disk slot or slot farthest from the fuse are temporarily still within the voltage range for the mechanical hard disk to work normally. The voltage of the remote hard disk slot will drop out of the normal working voltage range of the mechanical hard disk, and the voltage threshold set by the voltage monitoring chip is slightly higher than the normal working voltage of the mechanical hard disk. During the fast interaction of data, the voltage drops rapidly. During this period, the firmware of the baseboard management controller and the platform controller need to do some operations to protect the data integrity.

In the specific implementation, when there is a data burst or large data interaction between the disk array controller and the mechanical hard disk, there will definitely be a voltage drop as described above, that is, the voltage of the mechanical hard disk will drop rapidly. However, because the preset voltage threshold of the voltage monitoring chip is slightly higher, before the voltage of the mechanical hard disk drops below the normal working voltage, the voltage monitoring chip sends an interrupt signal to the baseboard management controller, and then the baseboard management control The controller and the platform controller combine with the disk array controller to protect the data to a certain extent.

In one example, assume that the minimum voltage for the normal operation of the mechanical hard disk is 11.4V, and data will be lost when it is lower than 11.4V, and then the normal working voltage of the mechanical hard disk is 12V or slightly higher than 12V (such as 12.2V), etc., assuming Set the preset voltage threshold of the voltage monitoring chip (ADC) to 11.6V. When there is fast interaction of large data between the mechanical hard disk and the Raid controller, the voltage of the mechanical hard disk will drop from 12V or 12.2V to 11.6V At V, the ADC will send an interrupt signal to the BMC, and then the voltage of the mechanical hard disk will continue to drop from 11.6V, but before it drops to 11.4V, the data has been protected.

Among them, the impedance of the copper skin between the power connector on the backplane and the backplane is fixed. When a sudden large current passes through, a voltage drop will occur. For the voltage drop, it is a voltage In the case of rapid decline, when there is a burst of burst (burst) large amounts of data read and write, the mechanical hard disk needs a lot of current, which will cause a voltage drop. It should be noted that during normal data exchange or non-burst data, there is usually no voltage drop.

It should be noted that the voltage monitoring chip is usually set next to the hard disk slot farthest from the fuse. Since the distance from the fuse is the farthest, the voltage distributed by the hard disk slot farthest or The generated current will be relatively small, so the operating voltage of the mechanical hard disk on the hard disk slot farthest from the fuse may be lower than the preset voltage threshold set by the voltage monitoring chip, so the voltage drop generated by the hard disk slot will be Most importantly, when the voltage monitoring chip detects that the operating voltage of the mechanical hard disk is lower than the preset voltage threshold set by the voltage monitoring chip, other hard disk slots will also have such voltage drop problems.

Optionally, after the step of determining to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller when the interrupt signal is not a false positive, the method further includes:

The baseboard management controller sends an interrupt mode corresponding to the interrupt signal to the platform controller; wherein the interrupt mode is a mode of interrupting the interactive process between the hard disk in the hard disk slot and the disk array controller;

When the platform controller receives the interrupt mode, the platform controller reports the interrupt mode to the central processing unit.

For the interrupt mode, it is a way to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller; the level of the interrupt mode can be a high-level interrupt mode, and the high-level interrupt mode can be understood as setting the interrupted event as a priority The highest level, so that the event can be executed first.

Optionally, a priority for the interrupt signal is set in firmware of the baseboard management controller; when the baseboard management controller receives the interrupt signal, the interrupt signal is processed according to the priority deal with.

As for the priority, it can be the highest level of the interrupt method, and the high-level interrupt method can be understood as setting the interrupt event as the highest priority, so that the event can be executed preferentially; for example, suppose there is a process When it needs to be executed, this process needs to be queued, that is, to arrange which process is sent to the core of the central processing unit for execution first according to a certain algorithm (such as the length of waiting time), but when a certain process is set with a priority When it is relatively high, such as the events that need to be interrupted mentioned in the embodiment of the present invention, they will be executed with priority and do not need to be queued for execution.

In a specific implementation, the priority for the interrupt signal is set in the firmware of the baseboard management controller, and when the baseboard management controller receives the interrupt signal, it processes the interrupt signal according to the priority.

In one example, when the baseboard management controller receives the interrupt signal sent by the voltage monitoring chip, the baseboard management controller will continuously send a voltage request to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, namely The baseboard management controller will perform continuous sampling. Assuming that the voltage of the hard disk slots sampled several times (for example, 20 times) is lower than the voltage threshold set by the voltage monitoring chip, the interrupt signal is not a false alarm, and it can be determined that Interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller, and then send the corresponding interrupt mode to the platform controller through the baseboard management controller. The processor reports the interrupt mode; if the baseboard management controller samples 1 voltage that is lower than the voltage threshold set by the voltage monitoring chip, and the other 19 times are not lower than the voltage threshold set by the voltage monitoring chip, it is a false alarm. The management controller does not need to send an interrupt mode corresponding to the interrupt signal to the platform controller, that is, the interactive process between the hard disk in the hard disk slot and the disk array controller does not need to be interrupted. Regarding the method for judging whether the interrupt signal is a false alarm, it can be understood that there is a filtering mechanism or a sampling mechanism. Those skilled in the art may adjust the sampling times, which is not limited in this embodiment of the present invention.

Optionally, if the interrupt signal is a false positive, re-execute the above-mentioned step of monitoring whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware.

Optionally, the step of sending instructions to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller through the central processing unit includes:

When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller so that the disk array controller interrupts the operation of the hard disk slot. Interaction process between hard disk and disk array controller.

Among them, the interrupt command is an interrupt command issued by the OS (operating system) running on the central processing unit to the disk array controller, which requires the disk array controller to immediately stop data interaction with all mechanical hard disks on the backplane. Among them, the data interaction can be mainly understood as the data interaction between the disk array controller on the motherboard and all the mechanical hard disks on the backplane.

In a specific implementation, when the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller to make the disk array controller interrupt the hard disk in the hard disk slot and the disk array controller. interactive process.

In an optional embodiment, the central processing unit is provided with a computer management control program, and the computer management control program is configured to issue an interrupt command corresponding to the interrupt mode to the disk array controller.

In a specific implementation, the central processing unit is provided with a computer management control program, which can also be an operating system OS. When the central processing unit receives the interrupt mode reported by the platform controller, the computer of the central processing unit The management control program OS sends an interrupt command to the disk array controller to stop the data interaction between the disk array controller and the mechanical hard disk.

In the embodiment of the present invention, when the voltage of the hard disk slot monitored by the voltage monitoring chip is lower than the preset voltage threshold, the voltage monitoring chip sends an interrupt signal to the baseboard management controller. When the interrupt signal is interrupted, the baseboard management controller will continuously send voltage requests to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and use the voltage of the hard disk slot obtained by the baseboard management controller as the verification voltage. Then judge whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage to judge whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller. When the interrupt signal is not a false alarm, determine whether to interrupt the hard disk in the hard disk slot The interaction process with the disk array controller, and the interrupt mode corresponding to the interrupt signal sent by the baseboard management controller to the platform controller. When the platform controller receives the interrupt mode, the platform controller reports the interrupt mode to the central processing unit for Interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller. When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller to make the disk array controller interrupt the hard disk. Slots of hard disks and disk array controllers interact with each other. In the embodiment of the present invention, the voltage of the hard disk slot is monitored by the voltage monitoring chip, and the baseboard management controller judges whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller, and the interrupt hard disk is issued by the central processing unit. The instruction of the interactive process between the hard disk in the slot and the disk array controller can quickly interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller, effectively reducing the failure of the storage system due to the voltage drop during the data interaction process. The problem of increased data rate can be effectively protected, and the reliability of the whole server can be further improved. At the same time, the architecture mentioned in the embodiment of the present invention is simple, easy to implement, high in realizability, and low in cost.

In an optional embodiment, the interaction process between the hard disk in the hard disk slot and the disk array controller is data interaction between the disk array controller and the hard disk in the hard disk slot. After the controller issues an instruction step of interrupting the interaction process between the hard disk in the hard disk slot and the disk array controller, the method also includes:

The data of the stop interaction between the disk array controller and the hard disk in the hard disk slot is stored in the disk array controller.

In the specific implementation, the interactive process between the hard disk in the hard disk slot and the disk array controller is that the disk array controller performs data interaction with the hard disk in the hard disk slot, and the hard disk in the hard disk slot and the disk array are interrupted by the central processing unit. After the instruction step of the interaction process of the controller, the data of the stop interaction between the disk array controller and the hard disk in the hard disk slot is stored in the disk array controller, which effectively protects user data, thus avoiding the loss caused by excessive voltage drop. If the disk or data is damaged, the reliability of the whole server can be further improved.

In the embodiment of the present invention, when the voltage of the hard disk slot monitored by the voltage monitoring chip is lower than the preset voltage threshold, the voltage monitoring chip sends an interrupt signal to the baseboard management controller. When the interrupt signal is interrupted, the baseboard management controller will continuously send voltage requests to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and use the voltage of the hard disk slot obtained by the baseboard management controller as the verification voltage. Then judge whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage to judge whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller. When the interrupt signal is not a false alarm, determine whether to interrupt the hard disk in the hard disk slot The interaction process with the disk array controller, and the interrupt mode corresponding to the interrupt signal sent by the baseboard management controller to the platform controller. When the platform controller receives the interrupt mode, the platform controller reports the interrupt mode to the central processing unit for Interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller. When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller to make the disk array controller interrupt the hard disk. Slots of hard disks and disk array controllers interact with each other. In the embodiment of the present invention, the voltage of the hard disk slot is monitored by the voltage monitoring chip, and the baseboard management controller judges whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller, and the interrupt hard disk is issued by the central processing unit. The instruction of the interactive process between the hard disk in the slot and the disk array controller can quickly interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller, effectively reducing the failure of the storage system due to the voltage drop during the data interaction process. rate increase, effectively protect user data, and can further improve the reliability of the server as a whole. At the same time, the architecture mentioned in the embodiment of the present invention is simple, feasible, and low in cost. At the same time, through After the central processing unit issues an instruction step of interrupting the interactive process between the hard disk in the hard disk slot and the disk array controller, the data of the stop interaction between the disk array controller and the hard disk in the hard disk slot is stored in the disk array controller, effectively User data is protected, thereby avoiding disk loss or data damage caused by excessive voltage drop, and can further improve the reliability of the server as a whole.

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present invention, an example is used to illustrate the following:

Referring to FIG. 4 , it shows a schematic flowchart of a power monitoring method provided in an embodiment of the present invention; specifically, the following steps may be included:

Step 1: After the whole system is powered on, the baseboard management controller runs the firmware corresponding to the baseboard management controller. The baseboard management controller will monitor whether the voltage monitoring chip on the backplane has an interrupt signal (init signal) from the hardware, In the firmware of the baseboard management controller, the priority of the interrupt signal of this hardware is set to the highest. When the baseboard management controller receives the interrupt signal from the voltage monitoring chip, it will immediately execute the corresponding action without operating the system. Time slice rotation between processes.

Step 2: When the baseboard management controller detects that the voltage monitoring chip sends an interrupt signal, the baseboard management controller immediately accesses the voltage monitoring chip on the backplane through the I2C link, obtains the voltage value monitored by the voltage monitoring chip, and uses This voltage value is used to determine whether the interrupt signal reported by the voltage monitoring chip is a false alarm. If it is a false alarm, the baseboard management controller ignores the interrupt signal this time, and the software process continues back to the baseboard management controller to listen to whether the voltage monitoring chip sends Effective interrupt signal; when the baseboard management controller judges that the monitored voltage of the mechanical hard disk is indeed lower than the preset voltage threshold of the voltage monitoring chip, then the baseboard management controller will use the IPMI link to interrupt the event at a high level Inform Platform Controller.

Step 3: When the platform controller receives the interrupt mode of the baseboard management controller, the platform controller reports the event to the OS (operating system) running on the central processing unit in a high-level interrupt mode, because the distance from the power supply on the backplane The voltage of the Slotn slot farthest from the connector is or is about to fall out of the normal operating voltage range of the mechanical hard disk, so the voltage of some other Slot (hard disk slot) slots will also have the same problem, so this event is the highest level The event needs to be processed first by the OS; the OS will then issue an instruction to the disk array controller, which requires the disk array controller to immediately stop the data interaction with all the mechanical hard disks on the backplane, and store the interacting data to the disk array controller.

Step 4: The disk array controller executes the operations described in Step 3.

Step five: end.

In the embodiment of the present invention, the voltage of the hard disk slot is monitored by the voltage monitoring chip, the baseboard management controller judges whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller, and the interrupt hard disk slot is issued by the central processing unit. Instructions for the interactive process of the hard disk and the disk array controller, specifically, when the voltage monitoring chip monitors the voltage of the hard disk slot is lower than the preset voltage threshold, the voltage monitoring chip sends an interrupt signal to the baseboard management controller, when the baseboard management When the controller receives the interrupt signal sent by the voltage monitoring chip, the baseboard management controller will continuously send voltage requests to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring The voltage of the slot is used as the verification voltage, and then according to the verification voltage, it is judged whether the interrupt signal sent by the voltage monitoring chip is a false alarm to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller. Time reporting, determine the interactive process of interrupting the hard disk in the hard disk slot and the disk array controller, and send the corresponding interrupt mode to the platform controller through the baseboard management controller, when the platform controller receives the interrupt mode, through the platform control The controller reports the interrupt mode to the central processing unit to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller. When the central processor receives the interrupt mode, the central processing unit sends the interrupt mode corresponding to the disk array controller Command to make the disk array controller interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller. In the embodiment of the present invention, the voltage of the hard disk slot is monitored by the voltage monitoring chip, and the baseboard management controller judges whether to interrupt the interactive process of the hard disk in the hard disk slot and the disk array controller, and the interrupt hard disk is issued by the central processing unit. The instruction of the interactive process between the hard disk in the slot and the disk array controller can quickly interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller, effectively reducing the failure of the storage system due to the voltage drop during the data interaction process. The problem of increased data rate can be effectively protected, and the reliability of the whole server can be further improved. At the same time, the architecture mentioned in the embodiment of the present invention is simple, easy to implement, high in realizability, and low in cost.

At the same time, after the central processing unit issues an instruction step of interrupting the interactive process between the hard disk in the hard disk slot and the disk array controller, the data of stopping the interaction between the disk array controller and the hard disk in the hard disk slot is stored in the disk array controller. The server can effectively protect user data, thereby avoiding the situation of disk loss or data damage caused by excessive voltage drop, and can further improve the reliability of the server as a whole.

It should be noted that, for the method embodiment, for the sake of simple description, it is expressed as a series of action combinations, but those skilled in the art should know that the embodiment of the present invention is not limited by the described action sequence, because According to the embodiment of the present invention, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

Referring to FIG. 5 , it shows a structural block diagram of a power monitoring device provided in an embodiment of the present invention, which may specifically include the following modules:

A voltage monitoring module 501, configured to monitor the voltage of the hard disk slot through a voltage monitoring chip;

A process judging module 502, configured to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller through the baseboard management controller;

The instruction issuing module 503 is configured to issue an instruction to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller through the central processing unit.

In an optional embodiment, the device also includes:

A signal sending module, configured to send an interrupt signal to the baseboard management controller through the voltage monitoring chip when the voltage of the hard disk slot monitored by the voltage monitoring chip is lower than a preset voltage threshold.

In an optional embodiment, the process judging module 502 is specifically configured to:

Sending a voltage request to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and using the voltage of the hard disk slot obtained by the baseboard management controller as a verification voltage;

judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage, so as to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller;

When the interrupt signal is not a false positive, it is determined to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller.

In an optional embodiment, the device also includes:

A non-false alarm determining module, configured to determine that the interruption signal is not a false alarm if the verification voltage is lower than a preset voltage threshold.

In an optional embodiment, the device also includes:

An interrupt mode sending module, configured to send an interrupt mode corresponding to the interrupt signal to the platform controller through the baseboard management controller; wherein, the interrupt mode is to interrupt the interaction between the hard disk in the hard disk slot and the disk array controller the manner of the process;

The interrupt mode reporting module is configured to report the interrupt mode to the central processing unit through the platform controller when the platform controller receives the interrupt mode.

In an optional embodiment, the instruction issuing module 503 is specifically configured to:

When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller so that the disk array controller interrupts the operation of the hard disk slot. Interaction process between hard disk and disk array controller.

In an optional embodiment, the baseboard management controller is provided with firmware for the baseboard management controller, and the device further includes:

A signal monitoring module, configured to monitor whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware when the baseboard management controller is running the firmware of the baseboard management controller.

In an optional embodiment, the device also includes:

a priority setting module, configured to set the priority for the interrupt signal in the firmware of the baseboard management controller;

A signal processing module, configured to process the interrupt signal according to the priority when the baseboard management controller receives the interrupt signal.

In an optional embodiment, the device also includes:

A monitoring and re-executing module, configured to re-execute the step of monitoring whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware if the interrupt signal is a false positive.

In an optional embodiment, the interaction process between the hard disk in the hard disk slot and the disk array controller is data interaction between the disk array controller and the hard disk in the hard disk slot, and the device further includes:

The data storage module is configured to store in the disk array controller the data of the stop interaction between the disk array controller and the hard disk in the hard disk slot.

As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.

In addition, an embodiment of the present invention also provides an electronic device, including: a processor, a memory, and a computer program stored in the memory and operable on the processor. When the computer program is executed by the processor, the above power monitoring method is implemented. Each process of the example, and can achieve the same technical effect, in order to avoid repetition, will not repeat them here.

Fig. 6 is a schematic structural diagram of a computer-readable storage medium provided in an embodiment of the present invention.

The embodiment of the present invention also provides a computer-readable storage medium 601. A computer program is stored on the computer-readable storage medium 601. When the computer program is executed by a processor, each process of the above-mentioned power supply monitoring method embodiment is realized, and the same To avoid repetition, the technical effects will not be repeated here. Wherein, the computer-readable storage medium 601 is, for example, a read-only memory (Read-Only Memory, ROM for short), a random access memory (Random Access Memory, RAM for short), a magnetic disk or an optical disk, and the like.

FIG. 7 is a schematic diagram of a hardware structure of an electronic device implementing various embodiments of the present invention.

The electronic device 700 includes, but is not limited to: a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, a processor 710, and Power supply 711 and other components. Those skilled in the art can understand that the structure of the electronic device shown in Figure 7 does not constitute a limitation on the electronic device, and the electronic device may include more or less components than shown in the illustration, or combine some components, or different components layout. In the embodiment of the present invention, electronic devices include but are not limited to mobile phones, tablet computers, notebook computers, palmtop computers, vehicle-mounted terminals, wearable devices, and pedometers.

It should be understood that, in the embodiment of the present invention, the radio frequency unit 701 can be used to receive and send signals during sending and receiving information or during a call. Specifically, the downlink data from the base station is received and processed by the processor 710; in addition, the Uplink data is sent to the base station. Generally, the radio frequency unit 701 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 701 can also communicate with the network and other devices through a wireless communication system.

The electronic device provides users with wireless broadband Internet access through the network module 702, such as helping users send and receive emails, browse web pages, and access streaming media.

The audio output unit 703 may convert audio data received by the radio frequency unit 701 or the network module 702 or stored in the memory 709 into an audio signal and output as sound. Also, the audio output unit 703 can also provide audio output related to a specific function performed by the electronic device 700 (for example, a call signal reception sound, a message reception sound, etc.). The audio output unit 703 includes a speaker, a buzzer, a receiver, and the like.

The input unit 704 is used to receive audio or video signals. The input unit 704 may include a graphics processor (Graphics Processing Unit, GPU) 7041 and a microphone 7042, and the graphics processor 7041 is used for still pictures or video images obtained by an image capture device (such as a camera) in video capture mode or image capture mode The data is processed. The processed image frames may be displayed on the display unit 706 . The image frames processed by the graphics processor 7041 may be stored in the memory 709 (or other storage medium) or sent via the radio frequency unit 701 or the network module 702 . The microphone 7042 can receive sound, and can process such sound into audio data. The processed audio data can be converted into a format that can be sent to a mobile communication base station via the radio frequency unit 701 for output in the case of a phone call mode.

The electronic device 700 also includes at least one sensor 705, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 7061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 7061 and 7061 when the electronic device 700 moves to the ear. / or backlighting. As a kind of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes), and can detect the magnitude and direction of gravity when it is stationary, and can be used to identify the posture of electronic equipment (such as horizontal and vertical screen switching, related games) , magnetometer posture calibration), vibration recognition-related functions (such as pedometer, tap), etc.; the sensor 705 can also include fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, Infrared sensors, etc., will not be repeated here.

The display unit 706 is used to display information input by the user or information provided to the user. The display unit 706 may include a display panel 7061, and the display panel 7061 may be configured in a liquid crystal display (Liquid Crystal Display, LCD), an organic light-emitting diode (Organic Light-Emitting Diode, OLED) or the like.

The user input unit 707 can be used to receive input numbers or character information, and generate key signal input related to user settings and function control of the electronic device. Specifically, the user input unit 707 includes a touch panel 7071 and other input devices 7072 . The touch panel 7071, also referred to as a touch screen, can collect touch operations of the user on or near it (for example, the user uses any suitable object or accessory such as a finger and a stylus on the touch panel 7071 or near the touch panel 7071). operate). The touch panel 7071 may include two parts, a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, and detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and sends it to the For the processor 710, receive the command sent by the processor 710 and execute it. In addition, the touch panel 7071 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 7071 , the user input unit 707 may also include other input devices 7072 . Specifically, other input devices 7072 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be repeated here.

Furthermore, the touch panel 7071 can be covered on the display panel 7061. When the touch panel 7071 detects a touch operation on or near it, it will be sent to the processor 710 to determine the type of the touch event. The type of event provides a corresponding visual output on the display panel 7061. Although in FIG. 7, the touch panel 7071 and the display panel 7061 are used as two independent components to realize the input and output functions of the electronic device, in some embodiments, the touch panel 7071 and the display panel 7061 can be integrated. The implementation of the input and output functions of the electronic device is not specifically limited here.

The interface unit 708 is an interface for connecting an external device to the electronic device 700 . For example, an external device may include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, audio input/output (I/O) ports, video I/O ports, headphone ports, and more. The interface unit 708 can be used to receive input from an external device (for example, data information, power, etc.) transfer data between devices.

The memory 709 can be used to store software programs as well as various data. The memory 709 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playback function, an image playback function, etc.); Data created by the use of mobile phones (such as audio data, phonebook, etc.), etc. In addition, the memory 709 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.

The processor 710 is the control center of the electronic device, and uses various interfaces and lines to connect various parts of the entire electronic device, by running or executing software programs and/or modules stored in the memory 709, and calling data stored in the memory 709 , to perform various functions of the electronic equipment and process data, so as to monitor the electronic equipment as a whole. The processor 710 may include one or more processing units; preferably, the processor 710 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application programs, etc., and the modem The processor mainly handles wireless communication. It can be understood that the foregoing modem processor may not be integrated into the processor 710 .

The electronic device 700 can also include a power supply 711 (such as a battery) that supplies power to various components. Preferably, the power supply 711 can be logically connected to the processor 710 through a power management system, so as to manage charging, discharging, and power consumption through the power management system. and other functions.

In addition, the electronic device 700 includes some functional modules not shown, which will not be repeated here.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products are stored in a storage medium (such as ROM/RAM, disk, CD-ROM), including several instructions to make a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) execute the methods described in various embodiments of the present invention.

Embodiments of the present invention have been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementations, and the above-mentioned specific implementations are only illustrative, rather than restrictive, and those of ordinary skill in the art will Under the enlightenment of the present invention, without departing from the gist of the present invention and the protection scope of the claims, many forms can also be made, all of which belong to the protection of the present invention.

Those of ordinary skill in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed in the embodiments of the present invention can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media capable of storing program codes such as U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (21)

1. A power architecture, characterized in that, comprising: A voltage monitoring chip arranged on the backboard, the voltage monitoring chip is connected with a baseboard management controller arranged on the main board; the voltage monitoring chip is used for monitoring the voltage of at least one hard disk slot on the backboard. 2. The power supply architecture according to claim 1, wherein the backplane is also provided with a resettable fuse, and the resettable fuse is connected to the voltage regulation chip provided on the motherboard; The voltage sent by the voltage regulating chip to the resettable fuse is converted into the voltage required by the hard disk slot. 3. The power supply architecture according to claim 1 or 2, wherein the voltage monitoring chip is arranged next to the hard disk slot away from the resettable fuse on the backplane. 4 . The power supply architecture according to claim 3 , wherein the main board is further provided with a central processing unit, a platform controller and at least one flash memory particle connected in sequence. 5. The power supply architecture according to claim 4, wherein a disk array controller is also arranged on the motherboard, the central processing unit is connected to the disk array controller through a first link, and the disk The array controller is used to convert the first link into a second link, and connect the hard disk in the hard disk slot through the second link. 6. The power supply architecture according to claim 5, wherein a power connector is further arranged on the backplane, and the power connector supplies power to the hard disk through the resettable fuse. 7. The power supply architecture according to claim 1, wherein the voltage of the hard disk slot is an operating voltage of a hard disk in the hard disk slot. 8. A power monitoring method, characterized in that, comprising the following steps: Monitor the voltage of the hard disk slot through the voltage monitoring chip; judging by the baseboard management controller whether to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller; An instruction to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller is issued by the central processing unit. 9. The power monitoring method according to claim 8, characterized in that, after the step of monitoring the voltage of the hard disk slot through the voltage monitoring chip, the method further comprises: When the voltage monitoring chip monitors that the voltage of the hard disk slot is lower than a preset voltage threshold, an interrupt signal is sent to the baseboard management controller through the voltage monitoring chip. 10. The power monitoring method according to claim 9, wherein the step of judging whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller through the baseboard management controller comprises: Sending a voltage request to the voltage monitoring chip to obtain the voltage of the hard disk slot monitored by the voltage monitoring chip, and using the voltage of the hard disk slot obtained by the baseboard management controller as a verification voltage; judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage, so as to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller; When the interrupt signal is not a false positive, it is determined to interrupt the interaction process between the hard disk in the hard disk slot and the disk array controller. 11. The power monitoring method according to claim 10, wherein the step of judging whether the interrupt signal sent by the voltage monitoring chip is a false alarm according to the verification voltage comprises: If the verification voltage is less than a preset voltage threshold, it is determined that the interruption signal is not a false alarm. 12. The power monitoring method according to claim 10, characterized in that, after the step of determining to interrupt the interactive process between the hard disk of the hard disk slot and the disk array controller when the interrupt signal is not a false positive, The method also includes: The baseboard management controller sends an interrupt mode corresponding to the interrupt signal to the platform controller; wherein the interrupt mode is a mode of interrupting the interactive process between the hard disk in the hard disk slot and the disk array controller; When the platform controller receives the interrupt mode, the platform controller reports the interrupt mode to the central processing unit. 13. The power monitoring method according to claim 12, wherein the instruction step of issuing an instruction step of interrupting the interactive process between the hard disk of the hard disk slot and the disk array controller through the central processing unit comprises: When the central processing unit receives the interrupt mode, the central processing unit sends an interrupt command corresponding to the interrupt mode to the disk array controller so that the disk array controller interrupts the operation of the hard disk slot. Interaction process between hard disk and disk array controller. 14. The power monitoring method according to claim 13, wherein a computer management control program is provided on the central processing unit, and the computer management control program is used to send the interrupt to the disk array controller mode corresponding to the interrupt instruction. 15. The power monitoring method according to claim 8, wherein the baseboard management controller is provided with firmware for the baseboard management controller, and the method further comprises: When the baseboard management controller runs the firmware of the baseboard management controller, the firmware monitors whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller. 16. The power monitoring method according to claim 15, further comprising: setting a priority for the interrupt signal in firmware of the baseboard management controller; When the baseboard management controller receives the interrupt signal, it processes the interrupt signal according to the priority. 17. The power monitoring method according to claim 15, further comprising: If the interrupt signal is a false positive, re-execute the step of monitoring whether the voltage monitoring chip sends an interrupt signal to the baseboard management controller through the firmware. 18. The power monitoring method according to claim 8, wherein the interactive process between the hard disk in the hard disk slot and the disk array controller is that the disk array controller and the hard disk in the hard disk slot carry out data Interacting, after the central processing unit issues the instruction step of interrupting the interaction process between the hard disk in the hard disk slot and the disk array controller, the method further includes: The data of the stop interaction between the disk array controller and the hard disk in the hard disk slot is stored in the disk array controller. 19. A power monitoring device, characterized in that it comprises the following modules: The voltage monitoring module is used to monitor the voltage of the hard disk slot through the voltage monitoring chip; A process judging module, configured to judge whether to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller through the baseboard management controller; The instruction sending module is used to send an instruction to interrupt the interactive process between the hard disk in the hard disk slot and the disk array controller through the central processing unit. 20. An electronic device, characterized in that it includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used to store computer programs; The processor is used to implement the power monitoring method according to any one of claims 8-18 when executing the program stored in the memory. 21. A computer-readable storage medium, characterized in that instructions are stored thereon, and when executed by one or more processors, the processors execute the power supply according to any one of claims 8-18. monitoring method.

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