CN116033673A - Circuit board level packaging method and circuit board - Google Patents
Circuit board level packaging method and circuit board Download PDFInfo
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- CN116033673A CN116033673A CN202211732265.1A CN202211732265A CN116033673A CN 116033673 A CN116033673 A CN 116033673A CN 202211732265 A CN202211732265 A CN 202211732265A CN 116033673 A CN116033673 A CN 116033673A
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Abstract
The disclosure provides a circuit board level packaging method and a circuit board, wherein the circuit board level packaging method comprises the following steps: providing a substrate; forming a metal rerouting layer on one side surface of the substrate through a rerouting process, wherein the metal rerouting layer comprises at least one metal connecting pad and a metal wire which is correspondingly and electrically connected with the metal connecting pad, and the at least one metal connecting pad comprises at least one chip circuit contact position corresponding to a chip; and bonding the at least one chip to the corresponding chip line contact position to obtain a circuit board level packaging structure, wherein each chip is electrically connected with the corresponding at least one chip line contact position.
Description
Technical Field
The present disclosure relates to the field of microelectronic packaging technology, and in particular, to a circuit board level packaging method and a circuit board.
Background
With the continuous development of circuit integration technology, electronic products are increasingly developed towards miniaturization, intellectualization, high performance and high reliability.
In the related art, a board-level package generally employs a printed wiring board (Printed Circuit Board, PCB), simply referred to as a printed board, for achieving electrical interconnection between individual elements. The printed circuit board consists of an insulating bottom plate, connecting wires and bonding pads for assembling and welding electronic elements, and has the dual functions of a conductive circuit and the insulating bottom plate.
Disclosure of Invention
The disclosure provides a circuit board level packaging method and a circuit board.
In a first aspect, the present disclosure provides a circuit board level packaging method, the packaging method comprising:
providing a substrate;
forming a metal rerouting layer on one side surface of the substrate through a rerouting process, wherein the metal rerouting layer comprises at least one metal connecting pad and a metal wire which is correspondingly and electrically connected with the metal connecting pad, and the at least one metal connecting pad comprises at least one chip circuit contact position corresponding to a chip;
and bonding the at least one chip to the corresponding chip line contact position to obtain a circuit board level packaging structure, wherein each chip is electrically connected with the corresponding at least one chip line contact position.
In a second aspect, the present disclosure provides a circuit board level packaging method, the packaging method comprising:
providing a circular substrate, wherein the circular substrate comprises a plurality of substrates;
forming a metal re-wiring layer on one side surface of each substrate on the circular substrate through a re-wiring process, wherein the metal re-wiring layer comprises at least one metal connection pad and metal wiring correspondingly and electrically connected with the metal connection pad, and the at least one metal connection pad comprises at least one chip circuit contact position corresponding to a chip;
bonding the at least one chip to a corresponding chip line contact location, each of the chips being electrically connected to the corresponding at least one chip line contact location;
and cutting the circular substrate into a plurality of substrates to obtain a plurality of circuit board level packaging structures.
In a third aspect, the present disclosure provides a circuit board comprising:
a substrate;
a metal re-wiring layer disposed on one side surface of the substrate, the metal re-wiring layer being formed on one side surface of the substrate by a re-wiring process, the metal re-wiring layer including at least one metal connection pad and a metal wiring electrically connected to the metal connection pad, the at least one metal connection pad including a chip wiring contact position corresponding to at least one chip;
at least one chip is arranged on the surface of the metal wiring layer, which is opposite to the substrate, and is bonded to the corresponding chip circuit contact position, and each chip is electrically connected with the corresponding at least one chip circuit contact position.
According to the circuit board level packaging method and the circuit board technical scheme provided by the embodiment of the disclosure, the novel substrate is adopted to replace the traditional PCB, the RDL technology is utilized to carry out board level wiring and form chip line contact positions (I/Opad) on the substrate, and bare chips are connected to the chip line contact positions on the substrate, so that the board level packaging is realized. On the other hand, the design of part of internal circuits of the chip can be replaced by the design of the RDL process, so that the design cost is reduced, the RDL process can support more pins, the RDL process can enable the I/O contact spacing of the chip to be more flexible and the bump area to be larger, and therefore the stress between the substrate and the device is smaller and the element reliability is higher. In addition, in the embodiment of the disclosure, the bare chip is directly connected to the substrate, so that the chip packaging process is saved, the cost is saved, the size of the board card is reduced, the functional density of the chip is improved, the interconnection length is shortened, the transmission rate is improved, and the power consumption is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
fig. 1 is a schematic flow chart of a circuit board level packaging method according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a process for forming a metal redistribution layer;
FIG. 3 is a schematic diagram of a process for bonding at least one chip to corresponding chip wire bond pad locations;
FIG. 4 is a schematic illustration of a process for forming a bonding layer;
FIG. 5 is a schematic diagram of a process for forming a plastic layer;
FIG. 6 is a schematic diagram of a process for forming a protective layer;
fig. 7 is a flowchart illustrating another circuit board level packaging method according to an embodiment of the disclosure;
FIG. 8 is a schematic view of a circular substrate;
fig. 9 is a schematic top view of a circuit board.
Detailed Description
For a better understanding of the technical solutions of the present disclosure, exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the related art, the manufacturing process of the PCB board limits the line width and the line distance, which is usually in millimeter level, and the line distance of the die is in micrometer level, so that pins of the chip need to be rearranged and enlarged to millimeter level through the first level packaging, and then the chip after the first level packaging is assembled on the PCB board, so that not only is the process steps more, but also the size is enlarged by several times or even tens of times. Where first level packaging refers to packaging chips into single chip assemblies (SCMs) and multi-chip assemblies (MCMs) with a package housing.
Therefore, the related art board-in-board packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product, and the chip needs to be subjected to primary packaging, and usually adopts a lead frame, a patch, wire bonding (i.e. wire bonding) and the like, so that the packaging technology has the defects of low efficiency and high cost.
Therefore, the embodiment of the disclosure provides a circuit board level packaging method and a circuit board, which aim to effectively solve at least one of the technical problems in the related art.
Fig. 1 is a flow chart of a circuit board level packaging method according to an embodiment of the disclosure.
An embodiment of the present disclosure provides a circuit board level packaging method, as shown in fig. 1, including:
step S1, providing a substrate.
In embodiments of the present disclosure, the substrate may be made of any suitable material, for example, the substrate material may be a ceramic material, an epoxy glass material, a diamond material, a metal matrix composite material, or the like.
In some embodiments, the substrate is a glass substrate, and the glass substrate has high thermal conductivity, so that better heat dissipation can be achieved, and more complex wiring requirements on higher density welding products can be met; in addition, the flatness of the glass substrate is higher, and the chip (bare chip) is easier to be pasted and aligned. Further, the glass substrate has a coefficient of thermal expansion close to that of the chip, and is less likely to warp.
And S2, forming a metal re-wiring layer on one side surface of the substrate through a re-wiring process, wherein the metal re-wiring layer comprises at least one metal connecting pad and metal wiring correspondingly and electrically connected with the metal connecting pad, and the at least one metal connecting pad comprises at least one chip circuit contact position corresponding to the chip.
In the disclosed embodiments, for circuit board level packaging structures, multiple layers of metal wiring are required to be fabricated to achieve electrical interconnection between components on the circuit board level packaging structure.
Fig. 2 is a schematic view of a process for forming a metal Re-wiring layer, as shown in fig. 2, in step S2, metal Re-wiring is performed by a Re-wiring (Re-distributed layer, RDL) process to form a metal Re-wiring layer 12 on a substrate 11, the metal Re-wiring layer 12 includes a metal wiring 122 formed on the substrate 11, and at least one metal connection pad (pad) 121 formed at a pre-arranged position, wherein the metal wiring 122 is electrically connected with the corresponding metal connection pad 121, the metal wiring 122 is used to connect different metal connection pads 121, and the metal connection pad 121 is used to connect various required devices such as a chip, an interface (connector), etc.
The at least one metal connection pad 121 may include a chip line contact location (I/O pad) 121a formed at a location of a reserved chip for connection with a chip of a desired configuration, and an interface connection structure 121b formed at a location of a reserved interface for connection with an interface of a desired configuration, and the different metal connection pads 121 may be interconnected by metal wiring 122, that is, the different devices may be electrically connected by the metal connection pad 121 and the metal wiring 122. The number of chip circuit contact positions (I/O pads) 121a to be formed is not particularly limited in the embodiments of the present disclosure, and may be specifically determined according to the number of chips to be configured and the pin pads of the chips, and similarly, the number of interface connection structures 121b to be formed is not particularly limited in the embodiments of the present disclosure, and may be specifically determined according to the number of interfaces to be configured.
And step S3, bonding at least one chip to the corresponding chip line contact position to obtain the circuit board level packaging structure, wherein each chip is electrically connected with the corresponding at least one chip line contact position.
Each chip may be a die (die), which refers to a chip obtained by dicing and testing on a wafer and without packaging.
Fig. 3 is a schematic process diagram of bonding at least one chip to a corresponding chip line contact position, as shown in fig. 3, in step S3, at least one chip 13 is bonded to a substrate 11 at a corresponding reserved position, so that a pin pad of the chip 13 is aligned with a chip line contact position (I/O pad) 121a formed in an RDL process, each chip 13 may be electrically connected to at least one chip line contact position 121a at the corresponding position, it should be noted that fig. 3 only illustrates a case where two chips 13 are provided, embodiments of the present disclosure include but are not limited to this case, more chips may be provided as needed, and the number of chip line contact positions (I/O pads) 121a to which the chips are connected in the embodiments of the present disclosure are not particularly limited, and may be determined according to the pin pads of actual chips.
According to the technical scheme of the circuit board level packaging method provided by the embodiment of the disclosure, a novel substrate is adopted to replace a traditional PCB, the RDL technology is utilized to carry out board level wiring on the substrate and form chip line contact positions (I/O pads), and bare chips are connected to the chip line contact positions on the substrate, so that the board level packaging is realized. On the other hand, the design of part of internal circuits of the chip can be replaced by the design of the RDL process, so that the design cost is reduced, the RDL process can support more pins, the RDL process can enable the I/O contact spacing of the chip to be more flexible and the bump area to be larger, and therefore the stress between the substrate and the device is smaller and the element reliability is higher. In addition, in the embodiment of the disclosure, the bare chip is directly connected to the substrate, so that the chip packaging process is saved, the cost is saved, the size of the board card is reduced, the functional density of the chip is improved, the interconnection length is shortened, the transmission rate is improved, and the power consumption is reduced.
In some embodiments, where the substrate is a glass substrate, in order to better bond the metal redistribution layer to the glass substrate, the packaging method may further include, prior to forming the metal redistribution layer: an adhesive layer is formed on one side surface of the substrate. The step of forming a metal re-wiring layer over one side surface of the substrate by a re-wiring process may further include: a metal redistribution layer is formed over a surface of the adhesion layer facing away from the substrate by a redistribution process.
Fig. 4 is a schematic view of a process for forming an adhesive layer, as shown in fig. 4, an adhesive layer 14 is formed on one surface of a substrate 11, and a metal redistribution layer 12 is formed on the surface of the adhesive layer 14 facing away from the substrate 11 through a redistribution process, so that the metal redistribution layer is better adhered to the substrate, and the adhesion between the substrate and the metal redistribution layer is improved.
In some embodiments, the material of the bonding layer may be silicon dioxide, siO 2 . Illustratively, the manufacturing process flow of the adhesive layer may include: depositing a silicon film on a substrate, for example, depositing the silicon film by a Chemical Vapor Deposition (CVD) method, wherein the temperature is controlled to increase so as to promote the conversion of physical adsorption state atoms on the surface of the substrate to chemical adsorption state, and multi-atomic layer chemical adsorption is formed due to the enhanced diffusion, so that the adhesive force of the film is increased along with the increase of the temperature; the deposited silicon film is subjected to an oxidation treatment to form a silicon dioxide layer, i.e., a bonding layer.
In some embodiments, the step of forming the metal redistribution layer may further include: forming a metal layer on one side surface of the substrate; and patterning the metal layer to form a metal rewiring layer.
For example, the preparation process flow of the metal redistribution layer may include: forming a metal seed layer on the substrate by a physical vapor deposition method (Physical Vapor Deposition, PVD), wherein the metal seed layer can cover the surface of the substrate; coating photoresist and patterning photoresist on the metal seed layer; and etching the metal seed layer by a patterning process, removing the photoresist, and electroplating a metal material layer on the etched metal seed layer by adopting an electroplating method, thereby forming a metal rewiring layer. Wherein, the material of the metal seed layer can be titanium ti and/or copper cu metal material, and the material of the metal material layer can be copper cu metal material.
In some embodiments, the step of forming the metal redistribution layer may further include: forming a dry film layer on one side surface of a substrate; forming a trench in the dry film layer; a metal material is deposited in the trench to form a metal redistribution layer.
For example, the preparation process flow of the metal redistribution layer may include: forming a dry film on a substrate, patterning the dry film to form a groove in the dry film, wherein the groove comprises a wiring area and a Pad area, depositing a metal material in the groove, filling the wiring area and the Pad area of the groove with the metal material, removing the dry film and the metal material on the dry film, and retaining the metal material in the wiring area and the Pad area of the groove, thereby forming a metal rewiring layer.
In some embodiments, the step of bonding at least one chip to a corresponding chip wire bond pad location may further comprise: forming a Bump (Bump) on a lead pad of a chip by using a flip chip bonding process; and welding the bump to the corresponding chip circuit joint position of the chip.
In some embodiments, the flip chip bonding (Flip Chip Bonding) process is adopted to connect the chip and the substrate in a manner of forming a Bump (Bump) on a lead pad of the chip, specifically, the Bump (Bump) is attached on the lead pad of the chip, then the top surface of the chip is placed on a corresponding position of the substrate downwards, the substrate passes through a temperature reflow (Temperature Reflow) channel, and the solder ball is melted to complete welding, so that the lead pad of the chip is electrically connected with a corresponding chip line contact position on the substrate.
In some embodiments, when the number of lead pads of the chip is large, the chip lead pads may be rearranged in advance by RDL process at the time of chip manufacture so as to bond with corresponding chip wire bond pad positions on the substrate.
In some embodiments, the at least one metal connection pad further comprises at least one interfacing structure, and the packaging method may further comprise: and connecting the interface which is required to be configured to a corresponding interface connection structure. In some embodiments, the interface of the desired configuration may be connected to the corresponding interfacing structure by means of soldering.
In some embodiments, the packaging method may further include: forming a plastic layer on at least one chip, wherein the plastic layer at least covers the at least one chip; or, locally molding the preset position on any chip.
In some embodiments, the chip is encapsulated after the chip and other devices are connected to the substrate. For example, the plastic packaging material can adopt o-cresol novolac epoxy resin and the like to carry out plastic packaging through a mould pressing resin or a filling and sealing method, so that the connection between the reinforced chip and the substrate is realized, and the chip is protected.
It should be noted that some packaged devices on the substrate may not need to be encapsulated again; the part to be protected on the device can be subjected to local plastic packaging; the product with the external frame of the board card can be not subjected to plastic packaging; for some chips with high heat dissipation requirements, plastic packaging is not required.
In some embodiments, the step of plastic packaging may be performed after the step of interfacing is completed.
Fig. 5 is a schematic view of a process for forming a molding layer, and as shown in fig. 5, a molding layer 15 is formed on at least one chip 13, and the molding layer 15 may cover the surface of the chip 13 and the surface of the metal redistribution layer 12.
In some embodiments, the packaging method may further include: a protective layer is formed on the other side surface of the substrate disposed opposite to the one side surface.
Fig. 6 is a schematic view of a process for forming a protective layer, as shown in fig. 6, in which a protective layer 16 is formed on the other surface of the substrate 11 opposite to the one surface, the protective layer 16 may cover the other surface of the substrate 11, and by the arrangement of the protective layer, the substrate may be protected on one hand, and the toughness of the substrate may be advantageously enhanced on the other hand. The protective layer can be an explosion-proof film or a lining plate made of organic materials.
In some embodiments, the substrate may be removed by laser, and the circuit board level package structure after the substrate is removed may be adhered to a liner made of an organic material.
In some embodiments, where the substrate is a silicon (Si) substrate, in order to better bond the metal redistribution layer to the substrate, the packaging method may further include, prior to forming the metal redistribution layer: a silicon dioxide layer is formed on the oxidized surface of the substrate. The step of forming a metal re-wiring layer over one side surface of the substrate by a re-wiring process may further include: and forming a metal re-wiring layer on the surface of the silicon dioxide layer, which is opposite to the substrate, through an RDL (RDL) process.
Further, in the case where the substrate is a silicon (Si) substrate, the protective layer may be a liner made of an organic material. Firstly, thinning the silicon substrate on the surface of the other side of the substrate, which is opposite to the surface of one side, and adhering a layer of lining board made of organic materials on one thinned side, so that the toughness of the substrate can be enhanced.
Fig. 7 is a flowchart illustrating another circuit board level packaging method according to an embodiment of the disclosure.
An embodiment of the present disclosure provides a circuit board level packaging method, as shown in fig. 7, including:
step S21, providing a circular substrate, wherein the circular substrate comprises a plurality of substrates.
Fig. 8 is a schematic structural diagram of a circular substrate, as shown in fig. 8, the circular substrate is similar to a circular wafer (wafer) structure, and may be integrated with a plurality of substrates, and the circular substrate may also be understood as a motherboard of the plurality of substrates, and the plurality of substrates may be obtained after cutting the circular substrate.
Step S22, for each substrate on the circular substrate, forming a metal redistribution layer on one side surface of the substrate through a redistribution process, where the metal redistribution layer includes at least one metal connection pad and a metal wiring electrically connected to the metal connection pad, and the at least one metal connection pad includes at least one chip line contact position corresponding to the chip.
Step S23, bonding at least one chip to the corresponding chip line contact position, each chip being electrically connected to the corresponding at least one chip line contact position.
And S24, cutting the circular substrate into a plurality of substrates to obtain a plurality of circuit board level packaging structures.
After packaging is completed on each substrate on the circular substrate, cutting is performed to form a plurality of independent circuit board level packaging structures. In some embodiments, after packaging is completed for each substrate on the circular substrate, wire cutting may be performed to reconnect the various interfaces of the desired configuration.
In the embodiments of the present disclosure, the use of a circular substrate may be applicable to semiconductor processing equipment and processes.
The packaging process of each substrate on the circular substrate can be referred to as the packaging process of the foregoing embodiment for a single substrate, which is not described herein.
The disclosed embodiments also provide a circuit board, as shown in fig. 3 to 6, including:
a substrate 11;
a metal re-wiring layer 12 provided on one side surface of the substrate 11, the metal re-wiring layer 12 being formed on one side surface of the substrate 11 by a re-wiring process, the metal re-wiring layer 12 including at least one metal connection pad 121 and a metal wiring 122 electrically connected to the metal connection pad 121, the at least one metal connection pad 121 including a chip wiring contact position 121a corresponding to at least one chip;
at least one chip 13 is provided on a surface of the metal wiring layer 12 facing away from the substrate 11, the at least one chip 13 being bonded to a corresponding chip wiring contact position 121a, each chip 13 being electrically connected to the corresponding at least one chip wiring contact position 121 a.
In some embodiments, the at least one metal connection pad 121 further includes at least one interface connection structure and at least one component connection structure, and the circuit board further includes at least one connector (interface) and at least one electronic component. The connector is electrically connected with the corresponding interface connection structure, and the electronic component is electrically connected with the corresponding component connection structure, wherein the electronic component is a resistor, an inductor or other components, and can also be a radiator, a communication module, a sensor or other functional modules or devices.
For a specific structural description of the circuit board, reference may be made to the description related to the packaging method in the foregoing embodiment, which is not repeated here.
Fig. 9 is a schematic top view of a circuit board, as shown in fig. 9, in practical application, through the circuit board level packaging method of the embodiment of the disclosure, corresponding wirings and connection pads (pads) are formed in a position area reserved on a substrate of each device, and corresponding devices are connected to the connection pads (pads) in the corresponding position area, so that each required device is integrated on the substrate and electrical interconnection between the devices is realized. The various devices can comprise various chips, various interfaces (connectors), various components such as resistors and inductors, various functional modules such as a heat dissipation module, a communication module and a sensor module, and therefore various required chips, interfaces, components and functional modules can be integrated on a substrate, and circuit board level packaging is achieved.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (11)
1. A circuit board level packaging method, comprising:
providing a substrate;
forming a metal rerouting layer on one side surface of the substrate through a rerouting process, wherein the metal rerouting layer comprises at least one metal connecting pad and a metal wire which is correspondingly and electrically connected with the metal connecting pad, and the at least one metal connecting pad comprises at least one chip circuit contact position corresponding to a chip;
and bonding the at least one chip to the corresponding chip line contact position to obtain a circuit board level packaging structure, wherein each chip is electrically connected with the corresponding at least one chip line contact position.
2. The method of claim 1, wherein the substrate is a glass substrate, the method further comprising, prior to forming the metal redistribution layer: forming an adhesive layer on one side surface of the substrate;
the forming a metal re-wiring layer over one side surface of the substrate by a re-wiring process includes:
and forming the metal rerouting layer on the surface of the bonding layer, which is opposite to the substrate, through a rerouting process.
3. The method of claim 1, wherein forming a metal redistribution layer over a side surface of the substrate by a redistribution process comprises:
forming a metal layer on one side surface of the substrate;
and carrying out a patterning process on the metal layer to form the metal rewiring layer.
4. The method of claim 1, wherein forming a metal redistribution layer over a side surface of the substrate by a redistribution process comprises:
forming a dry film layer on one side surface of the substrate;
forming a trench in the dry film layer;
a metal material is deposited in the trench to form the metal redistribution layer.
5. The method of claim 1, wherein bonding the at least one die to a corresponding die line contact location comprises:
forming a bump on a lead pad of the chip by adopting a flip chip bonding process; and
and welding the bump to a chip circuit joint position corresponding to the chip.
6. The method of claim 1, wherein the at least one metal connection pad further comprises at least one interfacing structure, the method further comprising:
and connecting the interface which is required to be configured to the corresponding interface connection structure.
7. The method according to claim 1, wherein the method further comprises:
forming a plastic layer on the at least one chip, wherein the plastic layer at least covers the at least one chip; or, locally molding the preset position on any chip.
8. The method according to claim 1, wherein the method further comprises:
a protective layer is formed on the other side surface of the substrate disposed opposite to the one side surface.
9. A circuit board level packaging method, the method further comprising:
providing a circular substrate, wherein the circular substrate comprises a plurality of substrates;
forming a metal re-wiring layer on one side surface of each substrate on the circular substrate through a re-wiring process, wherein the metal re-wiring layer comprises at least one metal connection pad and metal wiring correspondingly and electrically connected with the metal connection pad, and the at least one metal connection pad comprises at least one chip circuit contact position corresponding to a chip;
bonding the at least one chip to a corresponding chip line contact location, each of the chips being electrically connected to the corresponding at least one chip line contact location;
and cutting the circular substrate into a plurality of substrates to obtain a plurality of circuit board level packaging structures.
10. A circuit board, wherein the circuit board level package structure comprises:
a substrate;
a metal re-wiring layer disposed on one side surface of the substrate, the metal re-wiring layer being formed on one side surface of the substrate by a re-wiring process, the metal re-wiring layer including at least one metal connection pad and a metal wiring electrically connected to the metal connection pad, the at least one metal connection pad including a chip wiring contact position corresponding to at least one chip;
at least one chip is arranged on the surface of the metal wiring layer, which is opposite to the substrate, and is bonded to the corresponding chip circuit contact position, and each chip is electrically connected with the corresponding at least one chip circuit contact position.
11. The circuit board of claim 10, wherein the at least one metal connection pad further comprises at least one interface connection structure and at least one component connection structure, the circuit board further comprising at least one connector and at least one electronic component;
the connector is electrically connected with the corresponding interface connection structure, and the electronic component is electrically connected with the corresponding component connection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211732265.1A CN116033673A (en) | 2022-12-30 | 2022-12-30 | Circuit board level packaging method and circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211732265.1A CN116033673A (en) | 2022-12-30 | 2022-12-30 | Circuit board level packaging method and circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116033673A true CN116033673A (en) | 2023-04-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211732265.1A Pending CN116033673A (en) | 2022-12-30 | 2022-12-30 | Circuit board level packaging method and circuit board |
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| Country | Link |
|---|---|
| CN (1) | CN116033673A (en) |
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- 2022-12-30 CN CN202211732265.1A patent/CN116033673A/en active Pending
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