CN116033539A - Base station GNSS clock synchronization method and system based on EPLD - Google Patents

Abstract

The invention discloses a base station GNSS clock synchronization method and system based on an EPLD, and relates to the technical field of signal synchronization; aiming at the defects of GPS deviation, phase difference oscillation and the like of a GNSS clock on a base station, the GNSS clock synchronization system is improved, an EPLD with lower cost is adopted as a phase discriminator and a frequency divider, a CPU, a DAC and an OCXO chip form a large phase-locked loop, a small phase-locked loop is not nested in the large phase-locked loop, the phase-locked loop oscillation cannot be caused, the PP1S of the EPLD phase discriminator is a single pulse signal of the OCXO PP1S, the single pulse signal is introduced into an SSC synchronous code stream module, the clock deviation caused by external interference is eliminated regularly, the GPS deviation problem is solved, and the GNSS clock synchronization of the base station also combines the long stability characteristic of GNSS and the short stability characteristic of OCXO, so that a stable and reliable clock source is provided for the whole base station equipment.

Description

A kind of base station GNSS clock synchronization method and system based on EPLD

technical field

The invention discloses a method and a system, and relates to the technical field of signal synchronization, in particular to an EPLD-based base station GNSS clock synchronization method and system.

Background technique

In the TDD system, since the uplink and downlink signals of the air interface are at the same frequency, different time slots are used to realize the TDD system. Therefore, the TDD system is a strong self-interference system. If the clocks of different base stations are not synchronized, and the deviation is greater than 1.5us, there will be mutual interference between the base stations. The problem of interference. The way to ensure air interface synchronization is to use the GNSS synchronization solution. However, the existing GNSS clock synchronization system may have defects such as GPS deviation and phase difference oscillation. However, defects such as GPS deviation and phase difference oscillation have become a nightmare for outfield base stations, and the operation and maintenance teams in various places are under great pressure.

Contents of the invention

Aiming at the problems of the prior art, the present invention provides an EPLD-based base station GNSS clock synchronization method and system, which has the characteristics of strong versatility, simple implementation, etc., and has broad application prospects.

The concrete scheme that the present invention proposes is:

The present invention provides a base station GNSS clock synchronization method based on EPLD, which uses a base station GNSS clock synchronization system to perform clock synchronization. The base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization stream timing module.

Described GNSS clock processing module comprises GNSS receiving module, EPLD phase detection module, CPU, dac, OCXO clock source and EPLD frequency division module,

The timing module of the synchronous stream includes PLL, EPLD frequency division module and SCC module,

The GPS satellite signal is received by the GNSS receiving module, and the GPS PP1S signal is output to the EPLD phase detection module, and two 10MHz signals are output through the OCXO clock source, and one 10MHz signal is divided into OCXO PP1S signal by the EPLD frequency division module in the GNSS clock processing module. It is sent to the EPLD phase detection module, and the OCXO PP1S signal and the GPSPP1S signal are subjected to phase detection processing through the EPLD phase detection module to generate a phase lead or lag flag, and calculate the difference between the OCXO PP1S and GPS PP1S, and pass the difference value through the EPLD phase detection module Send it to the CPU, control the DAC to output the corresponding voltage value after processing the difference through the CPU, and adjust the frequency output of the OCXO clock source.

The other 10MHz signal output by the OCXO clock source enters the PLL, and multiple clock signals are output after the PLL is multiplied. One of the clock signals is connected to the EPLD phase detection module as the phase detection clock of the EPLD phase detection module, and the other clock signal is passed through The EPLD frequency division module in the synchronous code stream timing module divides the frequency to obtain a 40ms signal and sends it to the SSC module for timing output of the synchronous code stream. The PP1S signal is sent to the EPLD frequency division module in the synchronous code stream timing module through the EPLD phase detection module. The PP1S signal is a single pulse signal of the OCXO PP1S, which is used to remove the 40ms clock offset caused by external interference by using the PP1S signal as a 40ms timing output synchronous reset signal of the synchronous code stream.

Further, in the described a kind of EPLD-based base station GNSS clock synchronization method, OCXO PP1S signal and GPS PP1S signal are carried out phase identification process by EPLD phase identification module, generate phase lead or lag sign, comprising:

If the phase advance flag is generated, the OCXO PP1S signal is ahead of the GPS PP1S signal, indicating that the operating frequency of the OCXO clock source is higher than 10MHz.

If the phase lag flag is generated, the OCXO PP1S signal lags behind the GPS PP1S signal, indicating that the operating frequency of the OCXO clock source is lower than 10MHz.

Preferably, in the EPLD-based base station GNSS clock synchronization method, the CPU processes the difference and controls the DAC to output a corresponding voltage value to adjust the frequency output of the OCXO clock source, including:

Filter the difference through the CPU, and then control the DAC to output the corresponding voltage value through the SPI write register according to the processed difference, and adjust the frequency output of the OCXO clock source.

Preferably, in the described a kind of base station GNSS clock synchronization method based on EPLD, utilize SMA antenna to receive GPS satellite signal by GNSS receiving module, output GPS PP1S signal, utilize UART interface to carry out initialization configuration to GNSS receiving module by CPU, read relevant Signal.

Preferably, in the EPLD-based base station GNSS clock synchronization method, the PLL is AD9523, which has a two-stage phase-locked loop inside, and outputs a 61.44MHz clock signal for synchronizing code streams and phase detection.

The present invention also provides a base station GNSS clock synchronization system based on EPLD, wherein the base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization stream timing module,

Described GNSS clock processing module comprises GNSS receiving module, EPLD phase detection module, CPU, dac, OCXO clock source and EPLD frequency division module,

The timing module of the synchronous stream includes PLL, EPLD frequency division module and SCC module,

The GNSS receiving module receives GPS satellite signals, outputs GPS PP1S signals to the EPLD phase detection module, and the OCXO clock source outputs two 10MHz signals, of which one 10MHz signal is divided into OCXOPP1S signals by the EPLD frequency division module in the GNSS clock processing module and sent to the EPLD The phase detection module, the EPLD phase detection module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal, generates a phase lead or lag flag, and calculates the difference between the OCXO PP1S and GPS PP1S, and the EPLD phase detection module sends the difference to the CPU, After processing the difference, the CPU controls the DAC to output the corresponding voltage value, and adjusts the frequency output of the OCXO clock source.

The other 10MHz signal output by the OCXO clock source enters the PLL, and the PLL outputs multiple clock signals after frequency multiplication. One of the clock signals is connected to the EPLD phase detection module as the phase detection clock of the EPLD phase detection module, and the other clock signal passes through the synchronization code. The EPLD frequency division module in the stream timing module divides the frequency to obtain a 40ms signal and sends it to the SSC module for synchronous code stream timing output. The EPLD phase detection module sends the PP1S signal to the EPLD frequency division module in the synchronous code stream timing module. The PP1S signal It is the single pulse signal of OCXO PP1S, and the PP1S signal is used as the synchronous reset signal of the 40ms timing output of the synchronous code stream to remove the 40ms clock offset caused by external interference.

Further, the EPLD phase detection module described in the base station GNSS clock synchronization system based on EPLD carries out phase detection processing with the OCXO PP1S signal and the GPS PP1S signal, and generates a phase leading or lagging sign, including:

If the phase advance flag is generated, the OCXO PP1S signal is ahead of the GPS PP1S signal, indicating that the operating frequency of the OCXO clock source is higher than 10MHz.

If the phase lag flag is generated, the OCXO PP1S signal lags behind the GPS PP1S signal, indicating that the operating frequency of the OCXO clock source is lower than 10MHz.

Preferably, the CPU in the EPLD-based base station GNSS clock synchronization system controls the DAC to output a corresponding voltage value after processing the difference, and adjusts the frequency output of the OCXO clock source, including:

Filter the difference through the CPU, and then control the DAC to output the corresponding voltage value through the SPI write register according to the processed difference, and adjust the frequency output of the OCXO clock source.

Preferably, in the described a kind of EPLD-based base station GNSS clock synchronization system, the GNSS receiving module utilizes the SMA antenna to receive the GPS satellite signal, outputs the GPS PP1S signal, and the CPU utilizes the UART interface to initialize the configuration of the GNSS receiving module and read relevant signals.

Preferably, the PLL in the EPLD-based base station GNSS clock synchronization system is AD9523, which has a two-stage phase-locked loop inside and outputs a 61.44MHz clock signal for synchronizing code streams and phase detection.

The benefits of the present invention are:

The present invention provides a base station GNSS clock synchronization method based on EPLD. Aiming at defects such as GPS deviation and phase difference oscillation of the GNSS clock on the base station, the GNSS clock synchronization system is improved, and the low-cost EPLD is used as a phase detector and The frequency divider, CPU, DAC, and OCXO chip form a large phase-locked loop. There is no nested small phase-locked loop in the large phase-locked loop, which will not cause the phase-locked loop to oscillate. The PP1S of the EPLD phase detector is an OCXO The single pulse signal of PP1S is introduced into the SSC synchronous code stream module, which will be synchronized with the PP1S of the GNSS clock processing module every second, and the clock offset caused by external interference is regularly removed, and the problem of GPS deviation is solved. The GNSS clock of this base station Synchronization also combines the long-term stable characteristics of GNSS and the short-term stable characteristics of OCXO, providing a stable and reliable clock source for the entire base station equipment.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic diagram of the system module structure and interaction of the present invention.

Fig. 2 is a block diagram of processing signal detection in the EPLD phase identification module.

FIG. 3 is a schematic diagram of state switching of a clock synchronization system in a base station board.

Detailed ways

The GNSS clock synchronization system may have defects such as GPS deviation and phase difference oscillation. The GPS deviation fault shows that the clock system is in the LOCK state from the BBU side, but the information obtained from the RRU device of the base station is that the IOT is too high. By closing the stations at the center of the interference area one by one, the specific interference station can be located. The performance of phase difference oscillation is that when the clock is in the LOCK state, the DIF value of the phase detector suddenly jumps, such as jumping from "0" to "3" or "4", and then starts to oscillate, and enters the "abnormal" state from the LOCK state. "state.

The invention aims at the problems of GPS deviation, phase difference oscillation and the like in the base station, and provides an EPLD-based base station GNSS clock synchronization method to solve the above problems.

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and implement it, but the examples given are not intended to limit the present invention.

The present invention provides a base station GNSS clock synchronization method based on EPLD, which uses a base station GNSS clock synchronization system to perform clock synchronization. The base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization stream timing module.

Described GNSS clock processing module comprises GNSS receiving module, EPLD phase detection module, CPU, dac, OCXO clock source and EPLD frequency division module,

The timing module of the synchronous stream includes PLL, EPLD frequency division module and SCC module,

The GPS satellite signal is received by the GNSS receiving module, and the GPS PP1S signal is output to the EPLD phase detection module, and two 10MHz signals are output through the OCXO clock source, and one 10MHz signal is divided into OCXO PP1S signal by the EPLD frequency division module in the GNSS clock processing module. It is sent to the EPLD phase detection module, and the OCXO PP1S signal and the GPSPP1S signal are subjected to phase detection processing through the EPLD phase detection module to generate a phase lead or lag flag, and calculate the difference between the OCXO PP1S and GPS PP1S, and pass the difference value through the EPLD phase detection module Send it to the CPU, control the DAC to output the corresponding voltage value after processing the difference through the CPU, and adjust the frequency output of the OCXO clock source.

The other 10MHz signal output by the OCXO clock source enters the PLL, and multiple clock signals are output after the PLL is multiplied. One of the clock signals is connected to the EPLD phase detection module as the phase detection clock of the EPLD phase detection module, and the other clock signal is passed through The EPLD frequency division module in the synchronous code stream timing module divides the frequency to obtain a 40ms signal and sends it to the SSC module for timing output of the synchronous code stream. The PP1S signal is sent to the EPLD frequency division module in the synchronous code stream timing module through the EPLD phase detection module. The PP1S signal is a single pulse signal of the OCXO PP1S, which is used to remove the 40ms clock offset caused by external interference by using the PP1S signal as a 40ms timing output synchronous reset signal of the synchronous code stream.

In a further preferred solution, reference may be made to some embodiments of the method of the present invention, such as the improved base station GNSS clock synchronization system of the method of the present invention including a GNSS clock processing module and a synchronization stream timing module,

Described GNSS clock processing module comprises GNSS receiving module, EPLD phase detection module, CPU, dac, OCXO clock source and EPLD frequency division module,

Described synchronous stream timing module comprises PLL, EPLD frequency division module and SCC module, with reference to Fig. 1,

The GNSS receiving module receives GPS satellite signals through the SMA antenna, outputs GPS PP1S signals, and communicates with the CPU through the UART interface. The CPU initializes the GNSS receiving module through this interface and reads related signals.

The OCXO clock source outputs a high-precision 10MHz signal. After a clock buffer divided into four, it outputs a 10MHz signal to the PLL for synchronizing the stream timing module, and outputs another 10MHz signal to the EPLD frequency division module in the GNSS clock processing module. EPLD The internal frequency division of the frequency division module is divided into 1Hz, that is, OCXO PP1S, as shown in Figure 1.

OCXO PP1S signal and GPS PP1S signal complete the phase detection process inside the EPLD phase detection module, and generate phase lead and lag signs. If OCXO PP1S is ahead of GPS PP1S, it means that the operating frequency of OCXO is higher than 10MHz; if OCXOPP1S lags behind GPS PP1S, it means that OCXO The operating frequency is below 10MHz. You can use the OCXO PP1S Middle signal to reset the leading and lagging status flags, as shown in Figure 2.

After the OCXO PP1S and GPS PP1S complete the phase detection processing inside the EPLD phase detection module, the calculated difference DIF signal enters the CPU, and the CPU performs filtering processing first, and then controls the DAC to output the corresponding voltage value through the SPI write register, according to the lead or lag situation , adjust the frequency output of the OCXO in time.

And a 10MHz signal output by the clock buffer enters the PLL, and the PLL outputs multiple 61.44MHz clock signals after multiplying the frequency of the 10MHz signal. One of the 61.44MHz signals is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector. ;

The other channel 61.44MHz is used for synchronous code stream setting, which gets a 40ms signal through the EPLD frequency division module in the synchronous code stream timing module, and the PP1S of the EPLD phase detection module is the single pulse signal of the OCXO PP1S, which is introduced into the 40ms EPLD frequency division The module is used as the synchronous reset signal of the 40ms counter. In this way, the 40ms timing signal used to generate the synchronous code stream will be synchronized with the PP1S of the OCXO every second, and the 40ms clock offset caused by external interference will be cleared regularly. With this improved synchronization system, it is possible to deal with GPS deviation problems.

Preferably, the PLL in the embodiment of the method of the present invention can be AD9523, which has a two-stage phase-locked loop inside and outputs a 61.44MHz clock signal for synchronizing code stream and phase detection.

The GNSS receiving module can use ublox's LEA-M8T-0GNSS timing module, and the output time pulse frequency is 0.25Hz to 10MHz. The time pulse accuracy is less than 20ns in Clear sky mode, and less than or equal to 500ns in Indoor mode.

EPLD can use LCMXO2280, which is the Mach XO series of LatTlce Company. It has up to 271 IOs, sysMEM embedded block RAM, up to 7.7KB distributed RAM, supports IEEE standard 1149.1 boundary scan, and the working voltage supports 3.3V and 1.8V.

The OXCO clock source can be OC22L5D39-10MHz, the voltage control range is 0-5V, the initial frequency accuracy is 0.1ppm, the frequency temperature stability is less than 3ppb, the power supply voltage frequency stability is less than 1ppb, and the load frequency stability is less than 1ppb.

The CPU can choose X86. The CPU initializes the GNSS module through UART. The CPU receives the signal from the EPLD after phase detection, filters the signal, and controls the output of the DAC chip through the SPI interface. The voltage of the DAC output changes to control the OCXO. Output frequency. The DAC can be DAC8550, and the CPU adjusts its output through the SPI interface.

In the application of the improved base station GNSS clock synchronization system in the method of the present invention, the states of the GNSS receiving module can be divided into STARTUP, WARMUP, FAST, LOCK, HOLDOVER, HOLDOVERTIMEOUT and ABNORMAL. The GNSS receiving module continues to output PP1S, the CPU determines that the clock is available for 5 consecutive times, and the GNSS receiving module enters the FAST state from the STARTUP state. In the FAST state, if the locking condition is met 30 times in a row (plus or minus 10 units), then the GNSS receiving module enters the LOCK state; otherwise, the clock is unavailable, the state stays in FAST, and the EPLD difference is reset when the difference is too large. In the LOCK state, if the clock is unavailable, directly enter the HOLDOVER state; if the continuous clock does not meet the lock condition (plus or minus 30 units) for 30 consecutive times, then enter the ABNORMAL abnormal state from the LOCK state. After entering the HOLDOVER state, if the clock is available 5 times in a row and starts to judge the phase difference, and the lock condition is met 300 times in a row (plus or minus 10 units) and the clock is available, then you can re-enter the LOCK state. If the clock is unavailable for more than 8 hours, it will enter the HOLDOVERTIMEOUT state from the HOLDOVER state; the HOLDOVER factory reset will enter the initial STARTUP state. In the current HOLDOVERTIMEOUT state, if it is judged once every 10s, and the clock is available for 6 consecutive judgments, then the GNSS receiving module enters the WARMUP state. If the current ABNORMAL abnormal state exceeds 10s, it will enter the WARMUP state.

The status of the GNSS receiving module can be known by the CPU at any time through the UART interface. When the GNSS receiving module is locked, it outputs stable PP1S and TOD information. Both the GPS PP1S output and the OCXO PP1S output by PLLAD9523 enter the EPLD, and the phase detection process is carried out in the EPLD. The processed result enters the CPU for filtering processing. After processing, the CPU adjusts the output of the DAC through the SPI interface, and finally the DAC passes the pressure The control pin adjusts the frequency output of the OCXO. That is, EPLD PD, CPU, DAC and OCXO form a large PLL, and the digital PLLAD9523 is not involved in the large PLL. The 61.44MHz output by the digital PLLAD9523 is used for synchronous code stream timing output, and outputs multiple channels of SSC and SCK to the BBU Each baseband board ensures the clock synchronization of the entire base station system.

The method of the present invention aims at the GPS deviation and phase difference oscillation problems of the GNSS clock in the base station, and carries out a scheme design. Through EPLD and CPU software phase detection and filtering, the long-term stability characteristics of GNSS and the short-term stability characteristics of OCXO are combined to provide the entire base station equipment A stable and reliable clock source.

The present invention also provides a base station GNSS clock synchronization system based on EPLD, wherein the base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization stream timing module,

Described GNSS clock processing module comprises GNSS receiving module, EPLD phase detection module, CPU, dac, OCXO clock source and EPLD frequency division module,

The timing module of the synchronous stream includes PLL, EPLD frequency division module and SCC module,

The GNSS receiving module receives GPS satellite signals, outputs GPS PP1S signals to the EPLD phase detection module, and the OCXO clock source outputs two 10MHz signals, of which one 10MHz signal is divided into OCXOPP1S signals by the EPLD frequency division module in the GNSS clock processing module and sent to the EPLD The phase detection module, the EPLD phase detection module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal, generates a phase lead or lag flag, and calculates the difference between the OCXO PP1S and GPS PP1S, and the EPLD phase detection module sends the difference to the CPU, After processing the difference, the CPU controls the DAC to output the corresponding voltage value, and adjusts the frequency output of the OCXO clock source.

The other 10MHz signal output by the OCXO clock source enters the PLL, and the PLL outputs multiple clock signals after frequency multiplication. One of the clock signals is connected to the EPLD phase detection module as the phase detection clock of the EPLD phase detection module, and the other clock signal passes through the synchronization code. The EPLD frequency division module in the stream timing module divides the frequency to obtain a 40ms signal and sends it to the SSC module for synchronous code stream timing output. The EPLD phase detection module sends the PP1S signal to the EPLD frequency division module in the synchronous code stream timing module. The PP1S signal It is the single pulse signal of OCXO PP1S, and the PP1S signal is used as the synchronous reset signal of the 40ms timing output of the synchronous code stream to remove the 40ms clock offset caused by external interference.

The information interaction and execution process among the various modules in the above system are based on the same concept as the method embodiment of the present invention, and the specific content can refer to the description in the method embodiment of the present invention, and will not be repeated here.

Similarly, the system of the present invention has improved the GNSS clock synchronization system for defects such as GPS deviation and phase difference oscillation of the GNSS clock on the base station, and adopted EPLD with lower cost as phase detector and frequency divider, and CPU and DAC , The OCXO chip forms a large phase-locked loop. There is no nested small phase-locked loop in the large phase-locked loop, which will not cause the phase-locked loop to oscillate. The PP1S of the EPLD phase detector is the single pulse signal of the OCXO PP1S. Introduced into the SSC synchronous code stream module, it will be synchronized with the PP1S of the GNSS clock processing module every second, regularly clearing the clock offset caused by external interference, and solving the problem of GPS deviation. The GNSS clock synchronization of this base station also combines the long-term stability of GNSS characteristics and the short-term stable characteristics of OCXO provide a stable and reliable clock source for the entire base station equipment.

It should be noted that not all steps and modules in the above processes and system structures are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structures described in the above embodiments may be physical structures or logical structures, that is, some modules may be realized by the same physical entity, or some modules may be realized by multiple physical entities, or may be realized by multiple Certain components in individual devices are implemented together.

The above-mentioned embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention are all within the protection scope of the present invention. The protection scope of the present invention shall be determined by the claims.

Claims (10)

1. An EPLD-based base station GNSS clock synchronization method is characterized in that a base station GNSS clock synchronization system is utilized for clock synchronization, the base station GNSS clock synchronization system comprises a GNSS clock processing module and a synchronous code stream timing module,

the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,

the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,

receiving GPS satellite signals through a GNSS receiving module, outputting GPS PP1S signals to an EPLD phase discrimination module, outputting two paths of 10MHz signals through an OCXO clock source, dividing one path of 10MHz signals into OCXO PP1S signals through an EPLD frequency division module in the GNSS clock processing module, transmitting the OCXO PP1S signals to the EPLD phase discrimination module, carrying out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals through the EPLD phase discrimination module, generating a phase lead or lag mark, calculating the difference value between the OCXO PP1S and the GPS PP1S, sending the difference value to a CPU through the EPLD phase discrimination module, controlling a DAC to output corresponding voltage values after the difference value is processed through the CPU, adjusting the frequency output of the OCXO clock source,

the other path of 10MHz signal output by the OCXO clock source enters the PLL, after frequency multiplication by the PLL, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module is used for transmitting a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream for clearing 40ms clock offset caused by external interference.

2. The EPLD-based base station GNSS clock synchronization method of claim 1, wherein the phase discrimination processing is performed on the OCXO PP1S signal and the GPS PP1S signal by the EPLD phase discrimination module to generate the phase lead or lag flag, comprising:

if the phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source is operating at a frequency higher than 10MHz,

if the phase lag flag is generated, the OCXO PP1S signal lags the GPS PP1S signal, indicating that the OCXO clock source operating frequency is below 10MHz.

3. The EPLD-based base station GNSS clock synchronization method of claim 1 or 2, wherein the controlling the DAC to output the corresponding voltage value after the CPU processes the difference value, adjusting the frequency output of the OCXO clock source includes:

and filtering the difference value by a CPU, controlling a DAC to output a corresponding voltage value by an SPI write register according to the processed difference value, and adjusting the frequency output of the OCXO clock source.

4. The method for synchronizing GNSS clock of base station based on EPLD as claimed in claim 1, wherein the GNSS receiving module receives GPS satellite signals by using SMA antenna, outputs GPS PP1S signals, and uses UART interface to initialize the GNSS receiving module by CPU to read related signals.

5. The EPLD-based base station GNSS clock synchronization method of claim 1 wherein the PLL is an AD9523 with a 2-stage phase locked loop therein, outputting a 61.44MHz clock signal for synchronization of code streams and phase discrimination.

6. An EPLD-based base station GNSS clock synchronization system is characterized in that the base station GNSS clock synchronization system comprises a GNSS clock processing module and a synchronous code stream timing module,

the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,

the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,

the GNSS receiving module receives GPS satellite signals, outputs GPS PP1S signals to the EPLD phase discrimination module, the OCXO clock source outputs two paths of 10MHz signals, one path of 10MHz signals is divided into OCXO PP1S signals by the EPLD frequency division module in the GNSS clock processing module and is transmitted to the EPLD phase discrimination module, the EPLD phase discrimination module carries out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals to generate a phase lead or lag mark, calculates the difference value between the OCXO PP1S and the GPS PP1S, the EPLD phase discrimination module sends the difference value to a CPU, the CPU processes the difference value and then controls the DAC to output corresponding voltage value, the frequency output of the OCXO clock source is adjusted,

the other path of 10MHz signal output by the OCXO clock source enters the PLL, after the PLL frequency multiplication, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module transmits a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream and is used for eliminating 40ms clock offset caused by external interference.

7. The EPLD-based base station GNSS clock synchronization system of claim 6, wherein said EPLD phase discrimination module performs phase discrimination processing on OCXO PP1S signals and GPS PP1S signals to generate phase lead or lag flags, comprising:

if the phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source is operating at a frequency higher than 10MHz,

if the phase lag flag is generated, the OCXO PP1S signal lags the GPS PP1S signal, indicating that the OCXO clock source operating frequency is below 10MHz.

8. The EPLD-based base station GNSS clock synchronization system of claim 6 or 7, wherein the CPU processes the difference value and then controls the DAC to output a corresponding voltage value, adjusts the frequency output of the OCXO clock source, and includes:

and filtering the difference value by a CPU, controlling a DAC to output a corresponding voltage value by an SPI write register according to the processed difference value, and adjusting the frequency output of the OCXO clock source.

9. The EPLD-based base station GNSS clock synchronization system of claim 6, wherein the GNSS receiving module receives GPS satellite signals using SMA antenna, outputs GPS PP1S signals, and the CPU uses UART interface to perform an initialization configuration of the GNSS receiving module, and reads the relevant signals.

10. The EPLD-based base station GNSS clock synchronization system of claim 6, wherein the PLL is an AD9523 with a 2-stage phase locked loop therein, outputting a 61.44MHz clock signal for synchronization of code streams and phase discrimination.

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