CN116031273A - Wafer and method for manufacturing miniature light-emitting diode chips - Google Patents

Abstract

The application provides a wafer and a method for manufacturing a miniature light-emitting diode chip. The wafer comprises a plurality of test units, and a first test electrode and a second test electrode which are arranged on the periphery of the test units. The test unit comprises a first interconnection line, a second interconnection line and a plurality of micro light emitting diode chips distributed in an array. Each micro light emitting diode chip has a first electrode and a second electrode. The first electrode, the first interconnection line and the first test electrode are electrically connected, and the second electrode, the second interconnection line and the second test electrode are electrically connected. The circumference side of the miniature LED chip is provided with a plurality of cutting channels. The first test electrode and the second test electrode are arranged in the cutting channel. When testing the test unit, all the micro light emitting diode chips in the unit can be tested at the same time, so that the test efficiency is improved. In addition, the voltages applied to each micro light emitting diode chip are the same, so that the test can be performed under the same test condition, thereby improving the accuracy of the test result.

Description

Wafer and method for manufacturing miniature light-emitting diode chips

technical field

The present application relates to the technical field of semiconductors, in particular to a wafer and a method for manufacturing micro light emitting diode chips.

Background technique

Since Micro Light Emitting Diode (Micro LED) has the advantages of self-illumination, high efficiency, high color gamut, and high contrast, Micro LED is called the most potential next-generation display technology after Organic Light Emitting Diode. Typically, after fabrication of tiny LED chips on a wafer, the chips need to be tested for qualification and their electrical characteristics evaluated.

At present, the main test methods include photoluminescence test method and electroluminescence test method. Specifically, the electroluminescence test method adopts a power-on test, that is, the probe is in contact with the electrode of the micro-LED chip to supply power to the chip, so as to test the performance of the chip. However, as the size of the miniature light-emitting diode chip becomes smaller and smaller, the existing probes are easy to pierce the electrodes of the chip, resulting in damage to the chip. In addition, when multiple miniature light-emitting diode chips need to be tested simultaneously, correspondingly multiple probes are required for testing, which not only leads to higher requirements for precise positioning of the probes, but also makes the structure of the wafer testing system more complex.

Contents of the invention

The present application provides a wafer and a method for manufacturing miniature light-emitting diode chips, so as to simultaneously test a plurality of miniature light-emitting diode chips on the wafer, thereby improving the efficiency and accuracy of wafer testing.

In a first aspect, the present application provides a wafer. The wafer includes a plurality of test cells, first test electrodes and second test electrodes. Specifically, the first test electrode and the second test electrode are arranged on the peripheral side of the test unit. The testing unit includes a plurality of miniature LED chips, first interconnection lines and second interconnection lines. Wherein, the plurality of miniature LED chips are distributed in an array. Each miniature LED chip has a first electrode and a second electrode, the first electrode is electrically connected to the first interconnection line, and the second electrode is electrically connected to the second interconnection line. The first interconnection line is electrically connected to the first test electrode, and the second interconnection line is electrically connected to the second test electrode. The peripheral side of each miniature light-emitting diode chip has a plurality of dicing lines, therefore, the peripheral side of the test unit also has a plurality of dicing lines, and the first test electrode and the second test electrode are arranged in the dicing lines.

In the process of wafer testing, for the tested test unit, one probe is in contact with and electrically connected to the first test electrode in the test unit, and the other probe is in contact with and electrically connected to the second test electrode, so that the A plurality of miniature light-emitting diode chips of the test unit are energized at the same time to improve the efficiency of wafer testing. Moreover, the voltage drop between the two electrodes of each micro light emitting diode chip is the same, so testing each micro light emitting diode chip under the same voltage condition can reduce the error of the test result. In addition, the first test electrode and the second test electrode are arranged by using the dicing lines on the peripheral side of the test unit, which does not need to occupy the space of the micro light emitting diode chip, so that the space utilization rate of the wafer can be increased.

Specifically, the layout of the cutting lanes is not limited. For example, the cutting lanes may include a plurality of first cutting lanes extending along the first direction and arranged in parallel. The first test electrode can be set in the first scribe line; or, the second test electrode can be set in the first scribe line; or, the first test electrode and the second test electrode can be set in the first scribe line. The test unit is disposed between the first test electrode and the second test electrode. With this layout method, both the first test electrodes and the second test electrodes extend along the first direction and are arranged in parallel, so that the pattern design on the wafer can be simplified and the wafer manufacturing process can be reduced.

The above-mentioned cutting lanes may also include a plurality of second cutting lanes. These second cutting lines extend along a second direction and are arranged in parallel, and the second direction is perpendicular to the first direction. The first interconnection line and the second interconnection line are disposed on the second dicing line. In this technical solution, the first interconnection line and the second interconnection line utilize the second dicing line between the micro light emitting diodes, without occupying the space of the micro light emitting diodes on the wafer, so as to further improve the space of the wafer utilization rate.

The above-mentioned plurality of test units may include a plurality of first test units and a plurality of second test units arranged alternately along the second direction. In a specific technical solution, adjacent first test units and second test units may share the same first test electrode, or adjacent first test units and second test units may share the same second test electrode . That is to say, a first test electrode or a second test electrode can be arranged in the first cutting line between the adjacent first test unit and the second test unit, so that the space between the test units can be shortened, To increase space utilization on the wafer.

In another technical solution, two first test electrodes or two second test electrodes may be arranged in the first cutting line between adjacent first test units and second test units.

Or, in other technical solutions, a first test electrode and a second test electrode may be arranged in the first cutting line between adjacent first test units and second test units.

In the above technical solution, adjacent first test units and second test units do not share the same test electrode, that is to say, each test unit may correspond to a first test electrode and a second test electrode. When testing a selected test unit, the probes can directly contact the first test electrode and the second test electrode corresponding to the test unit, so that the test unit can be positioned quickly and accurately.

The first test electrode in each dicing line has an integral structure, and the second test electrode in each dicing line has an integral structure, thereby simplifying the pattern design of the wafer and the wafer manufacturing process.

The first test electrode, the second test electrode, the first interconnection line, the second interconnection line, and the first electrode and the second electrode of the micro-LED chip are fabricated on the same layer, so as to simplify the steps of wafer fabrication.

In a second aspect, the present application provides a method for manufacturing micro light emitting diode chips. The method includes:

Preparing wafers on substrate substrates;

Test wafers of tiny LED chips;

removing the first test electrode, the second test electrode, the first interconnection line and the second interconnection line;

The wafer is diced to form multiple individual tiny LED chips.

The wafer of the first aspect is used to manufacture independent miniature light-emitting diode chips. On the one hand, the first test electrode, the second test electrode, the first interconnection line and the second interconnection line for testing do not need to occupy the miniature light-emitting diode chip on the wafer, but use the dicing lines between the micro light-emitting diode chips, thereby improving the space utilization of the wafer; on the other hand, when testing the wafer, the probe of the wafer test system and the first The test electrode and the second test electrode do not need to be in direct contact with the micro light emitting diode chip, thereby preventing the probe from damaging the micro light emitting diode chip.

In addition, when wafer testing is performed, a plurality of miniature light-emitting diode chips in the testing unit can be tested simultaneously, thereby improving testing efficiency. Moreover, since each micro light emitting diode chip is electrically connected to the first test electrode and the second test electrode, the voltage applied to each micro light emitting diode chip in the test unit is equal. Therefore, under the same voltage condition, the optical power and wavelength of the micro-LED chip are relatively uniform, thereby improving the accuracy of test results, and when there is a defective micro-LED chip, the micro-LED chip can be accurately located.

In a specific technical solution, the first test electrode, the second test electrode, the first interconnection line, the second interconnection line, the first electrode and the second electrode are fabricated on the same layer, thereby simplifying the wafer pattern design and wafer pattern design. Circle craft.

Description of drawings

FIG. 1 is a schematic structural view of a wafer;

FIG. 2 is a schematic structural view of a wafer in an embodiment of the present application;

Fig. 3 is a kind of structural representation of the test unit in the embodiment of the present application;

Fig. 4 is another schematic structural diagram of the wafer in the embodiment of the present application;

FIG. 5 is another structural schematic diagram of the wafer in the embodiment of the present application;

Fig. 6 is another schematic structural diagram of the wafer in the embodiment of the present application;

FIG. 7 is another structural schematic diagram of the wafer in the embodiment of the present application;

FIG. 8 is a flowchart of a method for making a miniature light-emitting diode chip in an embodiment of the present application;

FIG. 9 is a schematic diagram of a wafer testing system in an embodiment of the present application.

Reference signs:

01-wafer; 02-miniature light-emitting diode chip;

10-wafer; 11-test unit;

12-the first test electrode; 13-the second test electrode;

14-the first cutting road; 15-the second cutting road;

90-wafer test system; 91-power supply;

92-Probe; 93-Workbench;

94-beam splitter; 95-image collector;

96-Integrating sphere; 97-Spectrometer;

98-power meter; 99-computer;

11a-the first test unit; 11b-the second test unit;

111-miniature light-emitting diode chip; 112-the first interconnection line;

113-the second interconnection line; 114-the first electrode;

115-second electrode; 116-wire;

931-table motion control system; 961-integrating sphere motion control system.

Detailed ways

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a wafer. As shown in FIG. 1 , in the process of manufacturing independent micro-LED chips, firstly, a plurality of micro-LED chips 02 are fabricated on a whole wafer 01 . Each micro LED chip 02 can be any one of red micro LED chip, green micro LED chip or blue micro LED chip. Then, each micro-LED chip 02 is transferred from the wafer 01 to obtain an independent micro-LED chip.

In order to ensure that the chip package finally installed on the circuit board can work normally, after the miniature light-emitting diode chip 02 is fabricated on the wafer 01, a wafer test is usually performed to identify whether each micro-light-emitting diode chip 02 can work normally. And evaluate its electrical characteristics. Through the wafer test, defective products of the chip can be identified, and these defective products can be removed when transferring the micro light-emitting diode chip 02, thereby improving the yield of the chip.

In the process of testing the wafer 01 by using the electroluminescent testing method, each micro light-emitting diode chip 02 on the wafer 01 is tested by a probe. Specifically, each micro LED chip 02 has two electrode terminals. For a micro light emitting diode chip 02, one probe is in contact with an electrode terminal of the micro light emitting diode chip 02, and another probe is in contact with the other electrode terminal of the micro light emitting diode chip 02, and then the two probes The needle energizes the micro light emitting diode chip 02 to make it work, so that the performance of the micro light emitting diode chip 02 can be tested.

However, with the continuous development of semiconductor technology, the size of micro-LED chips is getting smaller and smaller. Likewise, the size of the electrode terminals is getting smaller and smaller. When the probe is in contact with the electrode terminal, the probe is very easy to pierce the electrode terminal, thereby causing damage to the micro light emitting diode chip and reducing the yield of the chip.

In addition, as the size of micro-LED chips decreases, the number of micro-LED chips formed on the same wafer gradually increases. This requires higher positioning accuracy of probes and the ability to test a larger number of chips simultaneously, but existing wafer testing systems are difficult to meet this requirement.

To this end, the present application provides a wafer and a method for manufacturing micro-LED chips, so as to simultaneously test a plurality of micro-LED chips on the wafer, thereby improving the efficiency and accuracy of wafer testing.

It should be noted that, in the embodiments of the present application, the micro light-emitting diode chip refers to a chip fabricated on a wafer and not transferred. After the wafer test is completed, the miniature LED chips are transferred from the wafer to obtain independent miniature LED chips. Wherein, a red micro-LED chip, a green micro-LED chip and a blue micro-LED chip can be combined to form a group of micro-LED chips capable of emitting white light.

FIG. 2 is a schematic structural diagram of a wafer in an embodiment of the present application. As shown in FIG. 2 , the wafer 10 includes a plurality of test units 11 , first test electrodes 12 and second test electrodes 13 , wherein the first test electrodes 12 and the second test electrodes 13 are disposed around the test unit 11 . Specifically, FIG. 3 is a schematic structural diagram of the test unit in the embodiment of the present application. As shown in FIG. 3 , each testing unit 11 includes a plurality of miniature LED chips 111 , first interconnection lines 112 and second interconnection lines 113 . The above-mentioned plurality of miniature LED chips 111 are distributed in an array in the testing unit 11 , for example, may be distributed in a rectangular array, a triangular array, or a concentric circle array, which is not specifically limited in this application. Each micro LED chip 111 has a first electrode 114 and a second electrode 115 . In each test unit 11, one end of the first interconnection line 112 is electrically connected to the first test electrode 12, and the first electrodes 114 of all micro light emitting diode chips 111 are electrically connected to the first interconnection line 112 respectively; One end of the interconnection wire 113 is electrically connected to the second test electrode 13 , and the second electrodes 115 of all the micro LED chips 111 are electrically connected to the second interconnection wire 113 respectively. For example, in one embodiment, a first test unit 11 a and a second test unit 11 b are respectively arranged on two sides of the test unit 11 . The first interconnection line 112 is connected to the first test electrode 12 , and the second interconnection line 113 is connected to the second test electrode 13 . In the process of wafer testing, for the test unit 11 to be tested, one probe of the wafer test system is in contact with the first test electrode 12 on one side of the test unit 11 and is electrically connected, and the other probe is connected to the test unit. 11, the second test electrode 13 on the other side contacts and is electrically connected, so that the first test electrode 12, the first interconnection line 112, the first electrode 114, the second electrode 115, the second interconnection line 113 and the second test The electrodes 13 are electrically connected to test the micro LED chips 111 in the testing unit 11 .

It should be noted that the specific number of micro LED chips 111 in the test unit 11 is not limited, for example, a single test unit 11 may include tens of thousands or hundreds of thousands of micro LED chips 111 . For example, taking a 4-inch wafer 10 as an example, the wafer 10 may include 8 million miniature LED chips 111 , and each test unit 11 may include 100,000 miniature LED chips 111 . Therefore, when performing wafer testing, testing a single testing unit 11 is equivalent to testing tens of thousands or hundreds of thousands of miniature light-emitting diode chips 111 at the same time, which can not only significantly improve the efficiency of wafer testing, but also Reduce the number of probes required and simplify the wafer test system, thereby reducing the cost of wafer test.

In order to facilitate the transfer of the micro LED chips 111 after the wafer test is completed, the positions of the multiple dicing lines are usually designed using the gaps between the micro LED chips 111 . Moreover, due to the existence of dicing lines, all test units 11 on the wafer 10 are independent of each other. As shown in FIG. 2 , in some embodiments of the present application, the cutting line may include a plurality of first cutting lines 14 . The first dicing line 14 extends along the first direction A and is disposed on a peripheral side of the micro LED chip 111 . Alternatively, as shown in FIG. 3 , in some other embodiments of the present application, the cutting lines may include a plurality of first cutting lines 14 and a plurality of second cutting lines 15 . The first cutting line 14 and the second cutting line 15 are arranged on the peripheral side of the micro-LED chip 111, wherein the first cutting line 14 extends along the first direction A, and the second cutting line 15 extends along the second direction B, The first direction A is perpendicular to the second direction B. That is to say, two cutting lines, the first cutting line 14 and the second cutting line 15 , may be provided on the peripheral side of the testing unit 11 .

In the above embodiment, the first test electrode 12 and the second test electrode 13 are disposed on the cutting line around the test unit 11 , and the width may be 20 microns, 30 microns, 50 microns or 80 microns, for example. In this way, the first test electrode 12 and the second test electrode 13 do not need to occupy the position of the micro-LED chip 111 in the test unit 11, so that the occupied area of the micro-LED chip 111 can be increased as much as possible when the wafer 10 is designed. .

Please continue to refer to FIG. 2 , in some embodiments of the present application, a plurality of first cutting lines 14 extending along the first direction A are provided on the peripheral side of the testing unit 11 . The first test electrode 12 may be provided in the first scribe line 14, or the second test electrode 13 may be provided in the first scribe line 14, or the first test electrode 12 and the second test electrode 13 may be provided in the first scribe line 14. electrode 13. In the embodiment of the present application, the testing unit 11 is disposed between the first testing electrode 12 and the second testing electrode 13 . Therefore, when the selected test unit 11 needs to be tested, the probes of the wafer test system are in contact with the adjacent first test electrodes 12 and the second test electrodes 13 of the test unit 11 and are electrically connected, and the probes do not It needs to be in contact with the first electrode 114 and the second electrode 115 of the micro LED chip 111 , so as to prevent the probe from damaging the electrodes of the micro LED chip 111 .

Please continue to refer to FIG. 3, in each test unit 11, the first electrode 114 of each miniature LED chip 111 is connected to the first interconnection line 112 through a wire 116, and the first interconnection line 112 is connected to the first test electrode 12. Connection; the second electrode 115 of each micro LED chip 111 is connected to the second interconnection line 113 through the wire 116 , and the second interconnection line 113 is connected to the second test electrode 13 . When testing the selected test unit 11, each miniature light-emitting diode chip 111 in the test unit 11 is electrically connected with the first test electrode 12 and the second test electrode 13 respectively, and forms a circuit with the wafer test system. circuit. In other words, from a circuit point of view, the plurality of miniature LED chips 111 in the testing unit 11 are connected in parallel with each other. Therefore, the same voltage is applied to each micro-LED chip 111 in the test unit 11 , that is, the voltage drop between the two electrodes of each micro-LED chip 111 is the same. In this way, all micro-LED chips 111 in the test unit 11 can be tested under the same voltage condition, so that the power and wavelength of the micro-LED chips 111 are relatively uniform, so as to avoid errors in test results, thereby reducing the need for micro-LED chips 111. The false positive rate makes the test results more accurate.

As shown in FIG. 3, in a specific embodiment, in order to increase the space utilization rate of the wafer 10, the above-mentioned first interconnection lines 112 and second interconnection lines 113 can also be arranged in the second dicing line 15, the first The width of the first interconnection line 112 and the second interconnection line 113 may be 3 microns, 6 microns, 7 microns or 9 microns, for example. In this way, the space between the micro LED chips 111 can be utilized without reducing the micro LED chips 111 to arrange the first interconnection lines 112 and the second interconnection lines 113 . The first interconnection lines 112 and the second interconnection lines 113 extend along the second direction B and are arranged alternately along the first direction A. Referring to FIG. That is to say, along the first direction A, one side of the micro LED chip 111 is provided with a first interconnection line 112, and the first electrode 114 of the micro LED chip 111 is connected to the first interconnection line 112 through a wire 116; The other side of the micro light emitting diode chip 111 is provided with a second interconnection line 113 , and the second electrode 115 of the micro light emitting diode chip 111 is connected to the second interconnection line 113 through a wire 116 .

Please continue to refer to FIG. 2 , in a specific embodiment, only the first cutting line 14 extending along the first direction A is provided on the peripheral side of the testing unit 11 . In the wafer 10 of this embodiment, the test unit 11 is located between adjacent first dicing lines 14 . The first test electrode 12 can be disposed in the first cutting line 14 on one side of the testing unit 11 , and the second testing electrode 13 can be disposed in the first cutting line 14 on the other side of the testing unit 11 . In other words, the first test electrode 12 and the second test electrode 13 may be disposed on opposite sides of the test unit 11 .

FIG. 4 is a schematic diagram of another structure of a wafer in an embodiment of the present application. As shown in FIG. 4, in another specific embodiment, a plurality of first cutting lines 14 extending along the first direction A and a plurality of first cutting lines 14 extending along the second direction B may be provided on the peripheral side of the testing unit 11. Two cutting lanes 15 . Wherein, the first test electrode 12 can be arranged in the first cutting line 14 , and the second test electrode 13 can be arranged in the second cutting line 15 . In other words, in this embodiment, the first test electrode 12 and the second test electrode 13 may be disposed on adjacent two sides of the test unit 11 . Different layouts of the test unit 11, the first test electrode 12 and the second test electrode 13 will be explained below.

Please continue to refer to 2, the plurality of test units 11 of the wafer 10 may include a plurality of first test units 11 a and a plurality of second test units 11 b arranged alternately along the second direction B. A plurality of first cutting lines 14 extending along the first direction A are disposed on the peripheral side of the testing unit 11 . Specifically, between adjacent first test units 11 a and second test units 11 b , a first test electrode 12 and a second test electrode 13 may be provided on the first cutting line 14 . For example, in a specific embodiment, the order of the first test electrode 12, the first test unit 11a, the second test electrode 13, the first test electrode 12, the second test unit 11b and the second test electrode 13 can be followed along the The second directions B are arranged sequentially. Therefore, each test unit 11 can correspond to one first test electrode 12 and one second test electrode 13 . When testing a selected test unit 11 , the probes can directly contact the first test electrode 12 and the second test electrode 13 corresponding to the test unit 11 , so that the test unit 11 can be positioned more precisely. In addition, the first test electrode 12 and the second test electrode 13 are arranged at a distance from each other to avoid a short circuit between the first test electrode 12 and the second test electrode 13 .

FIG. 5 is a schematic diagram of another structure of the wafer in the embodiment of the present application. As shown in FIG. 5 , the plurality of test units 11 of the wafer 10 may include a plurality of first test units 11 a and a plurality of second test units 11 b arranged alternately along the second direction B. Referring to FIG. A plurality of first cutting lines 14 extending along the first direction A are disposed on the peripheral side of the testing unit 11 . Specifically, between adjacent first test units 11 a and second test units 11 b , the first cutting line 14 may be provided with two first test electrodes 12 or two second test electrodes 13 . That is to say, the adjacent first test unit 11a and the second test unit 11b do not share test electrodes. For example, in a specific embodiment, the first test electrode 12, the first test unit 11a, the second test electrode 13, the second test electrode 13, the second test unit 11b and the first test electrode 12 can be followed in the order The second directions B are arranged sequentially.

FIG. 6 is a schematic diagram of another structure of the wafer in the embodiment of the present application. As shown in FIG. 6 , between adjacent first test units 11 a and second test units 11 b , only one first test electrode 12 may be disposed in the first cutting line 14 . That is to say, the adjacent first testing unit 11 a and the second testing unit 11 b can share the same first testing electrode 12 . Alternatively, a second test electrode 13 may be disposed in the first cutting line 14 , that is, the first test unit 11 a and the second test unit 11 b may share the same second test electrode 13 . It can be understood that, in a specific embodiment, among any two adjacent first cutting lines 14, a first test electrode 12 is arranged in one first cutting line 14, and a first test electrode 12 is arranged in the other first cutting line 14. A second test electrode 13 is provided. With this structural design, adjacent test units 11 can share the same test electrode, so as to reduce the space between the test units 11 , thereby increasing the space utilization on the wafer 10 . Moreover, only one test electrode is provided in one first dicing line 14 , which can reduce the manufacturing cost of the wafer 10 and simplify the manufacturing process of the wafer 10 .

In the embodiment of the present application, the specific shape of the above-mentioned testing unit 11 is not limited, for example, it may be strip, rectangle, circle or irregular shape. As shown in FIG. 5 and FIG. 6 , in some other embodiments, the test unit 11 may be rectangular, and a plurality of test units 11 on the wafer 10 are distributed in an array. FIG. 7 is a schematic diagram of another structure of the wafer in the embodiment of the present application. As shown in FIG. 7 , in some embodiments, the test units 11 may be strip-shaped, and a plurality of test units 11 on the wafer 10 are arranged in parallel.

In the above-mentioned embodiment, the first test electrodes 12 of the test units 11 adjacent along the first direction A may have an integral structure, and the second test electrodes 13 of the test units 11 adjacent along the first direction A may have an integral structure. In other words, the first test electrodes 12 and the second test electrodes 13 are in the shape of strips for ease of fabrication. For example, in a specific embodiment, the wafer 10 includes a first test unit 11 a, a second test unit 11 b, a first test electrode 12 and a second test electrode 13 . The first test unit 11a, the second test unit 11b, the first test electrode 12 and the second test electrode 13 are all strip-shaped, and according to the first test electrode 12, the first test unit 11a, the second test electrode 13, the second The sequence of the test unit 11b and the first test electrode 12 is arranged sequentially along the second direction B.

In the embodiment of the present application, since the first test electrode 12, the second test electrode 13, the first interconnection line 112 and the second interconnection line 113 can use the first electrode 114 and the second The electrodes 115 are made of the same metal material, so the first test electrode 12, the second test electrode 13, the first interconnection 112 and the second interconnection 113 can be made on the same layer as the first electrode 114 and the second electrode 115, to simplify The steps of wafer 10 fabrication.

FIG. 8 is a flow chart of a method for manufacturing a micro LED chip according to an embodiment of the present application. The micro LED chip package is made of the micro LED chip 111 of the above-mentioned wafer 10 . As shown in Figure 8, the method may include:

Step S101 , preparing the wafer of the above-mentioned embodiment on the base substrate.

In this step S101 , the manufactured wafer 10 includes a plurality of test units 11 , first test electrodes 12 and second test electrodes 13 . The testing unit 11 includes a plurality of micro LED chips 111 , a first interconnection 112 and a second interconnection 113 , wherein each micro LED chip 111 has a first electrode 114 and a second electrode 115 . Specifically, the first test electrode 12 , the second test electrode 13 , the first interconnection line 112 and the second interconnection line 113 may also use a metal material different from that of the first electrode 114 and the second electrode 115 . In this case, the micro LED chip 111 can be fabricated first, and then the first interconnection 112 , the second interconnection 113 , the first test electrode 12 and the second test electrode 13 can be fabricated. Alternatively, the first test electrode 12, the second test electrode 13, the first interconnection 112 and the second interconnection 113 can be made of the same metal material as the first electrode 114 and the second electrode 115, so the first test electrode 12 , the second test electrode 13, the first interconnection line 112 and the second interconnection line 113 can be fabricated on the same layer as the first electrode 114 and the second electrode 115, that is, the first test electrode 12, the second test electrode 13, the second An interconnection line 112 , a second interconnection line 113 , a first electrode 114 and a second electrode 115 can be manufactured simultaneously by the same process, thereby simplifying the manufacturing steps.

Step S102 , testing the micro LED chips on the wafer.

A wafer test system is used to test the electrical characteristics of the miniature LED chips 111 . During the test, the probes are directly in contact with the first test electrode 12 and the second test electrode 13 adjacent to the tested test unit 11 and are electrically connected, so that the test unit 11 is energized to determine the condition of the test unit 11. Whether the micro-LED chips 111 are qualified, and evaluate the electrical characteristics of these micro-LED chips 111 .

Step S103, removing the first test electrode, the second test electrode, the first interconnection line and the second interconnection line.

In this step S103, since the first test electrode 12, the second test electrode 13, the first interconnection 112 and the second interconnection 113 are fabricated on the substrate, when the substrate is peeled off, the first test electrode 12, The second test electrode 13, the first interconnection line 112, and the second interconnection line 113 may be removed along with the substrate. Alternatively, the first test electrode 12 , the second test electrode 13 , the first interconnection line 112 and the second interconnection line 113 may be removed by an etching technique, for example, by a chemical method after photolithography. In this way, the first electrode 114 and the second electrode 115 can avoid problems such as detachment from the micro LED chip 111 or disconnection. At the same time, in step S103, the wire 116 between the first electrode 114 and the first interconnection line 112, and the wire 116 between the second electrode 115 and the second interconnection line 113 can also follow the first interconnection line 112 and The second interconnection line 113 is removed together.

Step S104, dicing the wafer to form a plurality of independent miniature LED chips.

After the wafer test is completed, the wafer 10 is diced so that the micro LED chips 111 are transferred from the wafer 10 to obtain independent micro LED chips.

Using the wafer 10 of the above-mentioned embodiment to manufacture independent miniature light-emitting diode chips, on the one hand, the first test electrode 12, the second test electrode 13, the first interconnection line 112 and the second interconnection line 113 for testing are not It is necessary to occupy the space of the micro-LED chips 111 on the wafer 10, but to use the dicing lines between the micro-LED chips 111, thereby improving the space utilization rate of the wafer 10; on the other hand, when testing the wafer 10, The probes of the wafer testing system and the first test electrodes 12 and the second test electrodes 13 do not need to be in direct contact with the micro LED chips 111 , so that the probes can avoid damaging the micro LED chips 111 .

In addition, when wafer testing is performed, multiple micro LED chips 111 in the testing unit 11 can be tested simultaneously, thereby improving testing efficiency. Moreover, since each micro LED chip 111 is electrically connected to the first test electrode 12 and the second test electrode 13 , the voltage applied to each micro LED chip 111 in the test unit 11 is equal. Therefore, under the same voltage condition, the optical power and wavelength of the micro LED chip 111 are relatively uniform, so that the accuracy of the test results can be improved, and when there is a defective micro LED chip 111, the micro LED chip 111 can be accurately positioned Chip 111.

FIG. 9 is a schematic diagram of a wafer testing system in an embodiment of the present application. As shown in FIG. 9 , a wafer test system 90 includes a power supply 91 , probes 92 , workbench 93 , beam splitter 94 , image collector 95 , integrating sphere 96 , spectrometer 97 , power meter 98 and computer 99 . Specifically, the workbench 93 is used to carry the wafer 10 to be tested. In some embodiments, the workbench 93 may be provided with a temperature control system for controlling the temperature of the wafer 10 . In addition, the workbench 93 can also be provided with a workbench motion control system 931, which is used to control the movement of the workbench 93 after the wafer 10 is placed on the workbench 93, so that the light beams emitted by the micro LED chips 111 of the wafer 10 can be into beam splitter 94. The probes 92 are electrically connected to the power source 91 for electrical connection with the first test electrodes 12 and the second test electrodes 13 of the micro LED chips 111 of the wafer 10 .

When the micro LED chip 111 is powered on, the micro LED chip 111 works. Part of the light beam emitted by the micro LED chip 111 can be directed to the image collector 95 after passing through the beam splitter 94, so that technicians can directly observe the micro LED chip 111 that is normally luminous, weakly luminous, or non-luminous through the image collector 95, And collect the total power and wavelength data of all micro-LED chips 111 in the test unit 11 . Afterwards, by analyzing the total power and wavelength data, it is possible to determine the specific location of the micro-LED chip 111 having an optical power problem, and provide data for subsequent screening of the micro-LED chip 111 .

Other light beams emitted by the miniature LED chip 111 pass through the beam splitter 94 and enter the integrating sphere 96 . Integrating sphere 96 analyzes the incoming light beam and can transmit the analyzed parameters to spectrometer 97, power meter 98 and computer 99 for detailed evaluation.

The wafer testing system 90 may also include an integrating sphere motion control system 961 for controlling the movement of the integrating sphere 96 so that it can receive the optical signal emitted by the optical splitter 94 . And, when there is a problem with the overall wavelength in the testing unit 11, the displacement of the integrating sphere 96 can be controlled by the integrating sphere motion control system 961, so that the integrating sphere 96 can accurately scan the wavelength of the miniature LED chip 111 in the testing unit 11, thereby Accurately find out the specific location of the problematic micro-LED chip 111 .

In the above-mentioned embodiment, through the beam splitter 94 , the image collector 95 , the spectrometer 97 and the power meter 98 can be used simultaneously to evaluate the electrical characteristics of the micro LED chip 111 .

The terms used in the above embodiments are only for the purpose of describing specific embodiments, and are not intended to limit the present application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also Expressions such as "one or more" are included unless the context clearly dictates otherwise.

Reference to "one embodiment" or "some embodiments" or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in another embodiment", "in some embodiments", "in other embodiments", "in "In some other embodiment" etc. do not necessarily all refer to the same embodiment, but mean "one or more but not all of the embodiments" unless specifically emphasized otherwise. The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically stated otherwise.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (10)

1. A wafer, characterized in that, comprises a plurality of test units, a first test electrode and a second test electrode, and the first test electrode and the second test electrode are arranged on the peripheral side of the test unit, in: The test unit includes a plurality of miniature light emitting diode chips, a first interconnection line and a second interconnection line, wherein the plurality of miniature light emitting diode chips are distributed in an array, and each of the miniature light emitting diode chips has a first electrode and a second electrode, the first electrode is electrically connected to the first interconnection line, and the second electrode is electrically connected to the second interconnection line; The peripheral side of the miniature light-emitting diode chip has a cutting line, the first test electrode and the second test electrode are arranged in the cutting line, the first interconnection line is electrically connected to the first test electrode, The second interconnection line is electrically connected to the second test electrode. 2. The wafer according to claim 1, wherein the dicing lines comprise a plurality of first dicing lines, the plurality of first dicing lines extend along a first direction and are arranged in parallel, and the first test An electrode and/or the second test electrode is disposed in the first scribe line; The test unit is disposed between the first test electrode and the second test electrode. 3. The wafer according to claim 2, wherein the dicing lines further comprise a plurality of second dicing lines, the plurality of second dicing lines extend along a second direction and are arranged in parallel, the second The direction is perpendicular to the first direction, and the first interconnection line and the second interconnection line are arranged in the second scribe line. 4. The wafer according to claim 2 or 3, wherein the plurality of test units comprises a plurality of first test units and a plurality of second test units arranged alternately along the second direction, the second test units a direction perpendicular to the first direction; One of the first test electrodes or one of the second test electrodes is disposed in the first cutting line between the adjacent first test units and the second test units. 5. The wafer according to claim 2 or 3, wherein the plurality of test units comprises a plurality of first test units and a plurality of second test units arranged alternately along the second direction, the second test units a direction perpendicular to the first direction; Two of the first test electrodes or two of the second test electrodes are disposed in the first cutting line between the adjacent first test units and the second test units. 6. The wafer according to claim 2 or 3, wherein the plurality of test units comprises a plurality of first test units and a plurality of second test units arranged alternately along the second direction, the second test units a direction perpendicular to the first direction; One first test electrode and one second test electrode are disposed in the first cutting line between adjacent first test units and second test units. 7. The wafer according to any one of claims 1 to 6, characterized in that, the first test electrodes in each of the dicing lines are of an integral structure, and the second testing electrodes in each of the dicing lines The test electrode is an integral structure. 8. The wafer according to any one of claims 1 to 7, wherein the first test electrode, the second test electrode, the first interconnect line, the second interconnect wires, and the first electrode and the second electrode are fabricated in the same layer. 9. A method of making a miniature light-emitting diode chip, characterized in that, comprising: Prepare the wafer as described in any one of claims 1 to 8 on the base substrate; testing micro light emitting diode chips of said wafer; removing the first test electrode, the second test electrode, the first interconnection line and the second interconnection line; The wafer is diced to form a plurality of independent miniature light-emitting diode chips. 10. The method according to claim 9, wherein the first test electrode, the second test electrode, the first interconnect line, the second interconnect line, the first electrode It is fabricated on the same layer as the second electrode.

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