CN116030876A - Method, system and equipment for memory control of power management system - Google Patents

Abstract

The invention discloses a method for performing memory control on a power management system, which comprises the following steps: the power supply controller detects whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module sends a secret key based on the peripheral bus request; the power supply controller receives the secret key sent by the equipment management module based on the peripheral bus, and writes the secret key into the static memory through the CPU memory control unit; the static memory performs unlocking processing based on the secret key; and the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory. When the memory control signal is changed, the invention can synchronously control the static memory to finish read-write operation, and prevent the phenomenon of CPU run-out or suspension death in the power failure process of each functional unit.

Description

Method, system and equipment for memory control of power management system

Technical Field

The present invention relates to the field of power technologies, and in particular, to a method, a system, and an apparatus for performing memory control on a power management system.

Background

A System On Chip (SOC) supports a normal running state RUN, a STANDBY state STANDBY and a STOP state STOP, the RUN state is entered after a Chip is Powered On and Reset (POR), all power supplies of the Chip, clocks and functional modules are in a normal working state in the RUN mode, the power supply module keeps supplying power in the STOP mode, a core clock is closed, a CPU in the System on Chip, namely a power management System, STOPs reading and writing flash memory units flash and static memories sram, and other clock sources can be determined whether to be closed or not by System software; in STANDBY mode, the mode that minimizes system-on-chip power consumption. In STANDBY mode, the system on chip turns off the power supply of most digital circuits, only the external wake-up source is reserved, the clock module reserves 128KHz low-speed clock, flash enters the deep power down or power off, and sram enters the memory recall state.

The system on a chip includes: and after receiving the deep sleep operation sent by the CPU, the PMC controls the whole system to be ready to enter a standby state, and needs to enter the CPU, a flash memory unit flash, a static memory sram and the like into a power-down ready state.

At present, a static memory can adopt a key management mode to ensure the read-write control of memory operation, but how to ensure that the memory operation can be safely read-written so that the whole power management system cannot run out becomes important.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, and provides a method, a system and equipment for carrying out memory control on a power management system, wherein when a memory control signal is changed, a static memory can be synchronously controlled to finish read-write operation, and the phenomenon of CPU running or hanging dead in the power failure process of each functional unit is prevented.

Accordingly, the present invention provides a method for performing memory control on a power management system, the method comprising the steps of:

the power supply controller detects whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module sends a secret key based on the peripheral bus request;

the power supply controller receives the secret key sent by the equipment management module based on the peripheral bus, and writes the secret key into the static memory through the CPU memory control unit;

The static memory performs unlocking processing based on the secret key and sends the unlocking feedback instruction to the power supply controller;

and the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory.

The method further comprises the steps of:

the power supply controller detects whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus;

the power supply controller receives a reset instruction sent by the equipment management module based on the peripheral bus and stops writing the secret key into the static memory;

and when the static memory recognizes that the key writing state disappears, the CPU memory control unit is forbidden to read and write data from the static memory.

The unlocking processing of the static memory based on the secret key comprises the following steps:

and when the static memory recognizes that the secret key is written, analyzing whether the safety data in the static register is consistent with the secret key data, and if the safety data is consistent with the secret key data, unlocking the static memory.

The power supply controller controlling the CPU memory control unit to perform read-write operation on the static memory comprises the following steps:

when the power management system enters a standby state from a normal operation state, the power controller controls the CPU memory control unit to read an operation instruction from the CPU and store the operation instruction into the static memory;

when the power management system enters a normal running state from a standby state, the power controller controls the CPU memory control unit to reload running instructions from the static memory to write into the CPU.

The method further comprises the steps of:

after receiving the deep sleep instruction, the PMC generates a holdsleep signal of the CPU hold non-execution instruction and sends the holdsleep signal to the CPU;

the internal low speed SIRC clock timing is controlled such that the holdsleep signal on the CPU is active low so that the power management system is ready to enter a standby state.

The method further comprises the steps of:

the power supply controller detects whether the holdsleep signal changes from an invalid state to an valid state;

when the power supply controller detects that the holdsleep signal is changed from the inactive state to the active state, the memory control signal acting on the static memory is triggered to be changed from the inactive state to the active state.

The method further comprises the steps of:

the PMC identifies that a wake-up source wakeup signal appears;

the PMC outputs an isolation control signal for the static memory.

Correspondingly, the invention also provides a power management system, which comprises:

the power supply controller is used for detecting whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module is requested to send a secret key based on the peripheral bus; receiving a secret key sent by the equipment management module based on a peripheral bus, and writing the secret key into the static memory through a CPU memory control unit; controlling a CPU memory control unit to perform read-write operation on the static memory;

the static memory is used for carrying out unlocking processing based on the secret key and sending the unlocking feedback instruction to the power supply controller;

and the CPU memory control unit is used for performing read-write operation on the static memory under the control of the power supply controller.

The power supply controller is also used for detecting whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus; receiving a reset instruction sent by the device management module based on a peripheral bus, and stopping writing the secret key into the static memory;

And the static memory is also used for prohibiting the CPU memory control unit from reading and writing data from the static memory when the key writing state is identified to disappear.

Correspondingly, the invention further provides a terminal device, which comprises a memory and a processor, wherein the processor executes the computer instructions stored in the memory, so that the terminal device executes the method.

According to the method and the system, when the power supply controller recognizes the state change of the memory control signal, the device management module is triggered to send the secret key, so that unlocking processing can be performed when the static memory is in the memory control state, when the unlocking processing is completed, the memory control unit can complete read-write operation of the static memory by combining the condition of the CPU, when different states of the CPU are switched, the running instructions of the CPU can be responded at any time, the running mechanisms of the CPU and the power supply management controller are the same, and the phenomenon of running or hanging of the CPU in the state change process is reduced.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings which are required in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a power management system according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for performing memory control on a power management system according to a second embodiment of the present invention;

FIG. 3 is a flow chart of a method for performing memory control on a power management system according to a third embodiment of the present invention;

FIG. 4 is a flow chart of a method for memory control of a power management system according to a fourth embodiment of the present invention;

fig. 5 is a schematic structural diagram of a terminal device according to a fifth embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

Specifically, fig. 1 shows a schematic structural diagram of a power management system in an embodiment of the present invention, where the power management system includes a power management module and a device management module, and the power management module includes: CPU, CPU memory control unit, static memory, system static memory unit, flash memory unit flash, analog unit, PMC control unit, etc.

The system supports CPU memory extension control, namely, the system controls the reading of running instructions from a CPU to be stored in a static memory sram before entering a STANDBY state STANDBY, and controls the reloading of the running instructions from the static memory sram to be written into the CPU after the system is powered on again in the STANDBY state STANDBY.

In the normal operation mode RUN, 1.1v power supply of the power management system is provided by the linear voltage regulator LDO 11_MR; in a low power mode, i.e., STANDBY mode, ldos11_mr is turned off and ldos11_lr powers the chip. The static memory and the flash are supplied with power by 1.1v through LDO 11_LR.

In STANDBY state STANDBY, the CPU memory control unit, and part of the analog units include an oscillator, a phase-locked loop, CMP, ADC, flash memory unit, etc. have no power supply, which belongs to a power-off region shutdown domain (shutdown), and the PMC control unit, and part of the analog units LDO have power supply all the time, which belongs to a power-on domain (alon) in a normally-on region.

The flash memory unit flash is internally provided with a power switch, and a supply signal support switch can be controlled. When support=0, the 1.1v and 3.3v power supplies of flash are turned off.

The system supports PAD keep enabling control, and mainly controls output of data related to a shutdown domain and enabling signals to be maintained in a state before power failure when the system is ready to enter a standby state.

When the system is not powered down, the CPU and the PMC can handshake to perform an abort standby operation, so that the CPU operation is prevented from being suspended or flying.

The power supply controller is used for detecting whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module is requested to send a secret key based on the peripheral bus; receiving a secret key sent by the equipment management module based on a peripheral bus, and writing the secret key into the static memory through a CPU memory control unit; controlling a CPU memory control unit to perform read-write operation on the static memory; the static memory is used for carrying out unlocking processing based on the secret key and sending the unlocking feedback instruction to the power supply controller; the CPU memory control unit is used for performing read-write operation on the static memory under the control of the power supply controller.

In the implementation process, the power supply controller is also used for detecting whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus; receiving a reset instruction sent by the device management module based on a peripheral bus, and stopping writing the secret key into the static memory; and the static memory is also used for prohibiting the CPU memory control unit from reading and writing data from the static memory when the key writing state is identified to disappear.

The power supply controller detects whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus; the power supply controller receives a reset instruction sent by the equipment management module based on the peripheral bus and stops writing the secret key into the static memory; and when the static memory recognizes that the key writing state disappears, the CPU memory control unit is forbidden to read and write data from the static memory.

In the implementation process, when the static memory recognizes the key writing, analyzing whether the security data in the static register is consistent with the key data, and if the security data is consistent with the key data, unlocking the static memory is completed.

In the implementation process, the static memory is unlocked by a public key when the static memory is a visible register, and is unlocked by a private key when the static memory is an invisible register.

When the state change of the memory control signal is recognized by the power supply controller in the embodiment of the invention, the device management module is triggered to send the secret key, so that the static memory can be unlocked when in the memory control state, and when the unlocking is finished, the memory control unit can finish the read-write operation of the static memory by combining the condition of the CPU, so that the running instructions of the CPU can be responded at any time when the different states of the CPU are switched, the running mechanisms of the CPU and the power supply management controller are the same, and the phenomena of running or hanging dead of the CPU in the state change process are reduced.

Example two

Specifically, fig. 2 is a flowchart of a method for performing memory control on a power management system according to a second embodiment of the present invention, where the method shown in fig. 2 is implemented according to the power management system shown in fig. 1, and the power management system supports CPU memory recall control, and the method includes the following steps:

s201, the CPU generates a deep sleep instruction and sends the deep sleep instruction to the PMC;

when the SOC is in the normal running RUN state and is required to enter the STANDBY state STANDBY, in order to ensure the state change, the SOC needs to undergo states such as waiting pmc_wait_cpu_hold, pmc_rdcpu_req, pmc_iso_on and the like to enter the STANDBY mode, wherein:

when the RUN state in the SOC enters a PMC_WAIT_CPU_HOLD state, the CPU generates a deep sleep instruction, the deep sleep instruction is sent to the PMC, the PMC generates a HOLD non-execution instruction HOLD sleep signal, and the PMC needs to WAIT for the CPU to be kept in a sleep (HOLD sleep) state by the PMC, namely, the PMC_WAIT_CPU_HOLD state, and the CPU is supplied with power but does not execute the instruction in the state;

in the process that the CPU is ready to be powered down, as the system supports CPU memory recall control, the system needs to enter a CPU retention read request stage, namely, needs to be shifted from a PMC_WAIT_CPU_HOLD state to a PMC_RDCPU_REQ state, in the PMC_RDCPU_REQ state, the CPU is supplied with power but does not execute instructions, the PMC generates a CPU memory instruction and then sends the CPU memory instruction to a static memory, and the static memory reads the current running instruction from the CPU based on the CPU memory instruction and writes the running instruction into the static memory; if the entire recovery control is complete, the PMC needs to enter an isolation ON enabled state, i.e., a PMC_ISO_ON state. In the pmc_iso_on state, the CPU is in a PMC hold sleep state, the PMC is in normal operation, it needs to make the PMC enter from normal operation to the mode with the lowest power consumption to complete the system isolation enabled state, after the system isolation enabled state is completed, the system ON chip turns off most of the voltage of the digital circuit, and only the external wake-up source is reserved to enter the STANDBY mode.

The isolation enable state refers to the isolation enable of the output signal of the shutdown domain, when the isolation enable is effective, the output signal has no influence on the control logic of the always on domain, and when the enable signal is ineffective, the output signal is a normal control logic signal.

S202, after receiving a deep sleep instruction, the PMC generates a holdsleep signal of a CPU hold non-execution instruction and sends the holdsleep signal to the CPU;

in the process of going through WAIT pmc_wait_cpu_hold, pmc_rdcpu_req, pmc_iso_on, etc. to enter STANDBY mode, the CPU simply does not execute instructions, but gets power supply of the power module.

A deep sleep instruction, a holdsleep signal and a holdsleep_ackn are arranged between the CPU and the PMC to realize the synchronization process between the CPU and the PMC.

The deep sleep instruction is a deep sleep signal generated by the CPU, and after the PMC receives the deep sleep signal, the PMC starts to control the system to enter STANDBY mode.

The holdsleep signal is a signal that holds the CPU in place of executing instructions, is generated by the PMC and fed into the CPU, and upon receipt of this signal, holds the CPU state hold. The holdsleep signal is deactivated in the second beat when a PMC synchronous wakeup source occurs during entry into STANDBY mode.

The holdsleep_ackn is an holded ackdledge signal fed back by the CPU after the CPU receives the holdsleep_ackn signal, the holdsleep_ackn signal is generated by the CPU and fed into the PMC component, and when the holdsleep_ackn signal is invalid, the holdsleep_ackn signal is invalid after the second beat.

After the PMC receives the deep sleep instruction, generating a holdsleep signal for the CPU to hold the non-execution instruction, and transmitting the holdsleep signal to the CPU includes: the PMC generates a holdsleep signal based on an internal low speed SIRC clock (src_clk) timing after receiving the deep sleep instruction.

S203, PMC controls internal low-speed SIRC clock time sequence to enable a holdsleep signal acting on a CPU to be in an active-low state, so that a power management system is ready to enter a standby state;

s204, the power supply controller detects whether the holdsleep signal changes from an invalid state to an valid state;

the power supply controller triggers the state change of the memory control signal by detecting the state change of the holdsleep signal, so that the memory control signal can be adaptively adjusted to be in a standby state along with the change of the power supply management system.

Specifically, if the power supply controller detects that the holdsleep signal changes from the inactive state to the active state, the step S205 is performed to trigger the memory control signal acting on the static memory to change from the inactive state to the active state; if the power supply controller does not detect that the holdsleep signal changes from the inactive state to the active state, the corresponding processing is performed in S203 or S204.

S205, triggering a memory control signal acting on the static memory to change from an invalid state to an effective state;

from the viewpoint of protecting the static memory and saving power consumption, after the system requests to enter the sleep mode, the system needs to set the signal CEN/TCEN of the sram (fixed as 1 at the sram port)/DFTRAMBYP (fixed as 1 at the sram port) and the like to a fixed value according to spec requirements, and clock gating to 0, and the sram enters the low power consumption mode.

The power controller controls the signal CEN/TCEN/DFTRAMBYP of the sram and performs the sramclock gating after the PMC waits for the CPU to be PMC hold sleep state.

The sram is specially used for storing CPU information when the CPU is in extension, so if the CPU is in extension, the sram used for storing the CPU is unable to fix CEN after finishing CPU extension reading operation after the PMC receives the deepseep signal, and clock is set to 0, and the CPU enters low power consumption.

When PMC enters the stage from isolation enable to power down, the signal of sram_ret1n needs to be pulled down to trigger the memory control signal acting on the static memory to change from invalid state to valid state, i.e. let sram enter the recovery state.

S206, the power supply controller detects whether a memory control signal on the static memory changes from an invalid state to an valid state;

specifically, if the power supply controller determines that the memory control signal is changed from the inactive state to the active state, the process proceeds to S207, otherwise, the process proceeds to S205.

S207, requesting a device management module to send a secret key based on a peripheral bus;

s208, the power supply controller receives a secret key sent by the equipment management module based on the peripheral bus;

s209, the power supply controller writes the secret key into the static memory through a CPU memory control unit;

s210, the static memory performs unlocking processing based on the secret key and sends the unlocking feedback instruction to a power supply controller;

and when the static memory recognizes that the secret key is written, analyzing whether the safety data in the static register is consistent with the secret key data, and if the safety data is consistent with the secret key data, unlocking the static memory.

In the specific implementation process, when the key writing is identified, firstly detecting the length of the key data, if the length of the key data meets the preset condition, stripping a head file and a tail check bit in the key data, extracting the safety data in the key, comparing and analyzing the safety data in the key with the safety data in the static register, and if the safety data in the key is judged to be consistent with the safety data in the static register, completing unlocking of the static register.

S211, the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory.

When the power supply controller detects that the sram_ret1n signal is generated effectively, the PMC sends a Key request instruction through the peripheral bus APB, and after receiving the Key request instruction, the equipment management module connected with the APB provides relevant software control information such as control information required by analog functional modules such as LDO, clock and the like for the power supply controller based on the APB; the static memory performs unlocking processing according to the secret key sent by the equipment management module, so that the CPU memory control unit is controlled to complete the memory control process.

Since the system supports CPU memory reservation control, the CPU memory control unit reads the running instruction from the CPU and stores the running instruction in the static memory when the memory control signal is in effect.

When the power supply controller in the embodiment of the invention enters the standby state from the normal running state, the state change of the memory control signal is identified, so that the equipment management module is triggered to send the secret key, the static memory can be unlocked when the memory control state is reached, when the unlocking is completed, the memory control unit can complete the read-write operation of the static memory by combining the condition of the CPU, the running instruction of the CPU can be responded at any time when the different states of the CPU are switched, the running mechanisms of the CPU and the power supply management controller are the same, and the running or hanging phenomenon of the CPU in the state change process is reduced.

Example III

Specifically, fig. 3 is a flowchart showing a method for performing memory control on a power management system according to a third embodiment of the present invention, where the method shown in fig. 3 is implemented according to the power management system shown in fig. 1, and the power management system supports CPU memory recall control, and the method includes the following steps:

starting;

the power supply controller in the embodiment of the invention controls the CPU memory control unit to perform read-write operation on the static memory under two conditions: when the power management system enters a standby state from a normal operation state, the power controller controls the CPU memory control unit to read an operation instruction from the CPU and store the operation instruction into the static memory; when the power management system enters a normal running state from a standby state, the power controller controls the CPU memory control unit to reload running instructions from the static memory to write into the CPU.

S301, a power supply controller detects whether a memory control signal acting on a static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state;

the memory control signal in the embodiment of the invention can be generated when the power management system enters the standby state from the normal running state, or can be generated when the power management system enters the normal running state from the standby state.

S302, a device management module sends a secret key based on a peripheral bus request;

s303, the power supply controller receives a secret key sent by the equipment management module based on the peripheral bus, and writes the secret key into the static memory through the CPU memory control unit;

s304, the static memory performs unlocking processing based on the secret key and sends the unlocking feedback instruction to a power supply controller;

it should be noted that, when the static memory recognizes the key writing, it analyzes whether the security data in the static register is consistent with the key data, and if the security data is consistent with the key data, it completes unlocking the static memory.

In the specific implementation process, when the key writing is identified, firstly detecting the length of the key data, if the length of the key data meets the preset condition, stripping a head file and a tail check bit in the key data, extracting the safety data in the key, comparing and analyzing the safety data in the key with the safety data in the static register, and if the safety data in the key is judged to be consistent with the safety data in the static register, completing unlocking of the static register.

S305, the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory;

the CPU memory control unit reads the operation instruction from the CPU under the action of the power supply controller and writes the operation instruction into the static memory, so that the operation instruction of the CPU can be ensured to complete the memory function.

When the power management system enters a standby state from a normal operation state, the power controller controls the CPU memory control unit to read an operation instruction from the CPU and store the operation instruction into the static memory; when the power management system enters a normal running state from a standby state, the power controller controls the CPU memory control unit to reload running instructions from the static memory to write into the CPU.

S306, the power supply controller detects whether a memory control signal on the static memory changes from an effective state to an ineffective state;

if it is determined that the memory control signal is changed from the inactive state to the active state, the process proceeds to S306, otherwise, the process proceeds to S305, where the whole memory operation is known to be completed by determining the change of the memory control signal, and further control of the read/write operation of the static memory is required.

S307, requesting the device management module to send a reset instruction based on the external network bus;

S308, the power supply controller receives a reset instruction sent by the equipment management module based on the peripheral bus and stops writing the secret key into the static memory;

s309, when the static memory recognizes that the key writing state disappears, the CPU memory control unit is prohibited from reading and writing data from the static memory.

According to the embodiment of the invention, the state change of the memory control signal is identified, so that the static memory can be combined with the validity of the memory control signal to complete unlocking processing to realize the reading and writing functions of the CPU running instruction, the validity of the CPU running instruction in reading and writing is ensured, when different states of the CPU are switched, the running instruction of the CPU can respond at any time, the running mechanisms of the CPU and the power management controller are the same, and the running or hanging phenomenon of the CPU in the state change process is reduced.

Example IV

Specifically, fig. 4 is a flowchart showing a method for performing memory control on a power management system according to a second embodiment of the present invention, where the method shown in fig. 4 is implemented according to the power management system shown in fig. 1, and the power management system supports CPU memory recall control, and the method includes the following steps:

s401, the PMC recognizes that a wake-up source wakeup signal appears;

When the whole power management system is in a standby state, the PMC recognizes that a wake-up source appears, a power-on process is required to be completed for a CPU and a CPU memory control unit in the whole power management system, and the memory control process is required to be completed when the power-on process is completed, so that an operation instruction in the static memory can be reloaded into the CPU, and the normal operation process of the whole power management system is ensured.

S402, the PMC outputs an isolation control signal for the static memory;

it should be noted that, when the SOC is in the normal running RUN mode and is required to enter the STANDBY mode STANDBY, in order to ensure a state change, it needs to undergo states such as waiting pmc_wait_cpu_hold, pmc_rdcpu_req, pmc_iso_on, and the like to enter the STANDBY mode, where:

when RUN mode in SOC enters PMC_WAIT_CPU_HOLD state, CPU generates deep sleep instruction, which is sent to PMC, PMC generates HOLD no-execute instruction HOLD sleep signal, in this process PMC needs to WAIT for CPU to be kept sleeping (HOLD sleep) state by PMC, i.e. PMC_WAIT_CPU_HOLD state, in which CPU has power supply but does not execute instruction;

in the process that the CPU is ready to be powered down, as the system supports CPU memory request control, the system needs to enter a CPU retention read request stage, namely, needs to be shifted from a PMC_WAIT_CPU_HOLD state to a PMC_RDCPU_REQ state, in the PMC_RDCPU_REQ state, the CPU has power supply but does not execute instructions, the PMC can generate a CPU memory instruction, and simultaneously triggers a memory control signal acting on a static memory to change from an invalid state to an effective state, and a CPU memory control unit reads a current running instruction from the CPU and writes the running instruction into the static memory; if the entire recovery control is complete, the PMC needs to enter an isolation ON enabled state, i.e., a PMC_ISO_ON state. In the pmc_iso_on state, the CPU is in a PMC hold sleep state, the PMC is in normal operation, it needs to make the PMC enter from normal operation to the mode with the lowest power consumption to complete the system isolation enabled state, after the system isolation enabled state is completed, the system ON chip turns off most of the voltage of the digital circuit, and only the external wake-up source is reserved to enter the STANDBY mode.

The isolation enable state refers to the isolation enable of the output signal of the shutdown domain, when the isolation signal is valid, the output signal has no influence on the control logic of the always on domain, and when the isolation control signal is invalid, the output signal is a normal control logic signal.

When the power management system is in a standby state to a normal running state, the whole system can change the isolation enabling state, namely the validity of the isolation control signal is changed, so that the shddown domain can receive the control logic signal, namely the isolation control signal is changed from the valid state to the invalid state, and the control logic signal on the whole power management system can meet the normal running.

S403, triggering a memory control signal acting on the static memory to change from an invalid state to an effective state;

from the viewpoint of protecting the static memory and saving power consumption, after the system requests to enter the sleep mode, the system needs to set the signal CEN/TCEN of the sram (fixed as 1 at the sram port)/DFTRAMBYP (fixed as 1 at the sram port) and the like to a fixed value according to spec requirements, and clock gating to 0, and the sram enters the low power consumption mode.

The power controller controls the signal CEN/TCEN/DFTRAMBYP of the sram and performs the sramclock gating after the PMC waits for the CPU to be PMC hold sleep state.

The sram is specially used for storing CPU information when the CPU is in extension, so if the CPU is in extension, the sram used for storing the CPU is unable to fix CEN after finishing CPU extension reading operation after the PMC receives the deepseep signal, and clock is set to 0, and the CPU enters low power consumption.

When PMC enters the stage from isolation enable to power down, the signal of sram_ret1n needs to be pulled down to trigger the memory control signal acting on the static memory to change from invalid state to valid state, i.e. let sram enter the recovery state.

S404, the power supply controller detects whether a memory control signal on the static memory changes from an invalid state to an valid state;

specifically, if the power supply controller determines that the memory control signal is changed from the inactive state to the active state, the process proceeds to S405, otherwise, the process proceeds to S403.

S405, requesting the device management module to send a secret key based on the peripheral bus;

s406, the power supply controller receives the secret key sent by the equipment management module based on the peripheral bus;

s407, the power supply controller writes the secret key into the static memory through the CPU memory control unit;

s408, the static memory performs unlocking processing based on the secret key and sends the unlocking feedback instruction to a power supply controller;

It should be noted that, when the static memory recognizes the key writing, it analyzes whether the security data in the static register is consistent with the key data, and if the security data is consistent with the key data, it completes unlocking the static memory.

In the specific implementation process, when the key writing is identified, firstly detecting the length of the key data, if the length of the key data meets the preset condition, stripping a head file and a tail check bit in the key data, extracting the safety data in the key, comparing and analyzing the safety data in the key with the safety data in the static register, and if the safety data in the key is judged to be consistent with the safety data in the static register, completing unlocking of the static register.

S409, the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory;

s410, the power supply controller detects whether a memory control signal on the static memory changes from an effective state to an ineffective state;

if it is determined that the memory control signal is changed from the inactive state to the active state, the process proceeds to S411, otherwise, the process proceeds to S410, where the memory control signal is determined to change so as to understand that the whole memory operation is completed, and then the read/write operation of the static memory needs to be further controlled.

S411, requesting the device management module to send a reset instruction based on an external network bus;

s412, the power supply controller receives a reset instruction sent by the equipment management module based on the peripheral bus, and stops writing the secret key into the static memory;

s413, when the static memory recognizes that the key writing state disappears, prohibiting the CPU memory control unit from reading and writing data from the static memory;

s414, the power management system enters a normal running state.

When the power supply controller detects that the sram_ret1n signal is generated effectively, the PMC sends a Key request instruction through the peripheral bus APB, and after receiving the Key request instruction, the equipment management module connected with the APB provides relevant software control information such as control information required by analog functional modules such as LDO, clock and the like for the power supply controller based on the APB; the static memory performs unlocking processing according to the secret key sent by the equipment management module, so that the CPU memory control unit is controlled to complete the memory control process.

Since the system supports CPU memory reservation control, the CPU memory control unit reads the running instruction from the CPU and stores the running instruction in the static memory when the memory control signal is in effect.

When the power supply controller in the embodiment of the invention enters a normal running state from a standby state, the state change of the memory control signal is identified, so that the equipment management module is triggered to send a secret key, the static memory can be unlocked when the memory control state is reached, when the unlocking is completed, the memory control unit can complete the read-write operation of the static memory by combining the condition of the CPU, the running instruction of the CPU can be responded at any time when different states of the CPU are switched, the running mechanisms of the CPU and the power supply management controller are the same, and the running or hanging phenomenon of the CPU in the state change process is reduced.

Example five

In order to facilitate better implementation of the foregoing solutions of the embodiments of the present invention, the present invention correspondingly provides a terminal device 50, which is described in detail below with reference to the accompanying drawings:

as shown in fig. 5, the terminal device 50 may include a processor 501, a memory 504 and a communication module 505, where the processor 501, the memory 504 and the communication module 505 may be connected to each other through a bus 506. The memory 504 may be a high-speed random access memory (Random Access Memory, RAM) memory or a nonvolatile memory (non-volatile memory), such as at least one disk memory. The memory 504 may also optionally be at least one storage system located remotely from the aforementioned processor 501. Memory 504 is used for storing application program codes and may include an operating system, a network communication module, a user interface module, and a data processing program, and communication module 505 is used for information interaction with external devices; the processor 501 is configured to invoke the program code to perform the steps of:

The power supply controller detects whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module sends a secret key based on the peripheral bus request;

the power supply controller receives the secret key sent by the equipment management module based on the peripheral bus, and writes the secret key into the static memory through the CPU memory control unit;

the static memory performs unlocking processing based on the secret key and sends the unlocking feedback instruction to the power supply controller;

and the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory.

and

The power supply controller detects whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus;

the power supply controller receives a reset instruction sent by the equipment management module based on the peripheral bus and stops writing the secret key into the static memory;

and when the static memory recognizes that the key writing state disappears, the CPU memory control unit is forbidden to read and write data from the static memory.

The unlocking processing of the static memory based on the secret key comprises the following steps:

when the static memory recognizes the key writing, analyzing whether the safety data in the static register is consistent with the key data, and if the safety data is consistent with the key data, unlocking the static memory is completed

It should be noted that, for the execution steps of the processor in the terminal device 50 in the embodiment of the present invention, reference may be made to the specific implementation manner of the method steps in the embodiments of fig. 2 to 4 in the above method embodiments, and details are not repeated here.

The computer readable storage medium may be an internal storage unit of the apparatus according to the foregoing embodiment, such as a hard disk or a memory. The computer-readable storage medium may be an external storage device of the above device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like. Further, the computer-readable storage medium may include both an internal storage unit and an external storage device of the above device. The computer-readable storage medium is used to store the computer program and other programs and data required by the apparatus. The above-described computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

Those skilled in the art will appreciate that implementing all or part of the above-described embodiment methods may be accomplished by way of a computer program, which may be stored in a computer-readable storage medium and which, when executed, may comprise the steps of the embodiments of the methods described above. And the aforementioned storage medium includes: various media capable of storing program code, such as ROM, RAM, magnetic or optical disks.

The foregoing has outlined rather broadly the more detailed description of embodiments of the invention, wherein the principles and embodiments of the invention are explained in detail using specific examples, the description of the embodiments being merely intended to facilitate an understanding of the method of the invention and its core concepts; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (10)

1. A method of memory control of a power management system, the method comprising the steps of:

the power supply controller detects whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module sends a secret key based on the peripheral bus request;

The power supply controller receives the secret key sent by the equipment management module based on the peripheral bus, and writes the secret key into the static memory through the CPU memory control unit;

the static memory performs unlocking processing based on the secret key and sends the unlocking feedback instruction to the power supply controller;

and the power supply controller controls the CPU memory control unit to perform read-write operation on the static memory.

2. The method of memory control of a power management system of claim 1, further comprising:

the power supply controller detects whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus;

the power supply controller receives a reset instruction sent by the equipment management module based on the peripheral bus and stops writing the secret key into the static memory;

and when the static memory recognizes that the key writing state disappears, the CPU memory control unit is forbidden to read and write data from the static memory.

3. The method for memory control of a power management system according to claim 1, wherein said unlocking of said static memory based on said key comprises:

And when the static memory recognizes that the secret key is written, analyzing whether the safety data in the static register is consistent with the secret key data, and if the safety data is consistent with the secret key data, unlocking the static memory.

4. A method of memory control of a power management system according to any one of claims 1 to 3, wherein the power controller controlling the CPU memory control unit to perform read and write operations on the static memory comprises:

when the power management system enters a standby state from a normal operation state, the power controller controls the CPU memory control unit to read an operation instruction from the CPU and store the operation instruction into the static memory;

when the power management system enters a normal running state from a standby state, the power controller controls the CPU memory control unit to reload running instructions from the static memory to write into the CPU.

5. The method of memory control of a power management system of claim 4, further comprising:

after receiving the deep sleep instruction, the PMC generates a holdsleep signal of the CPU hold non-execution instruction and sends the holdsleep signal to the CPU;

The internal low speed SIRC clock timing is controlled such that the holdsleep signal on the CPU is active low so that the power management system is ready to enter a standby state.

6. The method of memory control of a power management system of claim 5, further comprising:

the power supply controller detects whether the holdsleep signal changes from an invalid state to an valid state;

when the power supply controller detects that the holdsleep signal is changed from the inactive state to the active state, the memory control signal acting on the static memory is triggered to be changed from the inactive state to the active state.

7. The method of memory control of a power management system of claim 4, further comprising:

the PMC identifies that a wake-up source wakeup signal appears;

the PMC outputs an isolation control signal for the static memory.

8. A power management system, the power management system comprising:

the power supply controller is used for detecting whether a memory control signal acting on the static memory changes from an invalid state to an effective state, and if the memory control signal is judged to change from the invalid state to the effective state, the device management module is requested to send a secret key based on the peripheral bus; receiving a secret key sent by the equipment management module based on a peripheral bus, and writing the secret key into the static memory through a CPU memory control unit; controlling a CPU memory control unit to perform read-write operation on the static memory;

The static memory is used for carrying out unlocking processing based on the secret key and sending the unlocking feedback instruction to the power supply controller;

and the CPU memory control unit is used for performing read-write operation on the static memory under the control of the power supply controller.

9. The power management system of claim 8, wherein,

the power supply controller is also used for detecting whether a memory control signal on the static memory changes from an effective state to an ineffective state, and if the memory control signal is judged to change from the ineffective state to the effective state, the device management module is requested to send a reset instruction based on the external network bus; receiving a reset instruction sent by the device management module based on a peripheral bus, and stopping writing the secret key into the static memory;

and the static memory is also used for prohibiting the CPU memory control unit from reading and writing data from the static memory when the key writing state is identified to disappear.

10. A terminal device comprising a memory and a processor, the processor executing computer instructions stored in the memory, causing the terminal device to perform the method of any one of claims 1-7.

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