CN116015258B - Switching circuit and electronic device - Google Patents

Abstract

The application provides a switch circuit and electronic equipment, relates to the technical field of electronic equipment, and can reduce the cost of electronic equipment. The switching circuit includes: at least one analog switch, an input node, a power supply node, a ground node, an enable node, and a common node; the analog switch comprises an input pin, a power pin, a ground pin, an enable pin and a common pin; an input pin is coupled with the input node, a power supply pin is coupled with the power supply node, a ground pin is coupled with the ground node, an enabling pin is coupled with the enabling node, and a common pin is coupled with the common node; the switching circuit further includes: at least one impedance device; wherein the impedance device is coupled between at least one of the power pin and the power node, the ground pin and the ground node, and the enable pin and the enable node.

Description

Switch circuits and electronic equipment

This application is a divisional application. The name of the original application is switch circuits and electronic equipment. The application number of the original application is 202111235596.X. The original application date is October 22, 2021. The entire content of the original application is incorporated into this application by reference. middle.

Technical field

The present application relates to the technical field of electronic equipment, and in particular, to a switching circuit and electronic equipment.

Background technique

Analog switch is a switch that uses the characteristics of analog devices (MOS tubes) to control the signal path. It is mainly used to complete the switching function of connecting or disconnecting the signal link. Because of its low power consumption, fast speed, no mechanical contacts, small size and long service life, it is widely used in electronic devices such as mobile phones, tablets, and computers.

According to the application scenarios of analog switches, they are generally divided into low-speed analog switches and high-speed analog switches. For example, in a mobile phone, when a USB signal needs to be transmitted through an analog switch, the analog switch is a high-speed analog switch; when an audio analog signal needs to be transmitted through an analog switch, the analog switch can be a low-speed analog switch.

High-speed analog switches require higher switching speeds, so their design requirements are higher and their costs are higher. When high-speed analog switches are applied to electronic devices such as mobile phones, tablets, and computers, the cost of the electronic devices increases.

Contents of the invention

In order to solve the above technical problems, this application provides a switching circuit and electronic equipment. Can reduce the cost of electronic equipment.

In a first aspect, embodiments of the present application provide a switch circuit. The switch circuit includes: at least one analog switch, an input node, a power node, a ground node, an enable node, and a common node; the analog switch includes an input pin and a power pin. , ground pin, enable pin, common pin; the input pin is coupled to the input node, the power pin is coupled to the power node, the ground pin is coupled to the ground node, the enable pin is coupled to the enable node, the common pin The pin is coupled to the common node; the switch circuit also includes: at least one impedance device; wherein the impedance device is coupled between the power pin and the power node, between the ground pin and the ground node, and between the enable pin and the enable node between at least one of them.

Adding impedance devices to the pins of the analog switch increases the impedance of the path and reduces signal leakage. Even if the analog switch used is a low-speed analog switch, high-speed signals can be transmitted through the low-speed analog switch, broadening the use of low-speed analog switches. Scenes. In addition, since the cost of the low-speed analog switch is lower, when the switching circuit is applied to electronic equipment, the cost of the electronic equipment can be reduced.

For example, the number of analog switches is one, the number of input pins in the analog switch is two, the number of power pins, ground pins, enable pins and common pins is one, and the two input pins include an input pin and a second input pin. Alternatively, the number of input pins is four, that is, the input pins include a first input pin, a second input pin, a third input pin and a fourth input pin, and the number of common pins is two, that is, the common pins The pins include the first common pin and the second common pin. The number of enable pins is two, that is, the enable pins include the first enable pin, the second enable pin, the power pin and the ground pin. The quantity is one.

In some possible implementations, the input node includes a first input node and a second input node; the common node includes a first common node and a second common node; the enabling node includes a first enabling node and a second enabling node; The first input node, the second input node, the first common node, the second common node, the first enable node and the second enable node are respectively coupled to different pins of the analog switch; the first input node is used to receive the positive differential signal; the first enable node is used to receive the first enable voltage, and transmit the first enable voltage to the enable pin coupled with the first enable node, so that the common tube coupled with the first common node The pin is connected to the input pin coupled to the first input node; the common pin coupled to the first common node is used to transmit the positive differential signal to the first common node; the second input node is used to receive the negative differential signal; The two enable nodes are used to receive the second enable voltage and transmit the second enable voltage to the enable pin coupled with the second enable node, so that the common pin coupled with the second common node and The input pin coupled to the second input node is turned on; the common pin coupled to the second common node is used to transmit the negative differential signal to the second common node, so that the switch circuit can be used to transmit differential signals.

For example, the first input node, the second input node, the first common node, the second common node, the first enable node and the second enable node are respectively coupled to different pins of the analog switch and may be the first input node. , the second input node, the first common node, the second common node, the first enable node and the second enable node are respectively coupled to different pins of the same analog switch. It may also be an analog switch corresponding to the pin coupled to the first input node, the first common node, and the first enabling node, and an analog switch corresponding to the pin coupled to the second input node, the second common node, and the second enabling node. different.

In some possible implementations, the switch circuit includes: at least two analog switches, the at least two analog switches include a first analog switch and a second analog switch; the first input node is coupled to the input pin in the first analog switch, The first common node is coupled to the common pin in the first analog switch; the second input node is coupled to the input pin of the second analog switch; and the second common node is coupled to the common pin in the second analog switch. In this way, the positive differential signal and the negative differential signal are transmitted in the two analog switches respectively, further reducing mutual coupling within the analog switches.

In some possible implementations, the number of impedance devices corresponding to the first analog switch is the same as the number of impedance devices corresponding to the second analog switch. This makes the impedance device corresponding to each analog switch have the same impact on the positive differential signal and the negative differential signal, thereby improving signal reliability.

In some possible implementations, the position of the impedance device corresponding to the first analog switch and the position of the impedance device corresponding to the second analog switch are the same. This further makes the impedance device corresponding to each analog switch have the same impact on the positive differential signal and the negative differential signal, thereby improving signal reliability.

For example, the pins and nodes to which the impedance device corresponding to the first analog switch is coupled are the same as the pins and nodes to which the impedance device corresponding to the second analog switch is coupled.

In some possible implementation methods, the switching speed of the analog switch is less than or equal to 100 MHz, that is, high-speed signals can be transmitted through the low-speed analog switch, which reduces the cost of the electronic device when the switching circuit is applied to the electronic device.

In some possible implementation methods, the impedance value of the impedance device is greater than 600 ohms, which further increases the impedance of the path and further prevents signal leakage.

In some possible implementation methods, the impedance device includes an inductor, a magnetic bead, or a combination of an inductor and a capacitor.

Some possible implementation methods include: at least three impedance devices; the three impedance devices are respectively coupled between the ground node and the ground pin, between the enable node and the enable pin, and between the power node and the power pin. between. In this way, it will not affect the signal transmission, but can also better reduce signal leakage.

In a second aspect, embodiments of the present application provide an electronic device, which includes any of the above switching circuits. All the effects of the above switching circuit can be achieved.

Description of the drawings

Figure 1 is a schematic diagram of an application scenario of an electronic device provided by an embodiment of the present application;

Figure 2 is a schematic diagram of an application scenario of the electronic device provided by the embodiment of the present application;

Figure 3 is one of the schematic diagrams of an application scenario of the electronic device provided by the embodiment of the present application;

Figure 4 is a schematic diagram of an application scenario of the electronic device provided by the embodiment of the present application;

Figure 5 is a schematic diagram of an application scenario of the electronic device provided by the embodiment of the present application;

Figure 6 is a schematic diagram of an application scenario of the electronic device provided by the embodiment of the present application;

Figure 7 is one of the schematic diagrams of an application scenario of the electronic device provided by the embodiment of the present application;

Figure 8 is a schematic structural diagram of a switch circuit provided by an embodiment of the present application;

Figure 9 is an equivalent circuit diagram of an analog switch provided by an embodiment of the present application;

Figure 10 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application;

Figure 11 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application;

Figure 12 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application;

Figure 13 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application;

Figure 14 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 15 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 16 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 17 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 18 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 19 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 20 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 21 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 22 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

Figure 23 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application;

FIG. 24 is a schematic structural diagram of another switch circuit provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The term "and/or" in this article is just an association relationship that describes related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations.

The terms “first” and “second” in the description and claims of the embodiments of this application are used to distinguish different objects, rather than to describe a specific order of objects. For example, the first target object, the second target object, etc. are used to distinguish different target objects, rather than to describe a specific order of the target objects.

In the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

In the description of the embodiments of this application, unless otherwise specified, the meaning of “plurality” refers to two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

Embodiments of the present application provide an electronic device. The electronic device provided by the embodiment of the present application may be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA for short), a vehicle-mounted computer, a television, a smart wearable device, a smart phone Electronic equipment such as household equipment with analog switches. The embodiments of the present application do not specifically limit the specific form of the above-mentioned electronic equipment.

The specific structure and use of the electronic device provided by the embodiments of the present application are described below.

As shown in Figure 1 , Figure 1 shows a schematic diagram of an application scenario of the electronic device provided by the embodiment of the present application. The electronic device 100 includes a control module 10, an audio module 20, an analog switch 30, an external interface 40, etc. The external interface 40 is provided so that the electronic device 100 can be coupled with external devices. The external interface 40 is, for example, a USB interface. External devices may include, for example, chargers, headphones, mobile phones, computers and other electronic devices.

Exemplarily, the analog switch 30 may include, for example, a single pole double throw (Single Pole Double Throw, SPDT) switch. In conjunction with FIG. 2 , FIG. 2 shows a functional block diagram of the analog switch. The analog switch 30 includes a first input pin 1 and a grounding pin. Pin 2, second input pin 3, enable pin 4, power pin 5 and common pin 6. The first input pin 1 is coupled to the control module 10, the second input pin 3 is coupled to the audio module 20, the ground pin 2 is set to ground, the power pin 5 is used to receive the power signal, and the enable pin 4 is used to receive the power signal. enable voltage, and control the common pin 6 to be conductive with the first input pin 1 according to the enable voltage, or control the common pin 6 to be conductive with the second input pin 3.

It should be noted here that FIG. 2 takes the analog switch 30 as an SPDT switch as an example for illustration, but this does not constitute a limitation on the present application. Those skilled in the art can select the type of the analog switch 30 according to the actual situation. The embodiments of the present application do not Make specific limitations. Unless otherwise stated, the analog switch 30 is used as an SPDT switch as an example in the following description.

In this case, for example, referring to FIG. 3 , when the external device connected to the external interface 40 is the computer 200 , the control module 10 may be used to output a high-speed USB signal, for example. The enable pin 4 controls the common pin 6 to be connected to the first input pin 1 according to the received enable voltage, and the high-speed USB signal is transmitted to the computer 200 through the analog switch 30 and the external interface 40, thereby realizing the transmission of the USB signal. The control module 10 may include, for example, a microcontroller unit (Microcontroller Unit, MCU). The control module 10 may be an independent device or may be integrated on a system on chip SoC, which is not limited in the embodiment of the present application. Referring to FIG. 4 , when the external device connected to the external interface 40 is the earphone 300 , the audio module 20 is, for example, used to output an audio analog signal. The enable pin 4 controls the common pin 6 to conduct with the second input pin 3 according to the received enable voltage, and the audio analog signal output by the audio module 20 is transmitted to the earphone 300 through the analog switch 30 and the external interface 40, thereby causing the earphone to 300 can hear the sound emitted by the electronic device 100 . The audio module 20 may be, for example, a chip that performs audio processing. Based on this situation, the embodiment of the present application does not limit the type of the chip.

As shown in Figure 5, Figure 5 shows a schematic diagram of another application scenario of the electronic device provided by the embodiment of the present application. The electronic device 100 includes a control module 10, an analog switch 30, an external interface 40, and so on. The external interface 40 is provided so that the electronic device 100 can be coupled with external devices. The external interface 40 is, for example, a USB interface. External devices may include, for example, chargers, headphones, mobile phones, computers, test equipment and other electronic devices.

The analog switch 30 includes a single pole double throw (Single Pole Double Throw, SPDT) switch as an example for description. Referring to FIG. 6 , when the external device connected to the external interface 40 is a computer 200 , the control module 10 may be used to output a high-speed USB signal, for example. The enable pin 4 controls the common pin 6 to be connected to the first input pin 1 according to the received enable voltage, and the high-speed USB signal is transmitted to the computer 200 through the analog switch 30 and the external interface 40, thereby realizing the transmission of the USB signal. Referring to FIG. 7 , when the electronic device 100 needs to be debugged, the external device connected to the external interface 40 is the test device 400 , and the control module 10 outputs a low-speed debugging signal. The enable pin 4 controls the common pin 6 to conduct with the second input pin 3 according to the received enable voltage, and the low-speed debugging signal is transmitted to the test equipment 400 through the analog switch 30 and the external interface 40 to debug the electronic device 100 .

It should be noted that the above example only uses the analog switch 30 to be coupled to the control module 10 and the audio module 20 respectively, and the high-speed USB signal output by the control module 10 and the audio analog signal output by the audio module 20 are transmitted through the analog switch 30; and, analog The switch 30 is coupled with the control module 10 and transmits the high-speed USB signal and the low-speed debugging signal through the analog switch 30 as an example. Of course, the analog switch 30 can also be applied to other scenarios to realize the transmission of other signals. In addition, the analog switch 30 may transmit only one kind of signal; it may also transmit different signals, which is not limited in the embodiment of the present application. Unless otherwise stated below, the transmission of high-speed USB signals and audio analog signals through the analog switch 30 is used as an example.

Since the USB signal is a high-speed signal, the analog switch 30 needs to be a high-speed analog switch, so that link switching can be quickly realized and the transmission of high-speed signals can be completed. However, because the design requirements of high-speed analog switches are high, their costs are high, which results in a high cost of the electronic device 100 .

In order to solve the above technical problems, embodiments of the present application provide a switch circuit, which includes at least one analog switch and an impedance device located on the analog switch pin. By adding impedance devices to the pins of the analog switch, the impedance of the path is increased and signal leakage is reduced. Even if the analog switch used is a low-speed analog switch, high-speed signals can be transmitted through the low-speed analog switch, broadening the range of the low-speed analog switch. scenes to be used. In addition, since the cost of the low-speed analog switch is lower, when the switching circuit is applied to electronic equipment, the cost of the electronic equipment can be reduced.

The above switching circuit will be described in detail below in conjunction with electronic equipment.

As shown in FIG. 8 , the switch circuit 50 includes an analog switch 30 , an enable node IN, a power node VCC, a common node COM, a ground node GND, and an input node N. The input node N may include, for example, a first input node NO and a second input node NC. The switching speed of the analog switch 30 may be lower, for example, the switching speed of the analog switch 30 may be less than or equal to 100 MHz. The first input node NO is coupled to the first input pin 1, the second input node NC is coupled to the second input pin 3, the ground node GND is coupled to the ground pin 2, the enable node IN is coupled to the enable pin 4, The power node VCC is coupled to power pin 5, and the common node COM is coupled to common pin 6.

Continuing to refer to FIG. 8 , the switch circuit 50 further includes an impedance device 60 , and the number of the impedance devices 60 is, for example, three. One of the impedance devices 60 is coupled between the ground node GND and the ground pin 2, one of the impedance devices 60 is coupled between the enable node IN and the enable pin 4, and one of the impedance devices 60 is coupled between the power node VCC and the power supply between pins 5.

Specifically, the switching function of the analog switch 30 is realized by, for example, a MOS transistor. Figure 9 is an equivalent circuit diagram of the analog switch 30. Referring to Figure 9, the gate and source of the MOS tube form a parasitic capacitance C _gs . The gate and drain of the MOS tube form a parasitic capacitance C _gd . The source and drain of the MOS tube form a parasitic capacitance C gs . The first input node _NO and the ground node GND form a parasitic capacitance C _no , the second input node NC and the ground node GND form a parasitic capacitance C _nc , and the common node COM and the ground node GND form a parasitic capacitance C _com . That is to say, the analog switch 30 includes multiple parasitic capacitances inside. The size of the parasitic capacitance affects the edge time of the signal. The main limitation of low-speed analog switches is that the internal parasitic capacitance is relatively large. The large parasitic capacitance causes serious attenuation of high-speed signals and affects the transmission of high-speed signals. In the embodiment of the present application, the impedance device 60 is disposed between the ground node GND and the ground pin 2, the enable node IN and the enable pin 4, and between the power node VCC and the power pin 5. By increasing the impedance of the high-frequency path through the impedance device 60 , the path of high-speed signals through the ground node GND and ground pin 2, the path between enable node IN and enable pin 4, and the path between power node VCC and power pin 5 can be reduced. The path leaks, so that even if the analog switch 30 used is a low-speed analog switch, high-speed signals can be transmitted through the low-speed analog switch.

On this basis, for example, referring to FIG. 10 and FIG. 11 , when the external device connected to the external interface 40 is the computer 200 , the transmission of the high-speed USB signal can be completed through the switch circuit 50 including the low-speed analog switch 30 . Referring to FIG. 12 , when the external device connected to the external interface 40 is the earphone 300 , the audio analog signal transmission can also be completed through the switch circuit 50 including the low-speed analog switch 30 . And, referring to FIG. 13 , when the external device connected to the external interface 40 is the test device 400 , the transmission of the low-speed debugging signal can also be completed through the switch circuit 50 including the low-speed analog switch 30 .

In this application, when the switch circuit 50 is disposed in the electronic device 100, the analog switch 30 of the switch circuit 50 can be a low-speed analog switch. That is to say, the connection between the electronic device 100 and the external device is completed through the switch circuit 50 including the low-speed analog switch. By transmitting high-speed signals between them, the cost of the electronic device 100 can be reduced.

It should be noted that the above-mentioned analog switch 30 is not limited to a low-speed analog switch. The analog switch 30 can also be a high-speed analog switch. When the analog switch 30 in the switch circuit 50 is a high-speed analog switch, the switch circuit 50 can also be applied to Higher frequency scenarios support the transmission of higher speed signals.

It should be noted that not only the transmission of high-speed signals between the electronic device 100 and the external device can be completed through the switch circuit 50 including a low-speed analog switch, but also the transmission of high-speed signals within the electronic device 100 can be completed through the switch circuit 50 including a low-speed analog switch. etc., the embodiments of the present application do not limit the application scenarios of the switch circuit 50 .

In addition, as for the setting position of the impedance device 60, the above example only shows one setting position of the impedance device 60, that is, as shown in Figure 8, the impedance device 60 is set between the ground node GND and the ground pin 2, and the enable node An impedance device 60 is disposed between IN and enable pin 4, and an impedance device 60 is disposed between power node VCC and power pin 5. However, this does not constitute a limitation of the present application. When high-speed signals are transmitted through the analog switch 30, as long as the signal leakage can be reduced.

In some possible implementations, the impedance device 60 is coupled between only one of the pins and the node corresponding to the pin.

In one example, referring to FIG. 14 , impedance device 60 is coupled between ground node GND and ground pin 2 . The high-frequency path impedance is increased through the impedance device 60 between the ground node GND and the ground pin 2, thereby preventing high-speed signals from leaking through the path between the ground node GND and the ground pin 2.

In yet another example, referring to FIG. 15 , impedance device 60 is coupled between power node VCC and power pin 5 . The high-frequency path impedance is increased through the impedance device 60 between the power node VCC and the power pin 5, thereby preventing high-speed signals from leaking through the path between the power node VCC and the power pin 5.

In yet another example, referring to FIG. 16 , impedance device 60 is coupled between enable node IN and enable pin 4 . The high-frequency path impedance is increased through the impedance device 60 between the enable node IN and the enable pin 4, thereby preventing high-speed signals from leaking through the path between the enable node IN and the enable pin 4.

In some possible implementations, the impedance device 60 is coupled between one of the pins and the node corresponding to the pin; and between the other pin and the node corresponding to the pin.

In one example, referring to FIG. 17 , the impedance device 60 is coupled between the ground node GND and the ground pin 2 , and the impedance device 60 is coupled between the enable node IN and the enable pin 4 . The high-frequency path impedance is increased through the impedance device 60 between the ground node GND and the ground pin 2, thereby preventing high-speed signals from leaking through the path between the ground node GND and the ground pin 2. The high-frequency path impedance is increased through the impedance device 60 between the enable node IN and the enable pin 4, thereby preventing high-speed signals from leaking through the path between the enable node IN and the enable pin 4.

In yet another example, referring to FIG. 18 , the impedance device 60 is coupled between the ground node GND and the ground pin 2 , and the impedance device 60 is coupled between the power node VCC and the power pin 5 . The high-frequency path impedance is increased through the impedance device 60 between the ground node GND and the ground pin 2, thereby preventing high-speed signals from leaking through the path between the ground node GND and the ground pin 2. The high-frequency path impedance is increased through the impedance device 60 between the power node VCC and the power pin 5, thereby preventing high-speed signals from leaking through the path between the power node VCC and the power pin 5.

In yet another example, referring to FIG. 19 , the impedance device 60 is coupled between the enable node IN and the enable pin 4 , and the impedance device 60 is coupled between the power node VCC and the power pin 5 . The high-frequency path impedance is increased through the impedance device 60 between the enable node IN and the enable pin 4, thereby preventing high-speed signals from leaking through the path between the enable node IN and the enable pin 4. The high-frequency path impedance is increased through the impedance device 60 between the power node VCC and the power pin 5, thereby preventing high-speed signals from leaking through the path between the power node VCC and the power pin 5.

It should be noted that the following examples all assume that the impedance device 60 is disposed between the ground node GND and the ground pin, the impedance device 60 is disposed between the enable node IN and the enable pin, and the impedance device 60 is disposed between the power node VCC and the power pin. The impedance device 60 is provided as an example.

In addition, regarding the type of the impedance device 60 , the embodiment of the present application does not limit the type of the impedance device 60 .

In some possible implementations, see FIG. 20 , the impedance device 60 is, for example, an inductor. However, this does not constitute a limitation of the present application. As long as the device can increase the impedance on the path, it is within the protection scope of the present application. For example, the impedance device 60 may also be a combination of an inductor and a capacitor or a magnetic bead.

In addition, regarding the impedance value of the impedance device 60 , the embodiment of the present application does not limit the impedance value of the impedance device 60 . In some possible implementations, the impedance value of the impedance device 60 may be greater than 600 ohms, for example. When the impedance value of the impedance device 60 is greater than 600 ohms, it can better prevent high-speed signals from leaking through the path between the ground node GND and the ground pin 2, and prevent high-speed signals from leaking through the path between the enable node IN and the enable pin 4, and , to prevent high-speed signals from leaking through the path between the power node VCC and power pin 5.

It should be noted that the above example only takes the example that the analog switch 30 includes a switch inside and the transmitted signal is a single-ended signal. Optionally, the analog switch 30 may also include a multi-way switch inside, and the signals transmitted through the analog switch 30 are differential signals. For example, the analog switch 30 internally includes M switches, where M is a positive integer greater than or equal to 2. Then the analog switch 30 may include, for example, 2M input pins, M enable pins, and M common pins.

In some possible implementation methods, see FIG. 21 , for example, the analog switch 30 includes two switches internally. The analog switch 30 includes a first input pin 1, a second input pin 2, a ground pin 3, a third input pin 4, a fourth input pin 5, a first enable pin 6, and a first common pin. 7. Power pin 8, second enable pin 9 and second common pin 10. The switching circuit 50 includes the analog switch 30 . In addition, the switch circuit 50 also includes an enable node IN, a power node VCC, a common node COM, a ground node GND, and an input node N. The input node N includes a first input node NO1, a second input node NO2, a third input node NC1, and a fourth input node NC2. The enabled node IN includes a first enabled node IN1 and a second enabled node IN2. The common node COM includes a first common node COM1 and a second common node COM2. The first input pin 1 is coupled to the first input node NO1, the second input pin 2 is coupled to the third input node NC1, the ground pin 3 is coupled to the ground node GND, and the third input pin 4 is coupled to the fourth input node NC2 Coupling, the fourth input pin 5 is coupled to the second input node NO2, the first enable pin 6 is coupled to the first enable node IN1, the first common pin 7 is coupled to the first common node COM1, and the power supply pin 8 It is coupled with the power node VCC, the second enable pin 9 is coupled with the second enable node IN2, and the second common pin 10 is coupled with the second common node COM2.

For example, the external interface 40 is USB 2.0. The USB signal includes a positive differential signal USB_DP and a negative differential signal USB_DP. The low-speed analog analog signal includes a left channel signal L and a right channel signal R.

For example, when the transmitted signals are the positive differential signal USB_DP and the negative differential signal USB_DP, the first input node NO1 transmits the received positive differential signal USB_DP to the first input pin 1, and the first enable node IN1 transmits the received positive differential signal USB_DP to the first input pin 1. The first enable voltage is transmitted to the first enable pin 6 to control the first common pin 7 to be conductive with the first input pin 1. The positive differential signal USB_DP is transmitted to the first common node COM1 through the analog switch 30 to It is transmitted to an external device (such as a computer) through the first public node COM1. At the same time, the second input node NO2 transmits the received negative differential signal USB_DP to the fourth input pin 5, and the second enable node IN2 transmits the received second enable voltage to the second enable pin 9 to control the fourth enable pin 9. The two common pins 10 and the fourth input pin 5 are connected, and the negative differential signal USB_DP is transmitted to the second common node COM2 through the analog switch 30 to be transmitted to the external device through the second common node COM2. Thus realizing the transmission of USB signals.

When the transmitted signals are the left channel signal L and the right channel signal R, the third input node NC1 transmits the received left channel signal L to the second input pin 2, and the first enable node IN1 receives the first The enable voltage is transmitted to the first enable pin 6 to control the conduction of the first common pin 7 and the second input pin 2. The left channel signal L is transmitted to the first common node COM1 through the analog switch 30 to pass The first common node COM1 transmits to an external device (for example, a headset). At the same time, the fourth input node NC2 transmits the received right channel signal R to the third input pin 4, and the second enable voltage received by the second enable node IN2 is transmitted to the second enable pin 9 to control the third enable pin 9. The two common pins 10 are connected to the third input pin 4, and the right channel signal R is transmitted to the second common node COM2 through the analog switch 30, so as to be transmitted to the external device through the second common node COM2. Thus realizing the transmission of audio analog signals.

In this way, when the switch circuit 50 is disposed in the electronic device 100, since the analog switch 30 of the switch circuit 50 can be a low-speed analog switch, that is, the switch circuit 50 including the low-speed analog switch completes the processing of high-speed differential signals in the electronic device 100. Transmit, or complete the transmission of high-speed differential signals between the electronic device 100 and an external device, so that the cost of the electronic device 100 can be reduced.

In addition, when the signal transmitted by the analog switch 30 is a differential signal, in order to reduce the mutual coupling within the analog switch 30, the high-speed differential signal can also be transmitted to two independent low-speed analog switches. Optionally, the two low-speed Analog switches can be in close proximity. That is to say, the switch circuit 50 may only include one analog switch 30 , for example, see FIG. 8 , but this does not limit the application. The switch circuit 50 may also include L analog switches, where L is a positive integer greater than or equal to 2. .

In some possible implementations, referring to FIG. 22 , the switch circuit 50 includes two analog switches 30 . The two analog switches 30 include a first analog switch 31 and a second analog switch 32 . For example, the first analog switch 31 and the second analog switch 32 have the same structure as the analog switch 30 in the corresponding embodiment of FIG. 2. For details, please refer to the description of each pin of the analog switch 30 in FIG. 2, which will not be described again here. The switch circuit 50 also includes an enable node IN, a power node VCC, a common node COM, a ground node GND, and an input node N. The input node N includes a first input node NO1, a second input node NO2, a third input node NC1, and a fourth input node NC2. The enabled node IN includes a first enabled node IN1 and a second enabled node IN2. The common node COM includes a first common node COM1 and a second common node COM2. The ground node GND includes a first ground node GND1 and a second ground node GND2. The power supply node VCC includes a first power supply node VCC1 and a second power supply node VCC2. The first input pin 1 corresponding to the first analog switch 31 is coupled to the first input node NO1, the ground pin 2 corresponding to the first analog switch 31 is coupled to the first ground node GND1, and the second input corresponding to the first analog switch 31 Pin 2 is coupled to the third input node NC1, the enable pin 4 corresponding to the first analog switch 31 is coupled to the first enable node IN1, and the power supply pin 5 corresponding to the first analog switch 31 is coupled to the first power node VCC1 , the common pin 6 corresponding to the first analog switch 31 is coupled to the first common node COM1. The first input pin 1 corresponding to the second analog switch 32 is coupled to the fourth input node NC2, the ground pin 2 corresponding to the second analog switch 32 is coupled to the second ground node GND2, and the second input corresponding to the second analog switch 32 Pin 3 is coupled to the second input node NO2, the enable pin 4 corresponding to the second analog switch 32 is coupled to the second enable node IN2, and the power supply pin 5 corresponding to the second analog switch 32 is coupled to the second power node VCC2. , the common pin 6 corresponding to the second analog switch 32 is coupled to the second common node COM2.

For example, the external interface 40 is USB 2.0. The USB signal includes a positive differential signal USB_DP and a negative differential signal USB_DP. The low-speed analog analog signal includes a left channel signal L and a right channel signal R.

For example, when the transmitted signals are the positive differential signal USB_DP and the negative differential signal USB_DP, the first input node NO1 transmits the received positive differential signal USB_DP to the first input pin 1 of the first analog switch 31, and the first input node NO1 transmits the received positive differential signal USB_DP to the first input pin 1 of the first analog switch 31. The first enable voltage received by the energy node IN1 is transmitted to the enable pin 4 of the first analog switch 31 to control the common pin 6 of the first analog switch 31 to conduct with the first input pin 1, and the positive differential signal USB_DP It is transmitted to the first common node COM1 through the analog switch 30, so as to be transmitted to an external device (such as a computer) through the first common node COM1. At the same time, the second input node NO2 transmits the received negative differential signal USB_DP to the second input pin 3 of the second analog switch 32 , and the second enable voltage received by the second enable node IN2 is transmitted to the second analog switch 32 . Enable pin 4 to control the common pin 6 of the second analog switch 32 to be conductive with the second input pin 3 of the second analog switch 32, and the negative differential signal USB_DP is transmitted to the second common node COM2 through the analog switch 30, to transmit to the external device through the second public node COM2. Thus realizing the transmission of USB signals.

When the transmitted signals are the left channel signal L and the right channel signal R, the third input node NC1 transmits the received left channel signal L to the second input pin 3 of the first analog switch 31, and the first enable The first enable voltage received by node IN1 is transmitted to the enable pin 4 of the first analog switch 31 to control the common pin 6 of the first analog switch 31 and the second input pin 3 to conduct, and the left channel signal L It is transmitted to the first common node COM1 through the analog switch 30, so as to be transmitted to an external device (for example, a headset) through the first common node COM1. At the same time, the fourth input node NC2 transmits the received right channel signal R to the first input pin 1 of the second analog switch 32 , and the second enable voltage received by the second enable node IN2 is transmitted to the second analog switch 32 The enable pin 4 is used to control the common pin 6 of the second analog switch 32 to be connected with the first input pin 1. The right channel signal R is transmitted to the second common node COM2 through the analog switch 30 to pass through the second common node COM2. The public node COM2 transmits to external devices. Thus realizing the transmission of audio analog signals.

In addition, when the signal transmitted by the analog switch 30 is a differential signal, in the above example (see FIG. 22 ), the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31 , and the impedance device 60 is coupled Between the first enable node IN1 and the enable pin 4 of the first analog switch 31, the impedance device 60 is coupled between the first power node VCC1 and the power pin 5 of the first analog switch 31, and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32, and the impedance device 60 is coupled between the second enable node IN2 and the enable pin 4 of the second analog switch 32. The impedance device 60 is coupled between the second power node VCC2 and the power pin 5 of the second analog switch 32 for illustration. As can be seen from the foregoing content, the impedance device 60 can also be coupled only between one of the pins and the node corresponding to the pin; or, the impedance device 60 can be coupled between one of the pins and the node corresponding to the pin; and, between another pin and the node corresponding to that pin. In this case, optionally, the number of impedance devices 60 corresponding to the first analog switch 31 and the second analog switch 32 is the same, the type of the impedance device 60 is the same, and the position of the impedance device 60 is the same, that is to say, the impedance device 60 is the same. The corresponding pins and nodes of device 60 are the same.

For example, referring to FIG. 23 , when the impedance device 60 is only coupled between one of the pins and the node corresponding to the pin, the impedance device 60 is coupled to the first ground node GND1 and the ground pin 2 of the first analog switch 31 between them, and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32 .

For another example, referring to Figure 24, when the impedance device 60 is coupled between one of the pins and the node corresponding to the pin; and when the impedance device 60 is coupled between the other pin and the node corresponding to the pin. , the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31 , and the impedance device 60 is coupled between the first enable node IN1 and the enable pin 4 of the first analog switch 31 , and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32 , and the impedance device 60 is coupled between the second enable node IN2 and the enable pin 4 of the second analog switch 32 between.

This arrangement is because the impedance device 60 corresponding to each analog switch 30 has the same impact (preventing signal leakage) on the differential signal (positive differential signal USB_DP and negative differential signal USB_DP), thereby improving signal reliability.

As mentioned above, the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still make the foregoing technical solutions. The technical solutions described in each embodiment may be modified, or some of the technical features may be equivalently replaced; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions in each embodiment of the present application.

Claims (11)

1. A switching circuit, characterized in that it includes: at least two analog switches, input nodes, power nodes, ground nodes, enable nodes, and common nodes; At least two of the analog switches include a first analog switch and a second analog switch; The input node includes a first input node, a second input node, a third input node, and a fourth input node, the enabling node includes a first enabling node and a second enabling node, and the common node includes a first a common node and a second common node, the ground node includes a first ground node and a second ground node, the power node includes a first power node and a second power node; the first analog switch and the second analog Each switch includes a first input pin, a second input pin, a power pin, a ground pin, an enable pin, and a common pin; In the first analog switch, the first input pin is coupled to the first input node, the ground pin is coupled to the first ground node, and the second input pin is coupled to the third The input node is coupled, the enable pin is coupled with the first enable node, the power pin is coupled with the first power node, and the common pin is coupled with the first common node; In the second analog switch, the first input pin is coupled to the fourth input node, the ground pin is coupled to the second ground node, and the second input pin is coupled to the second The input node is coupled, the enable pin is coupled with the second enable node, the power pin is coupled with the second power node, and the common pin is coupled with the second common node; The first input node is used to receive a positive differential signal; the first enable node is used to receive a first enable voltage, and transmit the first enable voltage to the first enable node coupled to the Enable the pin, so that the common pin coupled to the first common node and the first input pin coupled to the first input node are turned on; the common pin coupled to the first common node is used to transmitting the positive differential signal to the first common node; The second input node is used to receive a negative differential signal; the second enable node is used to receive a second enable voltage, and transmit the second enable voltage to the second enable node coupled to the second enable node. Enable the pin, so that the common pin coupled to the second common node and the second input pin coupled to the second input node are turned on; the common pin coupled to the second common node is used to transmitting the negative differential signal to the second common node; The switch circuit further includes: at least one impedance device; the at least one impedance device includes a first impedance device and a second impedance device, the first impedance device is coupled to the first enable node and the first analog switch. between enable pins, the second impedance device is coupled between the second enable node and the enable pin of the second analog switch; The impedance device includes an inductor, a magnetic bead, or a combination of an inductor and a capacitor. 2. The switch circuit according to claim 1, wherein the number of the impedance devices corresponding to the first analog switch and the number of the impedance devices corresponding to the second analog switch are the same. 3. The switch circuit according to claim 1 or 2, characterized in that the position of the impedance device corresponding to the first analog switch and the position of the impedance device corresponding to the second analog switch are the same. 4. The switching circuit according to claim 1 or 2, characterized in that the switching speed of the analog switch is less than or equal to 100 MHz. 5. The switching circuit according to claim 1 or 2, characterized in that the impedance value of the impedance device is greater than 600 ohms. 6. The switching circuit according to claim 1 or 2, characterized in that at least one impedance device further includes: a third impedance device, a fourth impedance device, a fifth impedance device and a sixth impedance device; the third impedance device The device is coupled between the first ground node and the ground pin of the first analog switch, and the fourth impedance device is coupled between the first power node and the power pin of the first analog switch. , the fifth impedance device is coupled between the second ground node and the ground pin of the second analog switch, and the sixth impedance device is coupled between the second power node and the second between the power pins of the analog switch. 7. A switching circuit, characterized in that it includes: at least one analog switch, input node, power node, ground node, enable node, and common node; The analog switch includes two switches inside; the analog switch includes a first input pin, a second input pin, a third input pin, a fourth input pin, a ground pin, a first enable pin, the second enable pin, the first common pin, the second common pin and the power pin; The input node includes a first input node, a second input node, a third input node, and a fourth input node, the enabling node includes a first enabling node and a second enabling node, and the common node includes a first common node and second common node; The first input pin is coupled to the first input node, the second input pin is coupled to the third input node, the ground pin is coupled to the ground node, and the third input tube The fourth input pin is coupled to the fourth input node, the fourth input pin is coupled to the second input node, the first enable pin is coupled to the first enable node, and the first common tube The pin is coupled to the first common node, the power pin is coupled to the power node, the second enable pin is coupled to the second enable node, the second common pin is coupled to the Second common node coupling; The first input node is used to receive a positive differential signal; the first enable node is used to receive a first enable voltage and transmit the first enable voltage to the first enable pin. , so that the first common pin is connected to the first input pin; the first common pin is used to transmit the positive differential signal to the first common node; The second input node is used to receive a negative differential signal; the second enable node is used to receive a second enable voltage and transmit the second enable voltage to the second enable pin. , so as to conduct the second common pin and the fourth input pin coupled to the second input node; the second common pin is used to transmit the negative differential signal to the second common node; The switch circuit also includes: at least one impedance device; the at least one impedance device includes a first impedance device and a second impedance device, the first impedance device is coupled to the first enable node and the first enable tube between the pins, the second impedance device is coupled between the second enable node and the second enable pin; The impedance device includes an inductor, a magnetic bead, or a combination of an inductor and a capacitor. 8. The switching circuit according to claim 7, wherein the switching speed of the analog switch is less than or equal to 100 MHz. 9. The switching circuit according to claim 7 or 8, characterized in that the impedance value of the impedance device is greater than 600 ohms. 10. The switching circuit according to claim 7 or 8, wherein at least one impedance device further includes: a third impedance device and a fourth impedance device; the third impedance device is coupled between the ground node and the Between ground pins, the fourth impedance device is coupled between the power node and the power pins. 11. An electronic device, characterized by comprising the switch circuit according to any one of claims 1-10.