CN116013850A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN116013850A CN116013850A CN202211591570.3A CN202211591570A CN116013850A CN 116013850 A CN116013850 A CN 116013850A CN 202211591570 A CN202211591570 A CN 202211591570A CN 116013850 A CN116013850 A CN 116013850A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor structure at least comprises: the substrate is sequentially provided with a connecting layer, a contact hole etching stop layer, an interlayer dielectric layer and a multi-layer doping layer; a first concave portion provided in the doped layer and having a radial length gradually decreasing from an opening side to a bottom wall side of the first concave portion; the second concave part extends into part of the interlayer dielectric layer, and the side wall of the second concave part is vertically arranged; a third recess portion provided at the bottom of the second recess portion, the third recess portion extending into a portion of the connection layer, the radial length of the third recess portion gradually decreasing from an opening side to a bottom wall side of the third recess portion; and a conductive structure disposed in the first recess, the second recess, and the third recess. The manufacturing method of the semiconductor structure provided by the invention can improve the electrical performance of the semiconductor device.
Description
Technical Field
The invention belongs to the field of semiconductor structure manufacturing, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
As chip integration increases and feature sizes decrease, the Aspect Ratio (AR) of the contact hole becomes larger. When metal is deposited in the contact hole, if the contact hole process window is not optimized enough, a thin seam is easily formed after the contact hole is filled, and in serious cases, a large cavity can be caused to influence the performance of the device, even the device is disabled. And when the key size of the contact hole is too small, the filling abnormality of the contact hole is easy to be caused, and the electrical performance of the device is further affected.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, which can avoid forming a cavity in a contact hole and improve the electrical performance of a semiconductor device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a manufacturing method of a semiconductor structure, which at least comprises the following steps:
a substrate;
a connection layer disposed on the substrate;
the contact hole etching stop layer is arranged on the connecting layer;
the interlayer dielectric layer is arranged on the contact hole etching stop layer;
the multi-layer doping layer is arranged on the interlayer dielectric layer;
a first concave portion provided in the doped layer and having a radial length gradually decreasing from an opening side to a bottom wall side of the first concave portion;
the second concave part is arranged at the bottom of the first concave part, the first concave part extends into part of the interlayer dielectric layer, and the side wall of the second concave part is vertically arranged;
the third concave part is arranged at the bottom of the second concave part, penetrates through the interlayer dielectric layer, the contact hole etching stop layer and part of the connecting layer, and gradually reduces in radial length from one side of an opening of the third concave part to one side of a bottom wall; and
and a conductive structure disposed in the first recess, the second recess, and the third recess.
In an embodiment of the present invention, the conductive structure is located on the doped region, and a bottom of the second recess is located on a plane higher than a plane on which a top of the gate is located.
In an embodiment of the invention, a side wall of the first recess is disposed in an arc shape.
In an embodiment of the invention, the inclination angle of the first recess side wall is larger than the inclination angle of the third recess side wall.
In an embodiment of the present invention, the semiconductor structure further includes a hard mask layer, and the hard mask layer is located on the doped layer.
The invention also provides a manufacturing method of the semiconductor structure, which at least comprises the following steps:
providing a substrate, wherein a connecting layer, a contact hole etching stop layer and an interlayer dielectric layer are sequentially arranged on the substrate;
a plurality of doped layers are arranged on the interlayer dielectric layer;
etching the doped layer to form a first concave part, wherein the radial length of the first concave part gradually decreases from one side of an opening of the first concave part to one side of a bottom wall;
etching part of the interlayer dielectric layer at the bottom of the first concave part to form a second concave part, wherein the side wall of the second concave part is vertically arranged;
etching the interlayer dielectric layer, the contact hole etching stop layer and part of the connecting layer at the bottom of the second concave part to form a third concave part, wherein the radial length of the third concave part gradually decreases from one side of an opening of the third concave part to one side of a bottom wall of the third concave part; and
and depositing conductive materials in the first concave part, the second concave part and the third concave part to form a conductive structure.
In an embodiment of the present invention, as the height of the doped layer increases, the ion doping concentration in the doped layer increases.
In one embodiment of the present invention, the doped layer is etched by means of reactive ion etching.
In an embodiment of the present invention, a portion of the interlayer dielectric layer at the bottom of the first recess is etched by plasma etching to form the second recess, and the interlayer dielectric layer, the contact hole etching stop layer and a portion of the connection layer at the bottom of the second recess are etched to form a third recess.
In one embodiment of the present invention, the ratio of etching gas is constant during the formation of the second recess, and the ratio of etching source power to bias power is constant.
In an embodiment of the present invention, in the process of forming the third recess, as the etching depth increases, the ratio of fluorocarbon gas and oxygen gas is reduced, or the ratio of source power to bias power is reduced.
In summary, in the semiconductor structure and the manufacturing method thereof provided by the invention, the top of the contact hole is set to be the first concave part with the contracted bottom when the conductive structure is formed, so that the contact hole has a larger top size, which is beneficial to the subsequent metal filling. The middle part of the contact hole is arranged to be a second concave part close to the vertical side wall, which meets the size of the design requirement and meets the electrical requirement of the semiconductor device. Providing the contact hole bottom as a third recess with a shrinking bottom reduces the risk of bridging the contact hole with the gate. By the semiconductor structure and the manufacturing method thereof, the formation of a cavity in the contact hole can be avoided, and the electrical performance of the semiconductor device is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a structure of a connection layer, a contact hole etching stop layer and an interlayer dielectric layer formed on a substrate in an embodiment.
FIG. 2 is a schematic diagram of a doped layer formed in an embodiment.
FIG. 3 is a schematic diagram illustrating a structure of forming a patterned photoresist layer according to an embodiment.
FIG. 4 is a schematic diagram of a structure for forming a patterned hard mask layer in one embodiment.
Fig. 5 is a schematic structural view of forming a first recess in an embodiment.
Fig. 6 is a schematic structural view of forming a second concave portion in an embodiment.
Fig. 7 is a schematic structural view of forming a third recess in an embodiment.
Fig. 8 is a schematic structural diagram of a contact hole in an embodiment.
Fig. 9 is a schematic structural diagram of an adhesion layer formed in an embodiment.
FIG. 10 is a schematic diagram of a structure for forming a barrier layer in an embodiment.
FIG. 11 is a schematic diagram of a structure for forming a conductive structure in an embodiment.
Fig. 12 is a schematic structural diagram of forming a conductive structure in a contact hole in an embodiment.
Fig. 13 is a schematic diagram showing a structure of a semiconductor integrated device in an embodiment.
Description of the reference numerals:
101. a substrate; 102. a connection layer; 103. a contact hole etch stop layer; 104. an interlayer dielectric layer; 105. a doped layer; 1051. a first doped layer; 1052. a second doped layer; 1053. a third doped layer; 1054. a fourth doped layer; 106. a hard mask layer; 1061. a second opening; 107. patterning the photoresist layer; 1071. a first opening; 108. an adhesive layer; 109. a barrier layer; 110. a conductive structure; 111. a contact hole; 1111. a first concave portion; 1112. a second concave portion; 1113. a third recess; 112. and a gate.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
With the development of semiconductor integrated circuits, it is required to simultaneously form a plurality of individual or connected semiconductor devices on the same silicon wafer. The semiconductor device comprises one or more semiconductor devices including but not limited to a field effect transistor, a metal-oxide semiconductor field effect transistor, a complementary metal oxide semiconductor, an insulated gate bipolar transistor, a high-speed recovery diode, a high-speed high-efficiency rectifier diode, a constant voltage diode, a high-frequency diode, a light emitting diode, a gate light-blocking thyristor, a light triggering thyristor, a charge coupler, a digital signal processing device, an optical relay or a microprocessor. After forming the semiconductor device, a plurality of conductive structures need to be formed on the semiconductor device for connecting the semiconductor device with the metal interconnect structure.
Referring to fig. 1 to 13, the present invention provides a semiconductor structure and a method for manufacturing the same, which can form a high-quality conductive structure 110 in a contact hole 111 with a larger aspect ratio, thereby improving the reliability of the semiconductor structure and prolonging the service life of the semiconductor structure.
Referring to fig. 1, in an embodiment of the present invention, a substrate 101 is provided, and a material of the substrate 101 may be any commonly used substrate material such as undoped monocrystalline silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In some embodiments, the substrate 101 is formed from a single crystal silicon. In some embodiments, ions may be implanted in the substrate 101 to form a well region or doped region. An etching or deposition process may also be performed on the substrate 101 to form a plurality of semiconductor devices.
Referring to fig. 1 and 13, in one embodiment of the present invention, the semiconductor device is any semiconductor device that can be integrated. In some embodiments, the semiconductor device includes, for example, a doped region disposed in the substrate 101, and a gate 112 disposed on the substrate 101. Wherein the doped region is disposed in the substrate, for example comprising a source doped region or a drain doped region. In some embodiments, the semiconductor structure provided herein may be the conductive structure 110 formed on the gate 112 and connected to the gate 112, or may be the conductive structure 110 formed on the doped region and connected to the gate 112.
Referring to fig. 1 and 13, in an embodiment of the present invention, a connection layer 102 is further formed on the substrate 101, and the connection layer 102 is, for example, a salicide. Specifically, the connection layer 102 may be disposed on the gate electrode 112 or the doped region. An alloy layer, such as a nickel-platinum alloy layer, may be formed over the gate 112 or doped region. And then annealing is performed to enable nickel in the nickel-platinum alloy layer to react with silicon in the substrate 101 or the grid electrode 112, so as to generate NiSi, namely the connection layer 102. A contact hole etching stop layer 103 is further formed on the connection layer 102, and the contact hole etching stop layer 103 covers the connection layer 102 and the substrate 101. The material of the contact hole etching stop layer 103 may be silicon nitride with high stress, and a layer of silicon nitride may be deposited as the contact hole etching stop layer 103 by using a chemical vapor deposition method.
Referring to fig. 1, in an embodiment of the present invention, an interlayer dielectric layer 104 is formed on the contact hole etching stop layer 103, and the interlayer dielectric layer 104 covers the contact hole etching stop layer 103. The material of the interlayer dielectric layer 104 may be silicon dioxide, and the interlayer dielectric layer 104 may be formed on the contact hole etching stop layer 103 by a high-density plasma chemical vapor deposition method, for example. After the interlayer dielectric layer 104 is formed, a chemical mechanical polishing process may be performed on the interlayer dielectric layer 104, so that the surface of the interlayer dielectric layer 104 is flat. Finally formed interlayer mediumThe thickness of layer 104 is, for example
Referring to fig. 1 and 2, in an embodiment of the present invention, after forming the interlayer dielectric layer 104, a multi-doped layer 105 is formed on the interlayer dielectric layer 104. Wherein the doping material may be silicon oxide, and the thickness of the multi-doped layer 105 is
In the present invention, ions are doped in the doped layer 105, and the ions doped in the doped layer 105 may damage the lattice structure of silicon oxide. As the height of the doped layer 105 increases, the ion doping concentration in the doped layer 105 increases, i.e. the doping concentration of the doped layer 105 closest to the interlayer dielectric layer 104 is lowest, and as the distance from the doped interlayer dielectric layer 104 increases, the doping concentration of the doped layer 105 increases and the doping concentration of the doped layer 105 furthest from the interlayer dielectric layer 104 increases. In this embodiment, the doped ions in doped layer 105 are, for example, fluorine ions F-. And the doping energy of the fluorine ions is in the range of, for example, 10keV to 20keV, and the implantation dose of the fluorine ions is in the range of, for example, 1.5X10 13 atoms/cm 2 ～5.0×10 13 atoms/cm 2 . In other embodiments, the doped ions in the doped layer 105 are, for example, silicon ions si+, carbon ions c+ or oxygen ions o+, but may also be nitrogen ions n+, boron ions b+ or phosphorus ions p+ plasma.
Referring to fig. 2, in some embodiments, ions may be implanted into the multi-layer doped layer 105 by ion implantation, so as to form a multi-layer doped layer 105 with a certain concentration gradient. The number of layers of doped layer 105 is not limited in this application. In some embodiments, for example, 3-5 doped layers 105 are provided. In other embodiments, for example, 6 to 10 doped layers 105, or more doped layers 105, are provided. In the present invention, the number of doped layers 105 is 4, and the first doped layer 1051, the second doped layer 1052, the third doped layer 1053, and the fourth doped layer 1054 are provided on the interlayer dielectric layer 104. A second doped layer 1052 is positioned on the firstOn the doped layer 1051, a third doped layer 1053 is located on the second doped layer 1052, a fourth doped layer 1054 is located on the third doped layer 1053, and the ion doping concentration of the fourth doped layer 1054 is greater than the ion doping concentration of the third doped layer 1053, the ion doping concentration of the third doped layer 1053 is greater than the ion doping concentration of the second doped layer 1052, and the ion doping concentration of the second doped layer 1052 is greater than the ion doping concentration of the first doped layer 1051. In this embodiment, the implantation dose range of the fluorine ions in the first doped layer 1051 is, for example, 1.5X10 13 atoms/cm 2 ～2.0×10 13 atoms/cm 2 . The implantation dose range of the fluorine ion in the second doping layer 1052 is, for example, 2.0x10 13 atoms/cm 2 ～3.0×10 13 atoms/cm 2 . The implantation dose range of the fluorine ion in the third doped layer 1053 is, for example, 3.0x10 13 atoms/cm 2 ～4.0×10 13 atoms/cm 2 . The implantation dose range of the fluorine ion in the fourth doped layer 1054 is, for example, 4.0X10 13 atoms/cm 2 ～5.0×10 13 atoms/cm 2 。
Referring to fig. 2 to 4, in an embodiment of the present invention, after forming the multi-layered doped layer 105, a patterned hard mask layer 106 is formed on the doped layer 105. Specifically, a hard mask layer 106 may be formed on the doped layer 105, and a patterned photoresist layer 107 may be formed on the hard mask layer 106. On the patterned photoresist layer 107, a first opening 1071 is provided, which first opening 1071 exposes the hard mask layer 106 where the hard mask layer 106 needs to be etched, i.e. exposes the hard mask layer 106 over the contact hole 111. After forming the patterned photoresist layer 107, the hard mask layer 106 is etched using the patterned photoresist layer 107 as a mask, thereby forming the patterned hard mask layer 106. In some embodiments, the hard mask layer 106 may be an amorphous carbon (a-C) process, and the hard mask layer 106 may be a single layer or multiple layers depending on the process requirements to achieve the desired process standard. In etching the hard mask layer 106, the hard mask layer 106 may be etched by wet etching or reactive ion etching to form the patterned hard mask layer 106. In this embodiment, at the bottom of the first opening 1071, a second opening 1061 is etched in the hard mask layer 106, where the second opening 1061 exposes the contact hole 111. After etching the hard mask layer 106, the patterned photoresist layer 107 may be removed.
Referring to fig. 4 to 8, in an embodiment of the present invention, after forming the patterned hard mask layer 106, the doped layer 105, the interlayer dielectric layer 104, the contact hole etching stop layer 103 and a portion of the connection layer 102 are etched in sequence at the position of the second opening 1061, so as to form a contact hole 111. Specifically, the contact hole 111 includes a first recess 1111 formed by etching the doped layer 105, a second recess 1112 formed by etching a part of the interlayer dielectric layer 104, and a third recess 1113 formed by etching the interlayer dielectric layer 104, the contact hole etch stop layer 103, and a part of the connection layer 102.
Referring to fig. 5, in an embodiment of the invention, the doped layer 105 is etched by reactive ion etching to form a first recess 1111. In the case of reactive ion etching, the etching gas is, for example, fluorocarbon gas (C X F Y ) With oxygen (O) 2 ) Is a mixed gas of (a) and (b). Wherein the fluorocarbon gas (C X F Y ) In which X is in the range of, for example, 2 to 4, and Y is in the range of, for example, 2 to 8, the etching gas may be hexafluoroethane (C 2 F 6 ) Or octafluoropropane (C) 3 F 8 ) And fluorocarbon gas. In the present application, the etching rate increases when the doped layer 105 is etched using a gas, because the doped ions in the doped layer 105 may cause a lattice structure in the silicon oxide doped layer 105 to be broken. And the ion doping concentration in the doping layer 105 gradually decreases from the fourth doping layer 1054 at the uppermost layer to the first doping layer 1051 at the lowermost layer. During the etching process of the doped layer 105, the etching rate decreases with the decrease of the ion doping concentration in the doped layer 105, so that a first recess 1111 with a gradually-changed radial length of the opening is formed in the multi-layered doped layer 105. In this application, the radial length of the top of the first recess 1111 is greater than the radial length of the bottom. The radial length of the first concave portion 1111 gradually decreases from the opening side to the bottom wall side of the first concave portion 1111, and the side wall of the first concave portion 1111 is arranged in an arc shape.
Referring to FIG. 5, in some embodiments, a first recess 1111 is formed in the etch doped layer 105In the process, fluorocarbon gas (C) X F Y ) With oxygen (O) 2 ) The flow ratio is adjusted to control the lateral etching rate of the first recess 1111, adjusting the radial length of the first recess 1111. Specific fluorocarbon gas (C X F Y ) With oxygen (O) 2 ) The flow ratio may be set according to the critical dimensions of the contact hole 111, without being too limited in this application.
Referring to fig. 5 and 6, in an embodiment of the present invention, after the first recess 1111 is formed, a portion of the interlayer dielectric layer 104 at the bottom of the first recess 1111 is etched by plasma etching to form a second recess 1112. In the case of plasma etching, the etching gas is fluorocarbon gas (C X F Y ) And oxygen (O) 2 ) And introducing fluorocarbon gas (C) X F Y ) And oxygen (O) 2 ) Simultaneously, argon (Ar) is also introduced. In the case of using fluorocarbon gas (C X F Y ) And a certain physical bombardment etching is provided at the same time of etching, so that a better anisotropic etching effect can be achieved. In the present application, during the process of etching the second recess 1112, the ratio of etching gas is unchanged, and the ratio of source power to bias power of etching is also unchanged, so that the second recess 1112 is formed as a recess with vertical sidewalls. In this embodiment, the bottom of the second recess 1112 has a predetermined distance from the bottom of the interlayer dielectric layer 104, which is not limited by the present invention. Specifically, as shown in fig. 13, when the contact hole 111 is formed on the doped region, the bottom of the second recess 1112 is located on the horizontal plane where the top of the gate 112 is located. At this time, the third recess 1113 with gradually decreasing radial length can increase the space between the conductive structure 110 and the gate 112, and can reduce the leakage current, so as to improve the electrical performance of the semiconductor device. When the contact hole 111 is formed on the gate 112, the distance between the bottom of the second recess 1112 and the top of the gate 112 is larger than, for example
Referring to fig. 6 and 7, in one embodiment of the present invention, after forming the second recess 1112, the etching process is continued by plasmaThe interlayer dielectric layer 104, the contact hole etching stopper layer 103, and a part of the connection layer 102 at the bottom of the second recess 1112 are etched to form a third recess 1113. During the etching of third recess 1113, the same etching gas as that used for etching second recess 1112 is introduced with fluorocarbon gas (C X F Y ) And oxygen (O) 2 ) Simultaneously, argon (Ar) is also introduced. When third recess 1113 is etched, the etching depth gradually decreases in fluorocarbon gas (C X F Y ) And oxygen (O) 2 ) The ratio of gas, or the ratio of source power to bias power, is gradually reduced to form third recess 1113 of gradually decreasing radial length. In this application, third recess 1113 has a top radial length that is greater than a bottom radial length. The radial length of the third recess 1113 gradually decreases from the opening side to the bottom wall side of the third recess 1113, and the side wall of the third recess 1113 is provided in a slope.
Referring to fig. 8, in the present application, the contact hole 111 is formed to include a first recess 1111, a second recess 1112 extending toward the bottom of the first recess 1111, and a third recess 1113 extending toward the bottom of the second recess 1112. And the top of the contact hole 111 is the first concave 1111 with the bottom shrinking, so that the contact hole 111 has a larger top size, which is beneficial to the subsequent metal filling. The middle of the contact hole 111 is a second concave portion 1112 close to the vertical sidewall, which meets the design requirement and meets the electrical requirement of the semiconductor device. The third recess 1113 with the bottom shrinking at the bottom of the contact hole 111 may reduce the risk of bridging the contact hole 111 with the gate 112. In some embodiments, the sidewalls of the first recess 1111 have a greater inclination angle, i.e., a greater top dimension/bottom dimension ratio. In this application, the inclination angle of the side wall of the first recess 1111 ranges from 50 ° to 80 °, and the ratio of the radial dimension of the top of the first recess 1111 to the radial dimension of the bottom ranges from 1.3 to 1.8. The sidewall of third recess 1113 has an inclination angle in the range of 70 ° to 85 °, and the ratio of the radial dimension of the top to the radial dimension of the bottom of third recess 1113 ranges from 1.1 to 1.35.
Referring to fig. 7 and 8, in some embodiments, after forming the contact hole 111, the hard mask layer 106 over the doped layer 105 is removed. Specifically, the hard mask layer 106 may be removed by wet etching or reactive ion etching.
Referring to fig. 8 to 10, in an embodiment of the present invention, after forming the contact hole 111, an adhesion layer 108 is deposited on the sidewall of the contact hole 111, and a barrier layer 109 is deposited on the adhesion layer 108. Wherein the adhesion layer 108 may be a titanium adhesion layer and the barrier layer 109 may be a titanium nitride barrier layer. The blocking layer 109 can prevent the reaction gas from reacting with the adhesion layer 108 during the hole filling process of the contact hole 111, which affects the electrical performance of the contact hole. The adhesion layer 108 can increase the adhesion between the sidewall of the contact hole 111 and the barrier layer 109, so as to avoid the occurrence of voids between the barrier layer 109 and the sidewall of the contact hole 111, which affects the performance of the semiconductor device. In the present application, a layer of titanium (Ti) may be deposited as an adhesion layer in the contact hole 111 by physical vapor deposition, and the adhesion layer 108 has a thickness of, for example
A layer of titanium nitride (TiN) may be deposited as the barrier layer 109 using metal organic chemical vapor deposition, and the thickness of the barrier layer 109 is, for example +.>
While depositing the adhesion layer 108, a build-up of reactants is likely to form at the openings and corners of the contact hole 111, in this application, the build-up of reactants at the openings of the third recess 1113 does not affect the filling of the subsequent contact hole 111, since the openings at the top and bottom of the third recess 1113 are small.
Referring to fig. 10 and 11, in one embodiment of the present invention, after forming the barrier layer 109, a conductive material is deposited in the contact hole 111 to form the conductive structure 110. Specifically, the contact hole 111 may be filled with a conductive material by chemical vapor deposition, and the filled conductive material may be, for example, metal tungsten, or titanium/titanium nitride and metal tungsten. In the present embodiment, for example, tungsten metal is deposited, and the thickness of tungsten metal is
Referring to fig. 11 and 12, in an embodiment of the present invention, after forming the conductive structure 110 in the contact hole 111, the doped layer 105 on the interlayer dielectric layer 104 and the conductive structure 110 in the third recess 1113 are removed. The doped layer 105 and the conductive structure 110 in the third recess 1113 may be removed by chemical mechanical polishing. And after polishing the doped layer 105 and the conductive structure 110 in the third recess 1113, a certain amount of overpolish is performed to ensure that the doped layer 105 is completely removed. In this embodiment, the interlayer dielectric layer 104 is overground to a thickness of
In summary, the present invention provides a method for manufacturing a semiconductor structure, in which a connection layer, a contact hole etching stop layer and an interlayer dielectric layer are sequentially formed on a substrate, a plurality of doped layers with different doping concentrations are formed on the interlayer dielectric layer, and then the doped layers are etched by reactive ion etching to form a first recess with a contracted bottom. And etching the interlayer dielectric layer, the contact hole etching stop layer and part of the connecting layer by adopting plasma, and etching part of the interlayer dielectric layer to form a second concave part close to the vertical side wall. And continuing to etch the interlayer dielectric layer, the contact hole etching stop layer and part of the connecting layer at the bottom of the second concave part to form a third concave part with the contracted bottom, so as to form a complete contact hole. And depositing conductive material in the contact hole to form a conductive structure. The manufacturing method of the semiconductor structure can form a high-quality conductive structure in the contact hole with a larger depth-to-width ratio.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (11)
1. A semiconductor structure, comprising:
a substrate;
a connection layer disposed on the substrate;
the contact hole etching stop layer is arranged on the connecting layer;
the interlayer dielectric layer is arranged on the contact hole etching stop layer;
the multi-layer doping layer is arranged on the interlayer dielectric layer;
a first concave portion provided in the doped layer and having a radial length gradually decreasing from an opening side to a bottom wall side of the first concave portion;
the second concave part is arranged at the bottom of the first concave part, the first concave part extends into part of the interlayer dielectric layer, and the side wall of the second concave part is vertically arranged;
the third concave part is arranged at the bottom of the second concave part, penetrates through the interlayer dielectric layer, the contact hole etching stop layer and part of the connecting layer, and gradually reduces in radial length from one side of an opening of the third concave part to one side of a bottom wall; and
and a conductive structure disposed in the first recess, the second recess, and the third recess.
2. The semiconductor structure of claim 1, wherein the conductive structure is located on the doped region, and wherein a bottom of the second recess is located at a higher level than a top of the gate.
3. The semiconductor structure of claim 1, wherein sidewalls of the first recess are disposed in an arc shape.
4. The semiconductor structure of claim 1, wherein an inclination angle of the first recess sidewall is greater than an inclination angle of the third recess sidewall.
5. The semiconductor structure of claim 1, further comprising a hard mask layer, and wherein the hard mask layer is located on the doped layer.
6. A method of fabricating a semiconductor structure, comprising at least the steps of:
providing a substrate, wherein a connecting layer, a contact hole etching stop layer and an interlayer dielectric layer are sequentially arranged on the substrate;
a plurality of doped layers are arranged on the interlayer dielectric layer;
etching the doped layer to form a first concave part, wherein the radial length of the first concave part gradually decreases from one side of an opening of the first concave part to one side of a bottom wall;
etching part of the interlayer dielectric layer at the bottom of the first concave part to form a second concave part, wherein the side wall of the second concave part is vertically arranged;
etching the interlayer dielectric layer, the contact hole etching stop layer and part of the connecting layer at the bottom of the second concave part to form a third concave part, wherein the radial length of the third concave part gradually decreases from one side of an opening of the third concave part to one side of a bottom wall of the third concave part; and
and depositing conductive materials in the first concave part, the second concave part and the third concave part to form a conductive structure.
7. The method of claim 6, wherein the ion doping concentration in the doped layer increases as the height of the doped layer increases.
8. The method of claim 6, wherein the doped layer is etched by reactive ion etching.
9. The method according to claim 6, wherein the second recess is formed by etching a part of the interlayer dielectric layer at the bottom of the first recess by plasma etching, and the third recess is formed by etching the interlayer dielectric layer, the contact hole etching stopper layer, and a part of the connection layer at the bottom of the second recess.
10. The method of manufacturing a semiconductor structure according to claim 9, wherein a ratio of etching gas is constant during the forming of the second recess, and a ratio of source power to bias power of etching is constant.
11. The method according to claim 9, wherein in forming the third recess, a ratio of fluorocarbon gas to oxygen gas or a ratio of source power to bias power is reduced as an etching depth increases.
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| CN116798952B (en) * | 2023-08-21 | 2023-11-14 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN117995772B (en) * | 2024-04-03 | 2024-06-28 | 深圳市昇维旭技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN119133143A (en) * | 2024-09-03 | 2024-12-13 | 安徽长飞先进半导体股份有限公司 | Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle |
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| JPH11354499A (en) * | 1998-04-07 | 1999-12-24 | Oki Electric Ind Co Ltd | Formation of contact hole |
| CN101459119B (en) * | 2007-12-13 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| SG10201608814YA (en) * | 2015-10-29 | 2017-05-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for manufacturing the semiconductor device |
| CN110120382A (en) * | 2019-05-23 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and forming method |
| CN112635397A (en) * | 2020-12-18 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Method for manufacturing through hole |
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| CN116364658A (en) * | 2023-05-31 | 2023-06-30 | 合肥晶合集成电路股份有限公司 | Fabrication method of semiconductor structure and semiconductor structure |
| CN116364658B (en) * | 2023-05-31 | 2023-08-01 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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