CN116013390B - Memory and reading method thereof - Google Patents

Abstract

The embodiment of the disclosure provides a memory and a reading method thereof, wherein the memory comprises: a fuse array, a control signal generating circuit, and a reading circuit; the control signal generating circuit is configured to receive the reset signal and output a first control signal to the reading circuit based on the reset signal; the reset signal is used for indicating the memory to execute reset operation; the reset signal is inverted from an active level to an inactive level at a first time; the reading circuit is connected with the control signal generating circuit and is configured to start reading fuse data stored in a target fuse unit in the fuse array at a second moment according to the first control signal; there is a time interval between the second time and the first time.

Description

Memory and reading method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a memory and a reading method thereof.

Background

Memories are important components for storing data in various electronic devices, and as integrated circuit technology advances, the precision and complexity of memories are increasing. Various applications have also put increasing demands on the reliability of memories to meet the demands of various application scenarios.

Disclosure of Invention

In view of the above, a primary object of the present disclosure is to provide a memory and a reading method thereof.

In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:

the disclosed embodiments provide a memory, including:

a fuse array, a control signal generating circuit, and a reading circuit;

the control signal generating circuit is configured to receive a reset signal and output a first control signal to the reading circuit based on the reset signal; wherein the reset signal is used for indicating the memory to execute a reset operation; the reset signal is turned over from an active level to an inactive level at a first moment;

the reading circuit is connected with the control signal generating circuit and is configured to start reading fuse data stored in a target fuse unit in the fuse array at a second moment according to the first control signal; a time interval exists between the second time and the first time.

In the above aspect, the control signal generating circuit includes: a first signal generation unit and a second signal generation unit;

the first signal generating unit is configured to receive a second control signal and the reset signal, and generate a first clock signal based on the second control signal and the reset signal; the second control signal is used for indicating that reading of the fuse data is finished;

The second signal generation unit is configured to receive the first clock signal and the reset signal, and generate the first control signal based on the first clock signal and the reset signal.

In the above scheme, the first signal generating unit includes a first inverter, a first logical nor gate, and an oscillator; the first inverter and the first logical nor gate are configured to perform a logical operation on the second control signal and the reset signal, generate a first enable signal, and output the first enable signal to the oscillator for controlling the operation of the oscillator; the oscillator is configured to generate the first clock signal based on the first enable signal.

In the above scheme, the second signal generating unit includes a delay subunit and a signal generating subunit;

the delay subunit is configured to receive the first clock signal, generate and output a second clock signal based on the first clock signal, wherein a clock period of the second clock signal is greater than a clock period of the first clock signal;

the signal generation subunit is configured to receive the second clock signal and the reset signal, generate and output the first control signal based on the second clock signal and the reset signal.

In the above scheme, the delay subunit includes N cascaded flip-flops, where N is an integer greater than or equal to 1; the clock control end of the first-stage trigger is used as the input end of the delay subunit and receives the first clock signal; the inverting output end of each stage of the trigger is connected with the data input end of the trigger; clock control ends of other triggers except the trigger of the first stage are connected with a positive phase output end of the trigger of the previous stage; and the non-inverting output end of the flip-flop of the N-th stage outputs the second clock signal.

In the above scheme, the signal generating subunit includes a pulse signal generating unit, a second inverter, and an RS latch; the pulse signal generating unit is configured to receive the second clock signal, generate and output a first pulse signal based on the second clock signal; the second inverter is configured to receive the reset signal; the output ends of the pulse signal generating unit and the second inverter are connected to the input end of the RS latch, and the RS latch is configured to receive the first pulse signal and the reset signal subjected to logical negation operation, and generate and output the first control signal.

In the above aspect, the control signal generating circuit includes: and the signal detection unit is configured to detect the voltage values of M working voltages in the memory at the first moment according to the reset signal, and enable the first control signal when the voltage values of the M working voltages all reach corresponding reference voltage values, wherein M is an integer greater than or equal to 1.

In the above scheme, the signal detection unit includes M comparators and an and logic circuit; the inverting input end of each comparator is used for receiving the reference voltage, and the non-inverting input end of each comparator is used for receiving one of the M working voltages and outputting a comparison result; the output ends of the M comparators are connected to the input ends of the AND logic circuit, and the AND logic circuit is used for carrying out logical AND operation on the M comparison results and outputting the first control signals.

In the above scheme, the memory is a one-time programmable memory; the one-time programmable memory is applied to a dynamic random access memory. The embodiment of the disclosure also provides a method for reading a memory, the memory including a fuse array, a control signal generating circuit and a reading circuit arranged in an array, the method comprising:

The control signal generating circuit receives a reset signal and outputs a first control signal to the reading circuit based on the reset signal; wherein the reset signal is used for indicating the memory to execute a reset operation; the reset signal is turned over from an active level to an inactive level at a first moment;

the reading circuit starts to read fuse data stored in a target fuse unit in the fuse array at a second moment according to the first control signal; a time interval exists between the second time and the first time.

In the above aspect, the control signal generating circuit receives a reset signal and outputs a first control signal to the reading circuit based on the reset signal, and includes:

the control signal generating circuit receives a second control signal and the reset signal, and generates a first clock signal based on the second control signal and the reset signal; the second control signal is used for indicating that reading of the fuse data is finished;

the control signal generating circuit receives the first clock signal and the reset signal, and generates the first control signal based on the first clock signal and the reset signal.

In the above aspect, the control signal generating circuit receives a second control signal and the reset signal, generates a first clock signal based on the second control signal and the reset signal, and includes:

the control signal generating circuit carries out logic operation on the second control signal and the reset signal, generates a first enabling signal and outputs the first enabling signal to the oscillator so as to control the operation of the oscillator; the oscillator is configured to generate the first clock signal based on the first enable signal.

In the above aspect, the control signal generating circuit receives the first clock signal and the reset signal, generates the first control signal based on the first clock signal and the reset signal, and includes:

the control signal generating circuit generates and outputs a second clock signal based on the first clock signal, wherein the clock period of the second clock signal is greater than the clock period of the first clock signal;

the control signal generation circuit generates and outputs the first control signal based on the second clock signal and the reset signal.

In the above scheme, the method further comprises:

the control signal generating circuit detects voltage values of M working voltages in the memory at the first moment according to the reset signal, and enables the first control signal when the voltage values of the M working voltages reach corresponding reference voltage values, wherein M is an integer larger than or equal to 1.

In the above scheme, the second time is a time when the voltage values of the M working voltages in the memory all reach the corresponding reference voltage values.

According to the embodiment of the disclosure, the control signal generating circuit is arranged in the memory, so that the first control signal is turned over from the invalid level to the valid level at the second moment, and because a time interval exists between the second moment and the first moment, the first control signal instructs the reading circuit to start reading fuse data after a certain time interval passes after the reset operation of the memory is finished, reading errors caused by unstable internal circuit voltage due to the reset operation can be avoided, and the reliability of the memory is improved.

Drawings

FIG. 1 is a timing diagram illustrating reading fuse data according to one embodiment of the present disclosure;

FIG. 2 is a partial block diagram of a memory according to an embodiment of the present disclosure;

FIG. 3 is a block diagram of a control signal generation circuit according to an embodiment of the present disclosure;

fig. 4 is a block diagram of a second signal generating unit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit configuration diagram of a first signal generating unit according to an embodiment of the present disclosure;

FIG. 6 is a timing diagram illustrating a control signal generation circuit generating a first control signal according to one embodiment of the present disclosure;

Fig. 7 is a schematic circuit configuration diagram of a second signal generating unit according to an embodiment of the present disclosure;

fig. 8 is a schematic circuit diagram of a pulse signal generating unit according to an embodiment of the present disclosure;

fig. 9 is a schematic circuit configuration diagram of a pulse signal generating unit according to another embodiment of the present disclosure;

fig. 10 is a schematic circuit configuration diagram of a signal detection unit according to an embodiment of the present disclosure;

FIG. 11 is a timing diagram illustrating a control signal generation circuit generating a first control signal according to yet another embodiment of the present disclosure;

fig. 12 is a flowchart illustrating a method for reading a memory according to an embodiment of the disclosure.

Detailed Description

The technical scheme of the present disclosure will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the description that follows. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.

The One-time programmable memory comprising the fuse array has the characteristic that the memory state is not affected by power failure, can be applied to various technical fields, such as dynamic random access memory (Dynamic Random Access Memory, DRAM) chips, and can realize redundancy replacement by utilizing One-time programmable memory (One-time Programmable, OTP) to store the address information of a memory cell with defects; the accurate trimming of various parameters (such as voltage, current and frequency) inside the chip can also be realized by programming the disposable programming memory. Fig. 1 is a timing diagram illustrating reading fuse data according to an embodiment of the present disclosure. As shown in fig. 1, at time T1 when the power-up or reset of the one-time programmable memory is completed, a corresponding clock signal CLK is generated, and at time T1, a control signal ctrl is enabled, so that fuse data can be read and sent to and used by various components of the DRAM chip. However, the power-up or reset operation of the one-time programmable memory is easy to cause unstable voltage of the internal circuit, and the fuse data is read immediately after the power-up or reset of the one-time programmable memory, which may cause unreliable read data and cause other problems.

In this regard, the present disclosure proposes the following embodiments.

Fig. 2 is a partial block diagram of a memory shown in accordance with an embodiment of the present disclosure. As shown in fig. 2, the memory includes:

a fuse array 110, a control signal generation circuit 120, and a read circuit 130;

the control signal generating circuit 120 is configured to receive the RESET signal reset_n and output a first control signal scan_on to the reading circuit 130 based ON the RESET signal reset_n; wherein, the RESET signal reset_n is used for indicating the memory to execute the RESET operation; the RESET signal reset_n is inverted from an active level to an inactive level at a first time;

the reading circuit 130 is connected to the control signal generating circuit 120 and configured to start reading the fuse data f_data stored in the target fuse unit in the fuse array 110 at the second timing according to the first control signal scan_on; there is a time interval between the second time and the first time. The fuse data f_data may include address information characterizing a memory cell having a defect, or a code to adjust on-chip parameters.

In some embodiments, the active level of the RESET signal reset_n is a logic low level and the inactive level is a logic high level. It will be appreciated that the first time is the time when the memory ends the RESET operation, and the RESET signal reset_n toggles from a logic low level to a logic high level.

In the embodiment of the present disclosure, the memory further includes an output circuit 140, where the output circuit 140 is connected to the read circuit 130 and configured to output the fuse data f_data read by the read circuit 130.

Fig. 3 is a block diagram of a control signal generating circuit according to an embodiment of the present disclosure, and as shown in fig. 3, the control signal generating circuit 120 includes: a first signal generation unit 121 and a second signal generation unit 122;

a first signal generating unit 121 configured to receive the second control signal scan_end and the RESET signal reset_n, and generate a first clock signal af_clk_1 based on the second control signal scan_end and the RESET signal reset_n; the second control signal scan_end is used for indicating the END of reading the fuse data f_data;

the second signal generating unit 122 is configured to receive the first clock signal af_clk_1 and the RESET signal reset_n, and generate the first control signal scan_on based ON the first clock signal af_clk_1 and the RESET signal reset_n.

Fig. 4 is a block diagram of a second signal generating unit according to an embodiment of the present disclosure, and as shown in fig. 4, the second signal generating unit 122 includes a delay subunit 123 and a signal generating subunit 124;

the delay subunit 123 is configured to receive the first clock signal af_clk_1, generate and output the second clock signal af_clk_2 based on the first clock signal af_clk_1, wherein the clock period of the second clock signal af_clk_2 is greater than the clock period of the first clock signal af_clk_1.

The signal generating subunit 124 is configured to receive the second clock signal af_clk_2 and the RESET signal reset_n, generate and output the first control signal scan_on based ON the second clock signal af_clk_2 and the RESET signal reset_n.

In some embodiments, the RESET signal reset_n is logically negated and then used as a RESET signal for the delay subunit 123.

Fig. 5 is a schematic circuit diagram of a first signal generating unit according to an embodiment of the present disclosure, and as shown in fig. 5, the first signal generating unit 121 includes a first inverter 1210, a first logic nor gate 1211, and an oscillator 1212; the first inverter 1210 and the first logical nor gate 1211 are configured to logically operate the second control signal scan_end and the RESET signal reset_n, generate the first enable signal osc_en to be output to the oscillator 1212 for controlling the operation of the oscillator 1212; the oscillator 1212 is configured to generate the first clock signal af_clk_1 based on the first enable signal osc_en. In some embodiments, the oscillator 1212 may be a ring oscillator.

It should be noted that the oscillator 1212 is configured to generate an oscillation signal based on the first enable signal osc_en, and the oscillation signal is the first clock signal af_clk_1. The clock period of the first clock signal af_clk_1 is the oscillation period of the oscillation signal generated by the oscillator 1212.

In some embodiments, the active level of the second control signal scan_end is a logic high level, and the inactive level is a logic low level.

Fig. 6 is a timing diagram of a control signal generating circuit generating a first control signal according to an embodiment of the present disclosure. Referring to fig. 5 to 6, at a first time T1, when the RESET signal reset_n is at a logic high level and the second control signal scan_end is at a logic low level, the first enable signal osc_en is at an enable state of the logic high level, and thus the oscillator 1212 generates an oscillation signal when receiving the first enable signal osc_en. The first signal generation unit 121 is specifically configured to turn on the oscillator 1212 at a first time T1 according to the first enable signal osc_en. During the first to third times T1 to T3, the RESET signal reset_n maintains a logic high level, the second control signal scan_end maintains a logic low level, the first enable signal osc_en is also in an enable state of the logic high level, and the oscillator 1212 is in an operating state. Here, the operation state of the oscillator 1212 is a state when the oscillator 1212 generates an oscillation signal.

Until a third time T3, the second control signal scan_end is inverted from a logic low level to a logic high level, the RESET signal reset_n maintains the logic high level, the first enable signal osc_en is inverted from the logic high level to the logic low level, and is in a disable state, and the first signal generating unit 121 is specifically configured to turn off the oscillator 1212 at the third time T3 according to the first enable signal osc_en. The second control signal scan_end indicates that the reading of the fuse data f_data by the reading circuit 130 is ended at the third time T3.

Fig. 7 is a schematic circuit diagram of a second signal generating unit according to an embodiment of the disclosure, where, as shown in fig. 7, the delay subunit 123 includes N cascaded flip-flops, where N is an integer greater than or equal to 1; the clock control end of the first stage flip-flop is used as the input end of the delay subunit 123 and is connected withReceiving a first clock signal AF_CLK_1; the inverting output end of each stage of trigger is connected with the data input end of the trigger; clock control ends of other triggers except the first-stage trigger are connected with a positive-phase output end of a previous-stage trigger; the non-inverting output terminal of the nth stage flip-flop outputs the second clock signal af_clk_2. The clock period of the second clock signal af_clk_2 is greater than the clock period of the first clock signal af_clk_1. The second clock signal AF_CLK_2 has a second clock period and the first clock signal AF_CLK_1 has a first clock period, wherein the second clock period is 2 of the first clock period ^N Multiple times.

Taking N equal to 5 as an example, the delay subunit 123 includes five cascaded flip-flops, and the first clock cycle is taken as 2T as an example, and the frequency divider formed by the five cascaded flip-flops is used to divide the first clock signal af_clk_1 with the clock cycle of 2T to generate the second clock signal with the clock cycle of 64T, namely af_clk_2.

As shown in fig. 6, specifically, the first stage flip-flop outputs a clock signal out1 having a clock period of 4T, the second stage flip-flop outputs a clock signal out2 having a clock period of 8T, the third stage flip-flop outputs a clock signal out5 having a clock period of 16T, the fourth stage flip-flop outputs a clock signal out4 having a clock period of 32T, and the fifth stage flip-flop outputs a second clock signal af_clk_2 having a clock period of 64T. It is understood that the time interval between the second time T2 and the first time T1 is a half clock period of the second clock signal af_clk_2, i.e. 32T.

In some embodiments, the RESET signal reset_n is logically negated to serve as a RESET signal for 5 flip-flops of the delay subunit 123 to ensure synchronization of the entire circuit after the generation of the second clock signal af_clk_2.

It should be noted that, the clock period of the second clock signal af_clk_2 may be adjusted by setting the number N of flip-flops in the delay subunit 123. Specifically, with 2T as the first clock period, the second clock signal af_clk_2 with 32T clock period can be generated by using four cascaded flip-flops, and the second clock signal af_clk_2 with 128T clock period can be generated by using 6 cascaded flip-flops. The clock period of the second clock signal af_clk_2 can be set according to actual requirements.

In the embodiment of the present disclosure, as shown in fig. 7, the signal generating subunit 124 includes a pulse signal generating unit 125, a second inverter 126, and an RS latch 127; the Pulse signal generating unit 125 is configured to receive the second clock signal af_clk_2, generate and output the first Pulse signal Pulse based on the second clock signal af_clk_2; the second inverter 126 is configured to receive a RESET signal reset_n; the Pulse signal generating unit 125 and the output terminal of the second inverter 126 are connected to the input terminal of the RS latch 127, and the RS latch 127 is configured to receive the first Pulse signal Pulse and the RESET signal reset_n subjected to the logical non-operation, generate and output the first control signal scan_on. The set port of the RS latch receives the first Pulse signal Pulse, and the RESET port of the RS latch receives the RESET signal reset_n after logical negation operation.

In some embodiments, the output of RS latch 127 may be connected with an even number of inverters to enhance the transmission capability of the circuit. In a specific example, as shown in fig. 7, the output terminal of the RS latch 127 may be connected to the third inverter 128 and the fourth inverter 129, and the first control signal scan_on is output by the fourth inverter 129.

Fig. 8 is a schematic circuit diagram of a pulse signal generating unit according to an embodiment of the present disclosure, and as shown in fig. 8, the pulse signal generating unit 125 includes a fifth inverter 131, a first delay circuit 132, and a second logical nor gate 133.

The first delay circuit 132 may be implemented by any circuit structure that can implement a delay function, for example, an even number of connected inverters, some capacitors, or a buffer, which is not particularly limited in this disclosure.

The fifth inverter 131 and the first delay circuit 132 process the second clock signal af_clk_2 to obtain a delay signal, the input end of the second logic nor gate 133 receives the second clock signal af_clk_2 and the delay signal, and the second logic nor gate 133 performs logic operation on the second clock signal af_clk_2 and the delay signal to output the first Pulse signal Pulse.

It should be noted that, in the embodiment of the present disclosure, the pulse signal generating unit 125 is configured to detect a falling edge of the second clock signal af_clk_2.

Table 1 shows logic level values of a part of signals in the control signal generating circuit at different stages shown in fig. 6. TABLE 1

Referring to fig. 5 to 8 and table 1, at a first time T1, the RESET signal reset_n is switched from logic 0 to logic 1 to indicate that the memory ends the RESET operation. In the stages T1 to T2, the RESET signal reset_n is logic 1 and the first Pulse signal Pulse is logic 0, so that the signals received by the set port and the RESET port of the RS latch 127 are both logic 0, the RS latch 127 maintains the output Q value before the first time T1, and then the first control signal scan_on output by the RS latch 127 is logic 0.

At the second time T2, the first Pulse signal Pulse is switched from logic 0 to logic 1, and the RESET signal reset_n is logic 1, so that the signal received by the set port of the RS latch 127 is logic 1, and the signal received by the RESET port of the RS latch 127 is logic 0, and at this time, the first control signal scan_on output by the RS latch 127 is logic 1. After time T2, the first Pulse signal Pulse is switched from logic 1 to logic 0, and the RESET signal reset_n is logic 1, so that the signals received by the set port and the RESET port of the RS latch 127 are both logic 0, and the RS latch 127 maintains the output Q value at time T2, and at this time, the first control signal scan_on output by the RS latch 127 is logic 1. It will be appreciated that the first Pulse signal Pulse remains in the logic high state for a short period of time, and is only at a logic high level at time T2.

At time T3, the first enable signal osc_en is switched from logic 1 to logic 0 to indicate that the oscillator 1212 is turned off. The second control signal scan_end is switched from logic 0 to logic 1, indicating the END of reading the fuse data f_data. It should be noted that, the third time T3 shown in fig. 6 is only one illustration, and the time for the second control signal scan_end to flip from the inactive level to the active level can be adjusted according to the actual requirement.

In this way, the control signal generating circuit is arranged in the memory, so that the first control signal is turned over from the invalid level to the valid level at the second moment, and the time interval exists between the second moment and the first moment, so that the first control signal instructs the reading circuit to start reading the fuse data after a certain time interval passes after the reset operation of the memory is finished, the reading error caused by unstable internal circuit voltage due to the reset operation can be avoided, and the reliability of the memory is improved.

Further, the time interval between the first time and the second time can be controlled by adjusting the number of flip-flops in the delay subunit of the control signal generating circuit to ensure the reliability of reading.

Fig. 9 is a schematic circuit diagram of a pulse signal generating unit according to another embodiment of the present disclosure, and as shown in fig. 9, the pulse signal generating unit 125 includes a sixth inverter 134, a second delay circuit 135, and a first logic and gate 136.

The second delay circuit 135 may be implemented by any circuit structure that can implement a delay function, for example, an even number of connected inverters, some capacitors, or a buffer, which is not particularly limited in this disclosure.

The delay signal is obtained by processing the second clock signal af_clk_2 by the sixth inverter 134 and the second delay circuit 135, the input terminal of the first logic and gate 136 receives the second clock signal af_clk_2 and the delay signal, and the first logic and gate 136 performs logic operation on the second clock signal af_clk_2 and the delay signal, and outputs the first Pulse signal Pulse.

Note that, the pulse signal generating unit 125 shown in fig. 9 is used to detect the rising edge of the second clock signal af_clk_2. The turn-on time of the oscillator can be set to be the time when the first rising edge of the second clock signal af_clk_2 arrives according to actual requirements, so as to adjust the time when the first Pulse signal Pulse is switched from logic 0 to logic 1.

In another embodiment of the present disclosure, the control signal generating circuit 120 includes: the signal detection unit is configured to detect voltage values of M working voltages in the memory at a first time T1 according to the RESET signal RESET_n, and enable the first control signal SCAN_ON when the voltage values of the M working voltages all reach corresponding reference voltage values, wherein M is an integer greater than or equal to 1. The operating voltages are voltages required for reading fuse data and signal transmission, and include, but are not limited to, a precharge voltage v_pre, an array voltage VARY, a read column select line voltage v_csl, and the like.

In some embodiments, the signal detection unit includes M comparators and an and logic circuit; the inverting input end of each comparator is used for receiving the reference voltage, and the non-inverting input end of each comparator is used for receiving one of M working voltages and outputting a comparison result; the output ends of the M comparators are connected to the input ends of the AND logic operation circuit, and the AND logic circuit is used for carrying out logical AND operation ON the M comparison results and outputting a first control signal SCAN_ON.

In one embodiment, an example where M is equal to 3 is illustrated. Fig. 10 is a schematic circuit diagram of a signal detection unit according to an embodiment of the present disclosure, and as shown in fig. 10, the signal detection unit 150 includes a first comparator 151, a second comparator 152, a third comparator 153, and an and logic circuit 154.

The inverting input terminal of each comparator is used for receiving the reference voltage, and the non-inverting input terminal of each comparator is used for receiving one of 3 working voltages and outputting a comparison result. Specifically, the inverting input terminal of the first comparator 151 receives the first reference voltage VREF1, and the non-inverting input terminal of the first comparator 151 receives the first operating voltage vaf_pwr1. The inverting input terminal of the second comparator 152 receives the second reference voltage VREF2, and the non-inverting input terminal of the first comparator 151 receives the second operating voltage vaf_pwr2. The inverting input terminal of the third comparator 153 receives the third reference voltage VREF3, and the non-inverting input terminal of the third comparator 153 receives the third operating voltage vaf_pwr3. The first comparator 151, the second comparator 152, and the third comparator 153 input the corresponding comparison results R1, R2, and R3 to the and logic circuit 154, respectively. The and logic circuit 154 includes a first nand gate 1541 and a seventh inverter 1542, and outputs a first control signal scan_on after performing a logical and operation ON the comparison results R1, R2, and R3 by the and logic circuit 154.

In some embodiments, as shown in FIG. 10, an even number of inverters 155 may be provided between each comparator and the AND logic circuit to enhance the transfer capability of the circuit.

In some embodiments, as shown in FIG. 10, the output of AND logic 154 may be coupled to deglitch (deglitch) circuitry 156 to remove glitches (glitch) from the first control signal SCAN_ON to generate a corresponding smoothed first control signal SCAN_ON.

Fig. 11 is a timing chart of a control signal generating circuit generating a first control signal according to still another embodiment of the present disclosure, which is described taking the signal detecting unit shown in fig. 10 as an example. Referring to fig. 10 and 11, the signal detection unit 150 is configured to detect voltage values of the first, second, and third operating voltages vaf_pwr1, vaf_pwr2, and vaf_pwr3 in the memory at a first time T1 according to the RESET signal reset_n, compare with the corresponding first, second, and third reference voltages VREF1, VREF2, and VREF3, and output comparison results R1, R2, and R3, respectively. When the voltage values of the 3 working voltages reach the corresponding reference voltage values, the comparison results R1, R2 and R3 are all at logic high level, and at this time, the second time T2 is the enabling state of the first control signal scan_on output by the and logic circuit 154 at logic high level.

It should be noted that, in the stage between the first time T1 and the second time T2, the second working voltage vaf_pwr2 and the first working voltage vaf_pwr1 reach corresponding reference voltage values sequentially, and the comparison results R2 and R1 are switched from the logic low level to the logic high level, but the third working voltage vaf_pwr3 does not reach the corresponding reference voltage value yet, so the first control signal scan_on output by the logic circuit 154 is in the logic low level disabling state.

In this way, by providing the control signal generating circuit including the signal detecting unit in the memory, the first control signal is enabled at the second timing when the operating voltage in the memory reaches the corresponding reference voltage value after the end of the reset operation of the memory. Since the working voltage in the memory is stabilized at the second moment, the first control signal indicates the reading circuit to start reading the fuse data, so that the reading error caused by unstable internal circuit voltage due to the reset operation can be avoided, and the reliability of the memory is improved.

Fig. 12 is a flowchart of a method for reading a memory according to an embodiment of the disclosure, where the memory includes a fuse array, a control signal generating circuit and a reading circuit, and the method for reading the memory specifically includes the following steps:

Step S10: the control signal generating circuit receives the reset signal and outputs a first control signal to the reading circuit based on the reset signal; the reset signal is used for indicating the memory to execute reset operation; the reset signal is inverted from an active level to an inactive level at a first time;

step S20: the reading circuit starts to read fuse data stored in a target fuse unit in the fuse array at a second moment according to the first control signal; there is a time interval between the second time and the first time.

The method for reading the memory is further described below with reference to fig. 2 to 8 and 12.

In an embodiment of the present disclosure, a control signal generating circuit receives a second control signal scan_end and a RESET signal reset_n, and generates a first clock signal af_clk_1 based on the second control signal scan_end and the RESET signal reset_n; the second control signal scan_end is used to indicate the END of reading the fuse data. Illustratively, the second control signal scan_end and the RESET signal reset_n are logically operated to generate the first enable signal osc_en to be output to the oscillator 1212 for controlling the operation of the oscillator 1212; the oscillator 1212 is configured to generate the first clock signal af_clk_1 based on the first enable signal osc_en. In some embodiments, the oscillator 1212 may be a ring oscillator.

The logic level values of the second control signal scan_end, the RESET signal reset_n and the first enable signal osc_en at different stages can be referred to fig. 6 and table 1.

In an embodiment of the present disclosure, the control signal generating circuit receives the first clock signal af_clk_1 and the RESET signal reset_n, and generates the first control signal scan_on based ON the first clock signal af_clk_1 and the RESET signal reset_n.

Illustratively, the control signal generating circuit generates and outputs a second clock signal af_clk_2 based on the first clock signal af_clk_1, wherein the second clock signal af_clk_2 has a clock period greater than that of the first clock signal af_clk_1. In some embodiments, the second clock signal AF_CLK_2 may be generated by a delay subunit 123 as shown in FIG. 7, the second clock signal AF_CLK_2 having a second clock cycle and the first clock signal AF_CLK_1 having a first clock cycle, wherein the second clock cycle is 2 of the first clock cycle ^N Multiple times.

In the embodiment of the present disclosure, the control signal generating circuit generates and outputs the first control signal scan_on based ON the second clock signal af_clk_2 and the RESET signal reset_n.

Illustratively, the Pulse signal generating unit 125 generates and outputs a first Pulse signal Pulse based ON the second clock signal af_clk_2, and the RS latch 127 receives the first Pulse signal Pulse and the RESET signal reset_n subjected to the logical negation operation, and generates and outputs a first control signal scan_on.

In the embodiment of the present disclosure, the first signal generating unit 121 turns on the oscillator 1212 at a first time T1 and turns off the oscillator 1212 at a third time T3 according to the first enable signal osc_en; the reading circuit 130 ends reading the fuse data f_data at the third timing T3.

In some embodiments, the reading method further comprises: the output circuit outputs the fuse data F_data read by the reading circuit.

Fig. 10 to 12 are diagrams for describing another process of generating the first control signal according to the embodiment of the present disclosure.

In the embodiment of the disclosure, the control signal generating circuit detects the voltage values of M working voltages in the memory at a first time T1 according to the RESET signal reset_n, and enables the first control signal scan_on when the voltage values of the M working voltages all reach the corresponding reference voltage values, where M is an integer greater than or equal to 1. The operating voltages include, but are not limited to, a precharge voltage v_pre, an array voltage VARY, a read column select line voltage v_csl, and the like.

In the embodiment of the present disclosure, the second time T2 is a time when the voltage values of the M working voltages in the memory all reach the corresponding reference voltage values. It can be understood that when the voltage values of the M operating voltages in the memory reach the corresponding reference voltage values, the voltage of the internal circuit of the memory is stabilized, and the first control signal scan_on is enabled to instruct the reading circuit to start reading the fuse data f_data, so that the reliability of the reading operation can be improved.

In one embodiment, an example where M is equal to 3 is illustrated. Referring to fig. 10 and 11, the control signal generating circuit 120 detects voltage values of the first, second and third operating voltages vaf_pwr1, vaf_pwr2 and vaf_pwr3 in the memory at a first time T1 according to the RESET signal reset_n, compares the voltage values with corresponding first, second and third reference voltages VREF1, VREF2 and VREF3, and outputs comparison results R1, R2 and R3, respectively. When the voltage values of the 3 working voltages reach the corresponding reference voltage values, the comparison results R1, R2 and R3 are all at logic high level, and at this time, the second time T2 is the enabling state of the first control signal scan_on output by the and logic circuit 154 at logic high level.

The memory described in the embodiments of the present disclosure is a one-time programmable memory applied to a DRAM, which is composed of a plurality of memory cells, each memory cell generally including a transistor and a capacitor, and a word line voltage on a word line can control the on and off of the transistor so that data information stored in the capacitor can be read through a bit line or written into the capacitor. The fuse data is stored by the memory to enable redundancy replacement or accurate trimming of various parameters (e.g., voltage, current, and frequency) inside the DRAM.

It should be noted that the embodiments of the present disclosure are not limited to DRAM, but include other memories including a one-time programmable Memory, such as Static Random-Access Memory (SRAM), NAND Memory, and the like.

According to the embodiment of the disclosure, the control signal generating circuit is arranged in the memory, so that the first control signal is turned over from the invalid level to the valid level at the second moment, and because a time interval exists between the second moment and the first moment, the first control signal instructs the reading circuit to start reading fuse data after a certain time interval passes after the reset operation of the memory is finished, reading errors caused by unstable internal circuit voltage due to the reset operation can be avoided, and the reliability of the memory is improved.

It should be appreciated that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims (11)

1. A memory, comprising:

a fuse array, a control signal generating circuit, and a reading circuit;

the control signal generation circuit includes: a first signal generation unit and a second signal generation unit;

the first signal generating unit is configured to receive a second control signal and a reset signal, and generate a first clock signal based on the second control signal and the reset signal; wherein the second control signal is used for indicating that reading of the fuse data is finished; the reset signal is used for indicating the memory to execute a reset operation; the reset signal is turned over from an active level to an inactive level at a first moment;

the second signal generation unit comprises a delay subunit and a signal generation subunit; the delay subunit is configured to receive the first clock signal, generate and output a second clock signal based on the first clock signal, wherein a clock period of the second clock signal is greater than a clock period of the first clock signal; the signal generation subunit is configured to receive the second clock signal and the reset signal, generate and output a first control signal based on the second clock signal and the reset signal;

The reading circuit is connected with the control signal generating circuit and is configured to start reading fuse data stored in a target fuse unit in the fuse array at a second moment according to the first control signal; a time interval exists between the second time and the first time.

2. The memory of claim 1, wherein the first signal generation unit comprises a first inverter, a first logical nor gate, and an oscillator; the first inverter and the first logical nor gate are configured to perform a logical operation on the second control signal and the reset signal, generate a first enable signal, and output the first enable signal to the oscillator for controlling the operation of the oscillator; the oscillator is configured to generate the first clock signal based on the first enable signal.

3. The memory of claim 1, wherein the delay subunit comprises N cascaded flip-flops, N being an integer greater than or equal to 1; the clock control end of the first-stage trigger is used as the input end of the delay subunit and receives the first clock signal; the inverting output end of each stage of the trigger is connected with the data input end of the trigger; clock control ends of other triggers except the trigger of the first stage are connected with a positive phase output end of the trigger of the previous stage; and the non-inverting output end of the flip-flop of the N-th stage outputs the second clock signal.

4. The memory of claim 3, wherein the signal generation subunit comprises a pulse signal generation unit, a second inverter, and an RS latch; the pulse signal generating unit is configured to receive the second clock signal, generate and output a first pulse signal based on the second clock signal; the second inverter is configured to receive the reset signal; the output ends of the pulse signal generating unit and the second inverter are connected to the input end of the RS latch, and the RS latch is configured to receive the first pulse signal and the reset signal subjected to logical negation operation, and generate and output the first control signal.

5. The memory according to claim 1, wherein the control signal generation circuit includes: and the signal detection unit is configured to detect the voltage values of M working voltages in the memory at the first moment according to the reset signal, and enable the first control signal when the voltage values of the M working voltages all reach corresponding reference voltage values, wherein M is an integer greater than or equal to 1.

6. The memory of claim 5, wherein the signal detection unit comprises M comparators and logic circuits; the inverting input end of each comparator is used for receiving the reference voltage, and the non-inverting input end of each comparator is used for receiving one of the M working voltages and outputting a comparison result; the output ends of the M comparators are connected to the input ends of the AND logic circuit, and the AND logic circuit is used for carrying out logical AND operation on the M comparison results and outputting the first control signals.

7. The memory according to any one of claims 1 to 6, wherein the memory is a one-time programmable memory;

the one-time programmable memory is applied to a dynamic random access memory.

8. A method for reading a memory, wherein the memory comprises a fuse array, a control signal generating circuit and a reading circuit; the control signal generating circuit comprises a first signal generating unit and a second signal generating unit; the second signal generation unit comprises a delay subunit and a signal generation subunit; the method comprises the following steps:

the first signal generating unit receives a second control signal and a reset signal, and generates a first clock signal based on the second control signal and the reset signal; wherein the second control signal is used for indicating that reading of the fuse data is finished; the reset signal is used for indicating the memory to execute a reset operation; the reset signal is turned over from an active level to an inactive level at a first moment;

the delay subunit receives the first clock signal, and generates and outputs a second clock signal based on the first clock signal, wherein the clock period of the second clock signal is greater than that of the first clock signal;

The signal generation subunit receives the second clock signal and the reset signal, and generates and outputs a first control signal based on the second clock signal and the reset signal;

the reading circuit starts to read fuse data stored in a target fuse unit in the fuse array at a second moment according to the first control signal; a time interval exists between the second time and the first time.

9. The method of claim 8, wherein the first signal generating unit comprises a first inverter, a first logical nor gate, and an oscillator; the first signal generating unit receives a second control signal and a reset signal, generates a first clock signal based on the second control signal and the reset signal, and includes:

the first inverter and the first logical nor gate perform logical operation on the second control signal and the reset signal, generate a first enabling signal, and output the first enabling signal to the oscillator for controlling the operation of the oscillator;

the oscillator generates the first clock signal based on the first enable signal.

10. The method of claim 8, wherein the method further comprises:

The control signal generating circuit detects voltage values of M working voltages in the memory at the first moment according to the reset signal, and enables the first control signal when the voltage values of the M working voltages reach corresponding reference voltage values, wherein M is an integer larger than or equal to 1.

11. The method of claim 10, wherein the second time is a time when voltage values of M operating voltages in the memory each reach a corresponding reference voltage value.

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