CN116010309B - Memory controller, system and system on chip, timing parameter control method - Google Patents

Abstract

The present disclosure provides a memory controller, a system on chip, and a timing parameter control method, the memory controller including a command arbiter and a timing parameter control module; a command arbiter configured to assert a command valid signal corresponding to a target phase according to the target phase used by the command; the time sequence parameter control module is configured to initialize an actual initial count value of a counter corresponding to each time sequence parameter according to a target phase indicated by the valid command valid signal and a default initial count value of the time sequence parameter and start the counter to count down according to a first preset value; and when the second preset value is counted, setting the time sequence parameter meeting signal of the phase corresponding to the second preset value to be effective. By the scheme, the problem that the memory controller loses clock cycles to send out commands can be avoided, and the control efficiency of the memory controller can be improved.

Description

Memory controller, system and system on chip, timing parameter control method

technical field

The present disclosure relates to the technical field of memory, and in particular to a memory controller, a system, a system on chip, and a timing parameter control method.

Background technique

Conventional memory (internal memory) may include static random access memory (SRAM), dynamic random access memory (DRAM), and memory generally uses DRAM. For memory, it includes multiple memory arrays, and each memory array includes rows and columns. When it is necessary to read and write to a certain address, the line activation (Active) command must be sent to the line where the address is located first, and then the read (Read)/write (Write) command can be sent. If you need to switch to another row address for reading/writing, you need to close the currently activated row, that is, send a Precharge command and then activate a new row, and then read/write.

In current chip products, the frequency CK of the memory is generally greater than the frequency MC_CLK of the memory controller, for example, the ratio between the two is 1:2 or 1:4. When MC_CLK:CK=1:N, the interface DFI (The DDRPHY Interface) between the memory controller and the port physical layer chip (Physical, PHY) has N (N is greater than 1) phases, which are phase0, phase1...phaseN-1. The memory controller can issue commands to the memory from different phases. For the memory controller, the commands it sends to the memory need to meet the timing parameters defined in the memory specification. For example, the delay time from the Active command to the Read/Write command of the same memory array is not less than the row addressing to column addressing delay time tRCD, and the delay time from the Active command to the Precharge command is not less than the shortest period tRAS from the valid to precharged memory row, etc. Therefore, the control of timing parameters by the memory controller directly affects the performance of the memory.

However, when the current memory controller controls the timing parameters corresponding to various commands, as far as the same command is concerned, it simply sets the actual initial count value of the timing parameter corresponding to the command based on the phase sent by the command, and does not distinguish the parity of the default initial count value of the timing parameter. This may lead to the fact that in special cases, the timing parameter needs to be delayed for a certain memory clock cycle cycle before it can be recognized by the memory controller on the basis of meeting the delay requirement, which in turn causes the memory controller to lose a certain cycle before it can issue a corresponding response. The command affects the control efficiency of the memory controller, thereby affecting the performance of the memory.

Contents of the invention

The purpose of the present disclosure is to provide a memory controller, a system, a system on chip, and a timing parameter control method, which can avoid the problem that the memory controller loses a certain cycle before issuing commands, and improve the control efficiency of the memory controller.

According to one aspect of the present disclosure, a memory controller is provided, including a command arbiter and a timing parameter control module;

The command arbiter is configured to: according to the target phase used by the currently issued command, set the command valid signal corresponding to the target phase to be valid;

The timing parameter control module is configured to: for each preset timing parameter corresponding to the command, according to the target phase indicated by the effective command valid signal and the default initial count value of the timing parameter, initialize the actual initial count value of the counter corresponding to the timing parameter, and start the counter to count down according to the first preset value in each clock cycle of the memory controller; The timing parameter satisfies the subsequent command indicated by the timing parameter corresponding to the signal; the first preset value is a ratio of the memory frequency to the memory controller frequency, and each phase formed under the ratio has a corresponding second preset value.

In a feasible implementation manner of the present disclosure, the timing parameter control module is specifically configured to: for each timing parameter corresponding to the command, initialize the actual initial count value of the counter corresponding to the timing parameter to: the sum of the default initial count value of the timing parameter and a second preset value; the second preset value is the phase number of the target phase.

In a feasible implementation of the present disclosure, when the ratio of the memory controller frequency to the memory frequency is 1:2, there are a zeroth phase and a first phase, and the phase number corresponding to the zeroth phase is 0, and the phase number corresponding to the first phase is 1; when the ratio of the memory controller frequency to the memory frequency is 1:4, there are a zeroth phase, a first phase, a second phase, and a third phase, and the phase number corresponding to the zeroth phase is 0, and the phase number corresponding to the first phase is 1, which corresponds to the second phase The phase number of is 2, and the phase number corresponding to the third phase is 3.

In a feasible implementation manner of the present disclosure, the number of the phases is the same as the value of the ratio.

In a feasible implementation manner of the present disclosure, the count value of the counter is a non-negative number, and if the current count value is smaller than the ratio, its count value in a next memory controller clock cycle is configured to be 0.

In a feasible implementation of the present disclosure, the timing parameter is a delay time from row addressing to column addressing tRCD, a shortest period from memory row valid to precharging tRAS, a row-to-row delay tRRD or a write recovery delay tWR.

According to another aspect of the present disclosure, there is also provided a timing parameter control method applied to a memory controller including a command arbiter and a timing parameter control module, the method comprising:

The command arbiter sets the command valid signal corresponding to the target phase as valid according to the target phase used by the currently issued command;

For each preset timing parameter corresponding to the command, the timing parameter control module initializes the actual initial count value of the counter corresponding to the timing parameter according to the target phase indicated by the effective command valid signal and the default initial count value of the timing parameter, and starts the counter to count down according to the first preset value in each clock cycle of the memory controller; The subsequent command indicated by the timing parameter corresponding to the signal;

The first preset value is a ratio of the memory frequency to the memory controller frequency, and each phase formed under the ratio has a corresponding second preset value.

In a feasible implementation of the present disclosure, for each preset timing parameter corresponding to the command, according to the target phase indicated by the valid command valid signal and the default initial count value of the timing parameter, initializing the actual initial count value of the counter corresponding to the timing parameter includes:

For each timing parameter corresponding to the command, the actual initial count value of the counter corresponding to the timing parameter is initialized as: the sum of the default initial count value of the timing parameter and a second preset value; the second preset value is the phase number of the target phase.

According to another aspect of the present disclosure, there is also provided a memory control system, including the memory controller in any one of the above embodiments, a memory device, and a port physical layer chip (Physical, PHY) connected between the memory controller and the memory device.

In a feasible implementation manner, the memory device may be a dynamic random access memory, and the dynamic random access memory may be a graphics double data rate synchronous dynamic random access memory (Graphics Double DataRate Synchronous Dynamic Random Access Memory, GDDR SDRAM).

According to another aspect of the present disclosure, there is also provided a system on chip (System on Chip, SOC), where the system on chip includes the above memory control system. In some usage scenarios, the product form of the SOC is embodied as a GPU (Graphics Processing Unit, graphics processing unit) SOC; in other usage scenarios, the product form of the SOC is embodied as a CPU (Central Processing Unit, central processing unit) SOC.

According to another aspect of the present disclosure, an electronic component is also provided, the electronic component includes the system-on-chip SOC described in any one of the above embodiments. In some usage scenarios, the product form of the electronic component is a graphics card; in other usage scenarios, the product form of the electronic component is a CPU motherboard.

According to another aspect of the present disclosure, there is also provided an electronic device, including the above-mentioned electronic component. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

Description of drawings

FIG. 1 is one of timing diagrams of timing parameter control provided by the prior art;

Fig. 2 is the second sequence diagram of timing parameter control provided by the prior art;

FIG. 3 is a schematic structural diagram of a memory controller according to an embodiment of the present disclosure;

FIG. 4 is one of timing diagrams of timing parameter control in an embodiment of the present disclosure;

FIG. 5 is the second sequence diagram of timing parameter control in an embodiment of the present disclosure;

FIG. 6 is a third timing diagram of timing parameter control in an embodiment of the present disclosure;

FIG. 7 is a fourth timing diagram of timing parameter control according to an embodiment of the present disclosure;

FIG. 8 is a schematic flowchart of a timing parameter control method according to an embodiment of the present disclosure.

Detailed ways

Before introducing the embodiments of the present disclosure, it should be noted that:

Some embodiments of the present disclosure are described as a processing flow. Although each operation step of the flow may be labeled with a sequential step number, the operation steps therein may be implemented in parallel, concurrently or simultaneously.

The embodiments of the present disclosure may use the terms "first", "second" and so on to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

The term "and/or" may be used in embodiments of the present disclosure, and "and/or" includes any and all combinations of one or more listed associated features.

It should be understood that when describing the connection relationship or communication relationship between two components, unless the two components are directly connected or communicated directly, otherwise, the connection or communication of the two components can be understood as a direct connection or communication, or as an indirect connection or communication through an intermediate component.

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the exemplary embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than an exhaustive list of all embodiments. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

First define the concepts involved in the embodiments of the present disclosure:

Assume that when MC_CLK:CK=1:2, there are zeroth phase and first phase, and the phase number corresponding to the zeroth phase is 0, denoted as phase0, and the phase number corresponding to the first phase is 1, denoted as phase1. Assume that when MC_CLK:CK=1:4, there are the zeroth phase, the first phase, the second phase and the third phase; and the phase number corresponding to the zeroth phase is 0, expressed as phase0, the phase number corresponding to the first phase is 1, expressed as phase1, the phase number corresponding to the second phase is 2, expressed as phase2, and the phase number corresponding to the third phase is 3, expressed as phase3.

cmd_vld_p0, cmd_vld_p1 . . . cmd_vld_pn are command valid signals sent by the command arbiter in the memory controller respectively, and 1 indicates that the command is valid. Valid cmd_vld_p0 indicates that the phase0 command is valid, corresponding to phase0 of the DFI interface; valid cmd_vld_p1 indicates that the phase1 command is valid, corresponding to phase1 of the DFI interface; valid cmd_vld_pn indicates that the phasen command is valid, corresponding to phase n of the DFI interface.

dfi_address_p0, dfi_address_p1... dfi_address_p n represent the phase0 command interface of the DFI interface, the phase1 command interface of the DFI interface, and the phase n command interface of the DFI interface. Of course, in actual application scenarios, the command interface may also include other signals, which are omitted here.

trcd_cnt represents a counter corresponding to the tRCD timing parameter.

timing_ok indicates that the timing parameters are satisfied, and 1 indicates that the signal is valid. According to different timing parameters, it can be subdivided into corresponding signals. For example, for tRCD timing parameters, the corresponding timing_ok is trcd_ok, indicating that the tRCD timing parameters are satisfied. trcd_ok specifically includes trcd_ok_p0/p1/p n, trcd_ok_p0 indicates that the timing of phase0 is satisfied, trcd_ok_p1 indicates that the timing of phase1 is satisfied, and trcd_ok_pn indicates that the timing of phase n is satisfied.

param_trcd represents the default initial count value corresponding to the tRCD timing parameter, which is defined in the memory specification.

When the existing memory controller controls the timing parameters corresponding to various commands, as far as the same command is concerned, it simply sets the actual initial count value of the timing parameter corresponding to the command based on the phase sent by the command, and does not distinguish the parity of the default initial count value of the timing parameter. This may lead to special cases. cle (that is, loss of at least 1 cycle) to determine that it has the conditions to issue the corresponding command, which affects the control efficiency of the memory controller, thereby affecting the performance of the memory.

In the following, an example will be given for the above-mentioned special situation faced in the prior art.

When MC_CLK:CK=1:2, for a specific timing parameter, the counter starts counting from the actual initial count value corresponding to the timing parameter; during the counting process, the count value of the counter is decremented by 1 for each MC_CLK, and so on, until the count value of the counter is reduced to 0, and the timing is satisfied, indicating that the memory controller can only send subsequent commands corresponding to the timing parameter after that.

Among them, if the command is issued in phase0, the actual initial count value = the default initial count value set for the timing parameter defined in the memory specification is divided by 2 and then rounded up (if the current value has a decimal, discard the decimal and it will be the integer value + 1); if the command is issued in phase1, the actual initial count value = the sum of the default initial count value set by the timing parameter and 2 divided by 2 and then rounded down (the current value has a decimal, discard the decimal and round up).

The above design will cause a loss of 1 cycle when the default initial count value is odd and the command is issued in phase0, and will cause a loss of 1 cycle when the default initial count value is even and the command is issued in phase1.

Specifically, assuming that the timing parameter is tRCD, it means that the memory controller needs to wait for the default initial count value of tRCD cycle time delay before sending the Read/Write command after sending the Active command.

When the default initial count value param_trcd=5 (odd number) corresponding to tRCD, and the Active0 command is issued from phase0, the actual initial count value of the counter start_value=ceiling(param_trcd/2)=ceiling(5/2)=3, ceiling means round up. The counter needs to go through 3 MC_CLKs (6 CKs) to be reduced to 0, which means that the memory controller needs 6 CKs before sending a Read/Write command to the memory. Assuming that a Read command needs to be sent later, as shown in Figure 1, on the memory device side, the delay from the Active0 (simplified to ACT0) command to the READ0 command is 6 cycles, which will cause a loss of one cycle.

When the default initial count value param_trcd=4 (even number) corresponding to tRCD, and the Active0 command is issued from phase1, the actual initial count value of the counter start_value=Rounddown((param_trcd+2)/2)=Rounddown((4+2)/2)=3, Rounddown means rounding down. The counter needs to go through 3 MC_CLKs (since it is sent from phase1, so it corresponds to 5 CKs) before it can be reduced to 0, which means that the memory controller needs 5 CKs before it can send the Read/Write command to the memory. Assuming that a Read command needs to be sent later, as shown in FIG. 2 , on the memory device side, the delay from the ACT0 command to the READ0 command is 5 cycles, which will cause a loss of one cycle.

Similarly, when MC_CLK:CK=1:4, using the above-mentioned similar method, if you do not distinguish whether the timing of phase0, phase1, phase2, and phase3 is satisfied, a certain cycle will also be lost.

Based on this, the purpose of the present disclosure is to provide a timing parameter control scheme based on a memory controller, which can avoid the problem that the memory controller loses a certain cycle before issuing commands, so as to improve the control efficiency of the memory controller.

Specifically, an embodiment of the present disclosure provides a memory controller, which may include a command arbiter and a timing parameter control module. Certainly, the memory controller may also include other modules, such as a DFI interface control module.

Taking FIG. 3 as an example, FIG. 3 shows a specific memory controller 100 , including a command arbiter 101 , a timing parameter control module 102 and a DFI interface control module 103 .

Wherein, the command issued by the memory controller 100 is sent to the PHY 104 through the DFI command interface 107 conforming to the DFI interface protocol, and the PHY 104 converts the command into a command conforming to the memory interface protocol through the memory command interface 108, and then sends it to the memory device 105 through the memory command interface 108.

Of course, the DFI command interface 107 in FIG. 3 only shows the dfi_address signal interface for representation. It can be understood that the DFI command interface 107 may also include other unshown command interfaces.

When MC_CLK:CK=1:2, it includes two phases of phase0 (P0) and phase1 (P1). When MC_CLK:CK=1:4, it includes four phases of phase0 (P0), phase1 (P1), phase2 (P2) and phase3 (P3). That is to say, the number of phases included in each clock cycle of the memory controller is equal to the ratio of the memory frequency CK to the memory controller frequency MC_CLK.

In the embodiment of the present disclosure, when the upper user layer wants to read/write the memory device 105 , it first sends a corresponding Read/Write command to the memory controller 100 through an AXI (Advanced eXtensible Interface) bus interface.

After the memory controller 100 sorts the received commands into a sequenced queue, the command arbiter 101 of the memory controller 100 selects a command from the queue according to the sequence of the queue, and sends the command to the memory device 105 via the DFI interface control module 103 and the PHY 104.

Before the command arbiter 101 sends out the Read/Write command, it is necessary to determine whether the row at the address to be accessed by the Read/Write command has been activated, and then determine whether to issue an Active command for the row at the address to activate the row at the address. After the activation is completed, a Read/Write command can be issued at the row at the address. If the line where the address is located is inactive and the line where other addresses are located is currently active, you need to issue the Precharge command to the line where the other address is located before issuing the Active command for the line where the address is located.

It is worth pointing out that the above-mentioned process of the command arbiter 101 controlling the timing of issuing the Active command is a relatively mature prior art, and will not be repeated here.

In the embodiment of the present disclosure, in order to realize accurate control of timing parameters, for the memory controller 100, the commands issued by it may be tracked.

Wherein, the command tracked by the memory controller 100 may be at least one command involved in the process of the memory controller 100 performing read/write control on the memory device 105, such as an Active command, a Read command, a Write command, and a Precharge command.

As mentioned above, the number of phases included in each memory controller clock cycle is equal to the ratio of the memory frequency CK to the memory controller frequency MC_CLK. Therefore, in the case of MC_CLK:CK≠1:1, multiple phases are included in each memory control clock cycle. For the same command, any currently existing phase can issue the command, so that when the command arbiter 101 issues the command, the phase in which the command is issued is not fixed.

In the embodiment of the present disclosure, in order to make it easier for the subsequent timing parameter control module 102 to distinguish which phase the command comes from, for each phase, a corresponding command valid signal cmd_vld (1 valid) is set. For example, the current MC_CLK:CK=1:2, the zeroth phase phase0 and the first phase phase1 exist, and cmd_vld_p0 and cmd_vld_p1 are set accordingly. Valid cmd_vld_p0 indicates that the command issued from phase0 is valid, and cmd_vld_p1 valid indicates that the command issued from phase1 is valid. For another example, the current MC_CLK:CK=1:4, there are the zeroth phase phase0, the first phase phase1, the second phase phase2 and the third phase phase3, and correspondingly set cmd_vld_p0, cmd_vld_p1, cmd_vld_p2 and cmd_vld_p3.

Based on this, in order for the subsequent timing parameter control module 102 to be able to distinguish which phase the command comes from, in the embodiment of the present disclosure, the command arbiter 101 is configured to: according to the target phase used by the currently issued command, set the command valid signal corresponding to the target phase as valid.

In order to avoid clock cycles lost when the frequencies of MC_CLK and CK do not match, the timing parameter control module 102 is configured to: for each preset timing parameter corresponding to the command, initialize the actual initial count value of the counter corresponding to the timing parameter according to the target phase indicated by the effective command valid signal and the default initial count value of the timing parameter, and start the counter to count down at each MC_CLK according to the first preset value; when the counter counts to the second preset value, set the timing of the phase corresponding to the second preset value The parameter satisfaction signal is asserted.

Wherein, the first preset value is a ratio of the memory frequency to the memory controller frequency, and there is a corresponding second preset value for each phase formed under the ratio.

Optionally, the second preset value corresponding to each phase is the phase number of the target phase.

For example, there are currently a zeroth phase phase0 and a first phase phase1, the second preset value corresponding to phase0 is 0, and the second preset value corresponding to phase1 is 1.

Specifically, in the embodiment of the present disclosure, for each timing parameter to be controlled (that is, each preset timing parameter corresponding to the command), a corresponding timing parameter satisfaction signal timing_ok (1 is valid) and a counter may be set. Of course, for each timing parameter satisfaction signal, there is a corresponding command, indicating that the condition for sending the command is currently met when the timing parameter satisfaction signal is valid.

The timing parameter to be controlled may be a timing parameter that may need to be followed after the currently issued command during the read/write control process of the memory device 105 by the memory controller 100, for example, it may be: the timing parameter is at least one of the delay time tRCD from row addressing to column addressing, the shortest period tRAS from memory row valid to precharging, row-to-row delay tRRD, and write recovery delay tWR.

Taking tRCD as an example, the corresponding timing_ok can be trcd_ok, and it can be subdivided into trcd_ok_p0/p1/pn according to the phase currently included. When trcd_ok_p0 is valid, it means that the timing of phase0 is satisfied, when trcd_ok_p1 is valid, it means that the timing of phase1 is satisfied, and when trcd_ok_pn is valid, it means that the timing of phasen is satisfied. The counter corresponding to the tRCD timing parameter is trcd_cnt. The commands corresponding to trcd_ok are the Read command and the Write command.

After the timing parameter control module 102 determines the target phase used by the currently issued command according to the effective state of each cmd_vld, it can initialize the actual initial count value start_value of the counter corresponding to the timing parameter according to the target phase and the default initial count value corresponding to the timing parameter for each timing parameter corresponding to the command.

An optional initialization manner is as follows: for each timing parameter corresponding to the command, the timing parameter control module 102 initializes the start_value of the counter corresponding to the timing parameter to be: the sum of the default initial count value and the second preset value of the timing parameter.

The default initial count value for each timing parameter is defined by the memory specification. The second preset value corresponding to each phase is the phase number of the phase.

In the case of MC_CLK: CK = 1: 2, there is a zero -phase and first phase, and the phase number corresponding to the zero phase is 0, and the phase number corresponding to the first phase is 1; in the case of mc_ck: CK = 1: 4, there is a zero phase, first phase, second phase and third phase, and the phase number corresponding to the zero phase is 0. The phase number corresponding to the first phase is 1, the phase number corresponding to the second phase is 2, and the phase number corresponding to the third phase is 3.

Suppose MC_CLK:CK=1:4, and the timing parameter of the current control is tRCD. If the command is sent from phase0 (the target phase is phase0), then trcd_start_value=param_trcd+0; if the command is sent from phase1 (the target phase is phase1), then trcd_start_value=param_trcd+1; if the command is sent from phase2 (the target phase is phase2), then trcd_start_value=param_trcd+2; if the command is sent from phase3 (the target phase is phase3 ), then trcd_start_value=param_trcd+3.

After the initialization is completed, for each timing parameter, the timing parameter control module 102 starts the corresponding counter to count down according to CK/MC_CLK at each MC_CLK. For example, when MC_CLK:CK=1:2, after each MC_CLK arrives, the timing parameter control module 102 will decrement the count value of the counter by 2; when MC_CLK:CK=1:4, after each MC_CLK arrives, the timing parameter control module 102 will decrement the count value of the counter by 4.

Of course, it is worth pointing out that in the embodiment of the present disclosure, the count value of each counter is defined as a non-negative number, so if the current count value of the counter is less than CK/MC_CLK, its count value in the next memory controller clock cycle is configured as 0. For example, if MC_CLK:CK=1:2, when the counter is less than 2 to 1, the next count value of the counter will jump to 0; if MC_CLK:CK=1:4, when the counter is less than 4 to 3, the next count value of the counter will jump to 0.

After the counter is started, for each timing parameter corresponding to the command, the timing parameter control module 102 monitors the count value of the counter corresponding thereto, and when the corresponding counter counts to the second preset value, the timing parameter satisfaction signal of the phase corresponding to the second preset value is asserted.

The phase corresponding to the timing parameter satisfaction signal that is enabled indicates that the command arbiter 101 can subsequently send a subsequent command indicated by the timing parameter corresponding to the timing parameter satisfaction signal at this phase.

For example, MC_CLK:CK=1:2, and the timing parameter of current control is tRCD. After a plurality of MC_CLKs, when the timing parameter control module 102 detects that the count value of trcd_cnt is reduced to 1, since 1 is the second preset value corresponding to phase1, indicating that the timing of phase1 is satisfied, the trcd_ok_p1 signal is set to 1, indicating that the command arbiter 101 can subsequently issue a command corresponding to trcd_ok in phase1, that is, a Read command and a Write command.

In the next MC_CLK, when the timing parameter control module 102 checks that the count value of trcd_cnt is reduced to 0, since 0 is the second preset value corresponding to phase0, indicating that the timing of phase0 is satisfied, the trcd_ok_p0 signal is set to 1. Since the current trcd_ok_p1 and trcd_ok_p0 are both valid, the command arbiter 101 can subsequently issue a command corresponding to trcd_ok in phase1, or in phase0 Issue the command corresponding to trcd_ok.

Of course, when the timing parameter satisfaction signal corresponding to a specific phase is asserted (that is, the specific phase satisfies the timing), it does not mean that the command arbiter 101 will definitely issue a corresponding command at the specific phase in the next clock cycle of the memory controller. The timing of issuing the corresponding command is determined by a specific application scenario.

It is worth noting that, for various timing parameters, the above processes are executed in parallel.

Taking MC_CLK:CK=1:2 and the timing parameter being tRCD as an example, several situations in which the memory controller 100 controls tRCD will be described below.

As shown in FIG. 4, when the default initial count value param_trcd=5 corresponding to tRCD is an odd number, and the command arbiter 101 issues the ACT0 command in phase0, trcd_cnt starts counting from trcd_start_value=param_trcd=5. Each MC_CLK counts down by 2, and when the timing parameter control module 102 detects that the counter trcd_cnt has decreased to 1, the trcd_ok_p1 signal is 1, indicating that the corresponding Read command/Write command can be issued in the subsequent phase1. When trcd_cnt decreases to 0, the trcd_ok_p0 and trcd_ok_p1 signals are 1, indicating that the corresponding Read command/Write command can be issued in phase0 or phase1.

In FIG. 4 , after the command arbiter 101 checks that trcd_ok_p1 is valid, the READ0 command can be issued in the subsequent phase1 without waiting for another MC_CLK to reduce the count value to 0. It can be seen from FIG. 4 that after dfi_address_p0 and dfi_address_p1 of the DFI interface are converted by the PHY 104 , the delay from ACT0 to READ0 of the memory device 105 is 5 memory clock cycles, and there is no clock loss.

As shown in FIG. 5 , when param_trcd=4 is an even number and the command arbiter 101 issues the ACT0 command in phase0, trcd_cnt starts counting from trcd_start_value=param_trcd=4. Each MC_CLK counts down by 2, and when the timing parameter control module 102 checks that the counter is reduced to 0, both trcd_ok_p0 and trcd_ok_p1 are 1, indicating that the corresponding Read command/Write command can be issued in phase0 or phase1.

In FIG. 5 , when the command arbiter 101 checks that trcd_ok_p0 is valid, the READ0 command is issued in phase0. It can be seen that after the command interface signals dfi_address_p0 and dfi_address_p1 of the DFI interface are converted by the PHY, the delay from ACT0 to READ0 of the memory device 105 is 4 memory clock cycles, and there is no clock loss.

As shown in FIG. 6 , when param_trcd=5 is an odd number and the command arbiter 101 issues the ACT0 command in phase1, trcd_cnt starts counting from trcd_start_value=param_trcd+1=6. Each MC_CLK count value is decremented by 2. When it is checked that the counter is reduced to 0, both trcd_ok_p0 and trcd_ok_p1 are 1, indicating that the corresponding Read command/Write command can be issued in phase0 or phase1.

When the command arbiter 101 checks that trcd_ok_p0 and trcd_ok_p1 are valid, a READ0 command is issued in phase0. It can be seen that after the command interface signals dfi_address_p0 and dfi_address_p1 of the DFI interface are converted by the PHY, the delay converted to ACT0 to READ0 of the memory device 105 is 5 memory clock cycles, and there is no clock loss.

As shown in FIG. 7 , when param_trcd=4 is an even number, and the command arbiter 101 issues the ACT0 command in phase1, trcd_cnt starts counting from trcd_start_value=param_trcd+1=5. Each MC_CLK counts down by 2. When it is checked that the counter is down to 1, the trcd_ok_p1 signal is 1, indicating that the corresponding Read command/Write command can be issued in phase1. When trcd_cnt is reduced to 0, the trcd_ok_p0 and trcd_ok_p1 signals are 1, indicating that the corresponding Read command/Write command can be issued in phase0 or phase1.

When the command arbiter 101 checks that trcd_ok_p1 is valid, it sends the READ0 command in phase1. It can be seen that after the command interface signals dfi_address_p0 and dfi_address_p1 of the DFI interface are converted by the PHY, the delay converted to ACT0 to READ0 of the memory device 105 is 4 memory clock cycles, and there is no clock loss.

It can be seen from the above that in the embodiments of the present disclosure, by distinguishing which target phase the command is sent from, and setting the corresponding actual initial count value of the timing parameter, the timing parameter satisfaction signal, and the second preset value used to indicate that the timing parameter satisfaction signal is valid for each phase, it is possible to deal with various default initial count values and various phases in a targeted manner, thereby avoiding the problem of clock cycle loss caused by different default initial count values and different phases when the frequencies of MC_CLK and CK do not match.

In addition, an embodiment of the present disclosure further provides a memory control system, including the memory controller in any of the above embodiments, a memory device, and a port physical layer chip PHY connected between the memory controller and the memory device.

Optionally, the memory device may be a dynamic random access memory, and the dynamic random access memory may be a graphics double rate synchronous dynamic random access memory (GDDR SDRAM).

Due to the use of the above memory controller, the problem that the memory controller loses clock cycles to issue commands can be avoided, and the control efficiency can be improved. Correspondingly, for the memory control system including the memory controller, the memory access performance can also be improved.

In addition, an embodiment of the present disclosure further provides a SOC, which includes the above memory control system. In some usage scenarios, the product form of the SOC is a GPU (Graphics Processing Unit, graphics processing unit) SOC; in other usage scenarios, the product form of the SOC is a CPU (Central Processing Unit, central processing unit) SOC.

Since the performance of the memory has a great influence on the performance of the SOC, correspondingly, on the basis of improving the memory access performance based on the memory control system, the performance of the SOC can be improved indirectly.

In addition, an embodiment of the present disclosure further provides an electronic component, which includes the SOC described in any one of the above embodiments. In some usage scenarios, the product form of the electronic component is a graphics card; in other usage scenarios, the product form of the electronic component is a CPU motherboard.

In addition, an embodiment of the present disclosure also provides an electronic device, which includes the above-mentioned electronic component. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, a workstation, a server, etc.

In addition, an embodiment of the present disclosure also provides a timing parameter control method, which is applied to a memory controller, and the memory controller includes a command arbiter and a timing parameter control module.

Referring to FIG. 8, the timing parameter control method may include:

Step S110: the command arbiter sets the command valid signal corresponding to the target phase to active according to the target phase used by the currently issued command.

Step S120: For each preset timing parameter corresponding to the command, the timing parameter control module initializes the actual initial count value of the counter corresponding to the timing parameter according to the target phase indicated by the effective command valid signal and the default initial count value of the timing parameter, and starts the counter to count down according to the first preset value in each clock cycle of the memory controller; when the counter counts to the second preset value, the timing parameter satisfaction signal of the phase corresponding to the second preset value is set to valid.

The phase corresponding to the timing parameter satisfaction signal that is enabled indicates that the command arbiter can send a subsequent command indicated by the timing parameter corresponding to the timing parameter satisfaction signal at this phase.

The first preset value is a ratio of the memory frequency to the memory controller frequency, and each phase formed under the ratio has a corresponding second preset value.

Optionally, for each preset timing parameter corresponding to the command, according to the target phase indicated by the effective command valid signal and the default initial count value of the timing parameter, initializing the actual initial count value of the counter corresponding to the timing parameter includes:

For each timing parameter corresponding to the command, the actual initial count value of the counter corresponding to the timing parameter is initialized as: the sum of the default initial count value of the timing parameter and a second preset value; the second preset value is the phase number of the target phase.

Optionally, when the ratio of the memory controller frequency to the memory frequency is 1:2, there are a zeroth phase and a first phase, and the phase number corresponding to the zeroth phase is 0, and the phase number corresponding to the first phase is 1; when the ratio of the memory controller frequency to the memory frequency is 1:4, there are a zeroth phase, a first phase, a second phase, and a third phase, and the phase number corresponding to the zeroth phase is 0, the phase number corresponding to the first phase is 1, and the phase number corresponding to the second phase is 2 , the phase number corresponding to the third phase is 3.

Optionally, the second preset value corresponding to each phase is the phase number of the phase.

Optionally, the number of phases is the same as the value of the ratio.

Optionally, the count value of the counter is a non-negative number, and if the current count value is smaller than the ratio, its count value in the next memory controller clock cycle is configured as 0.

Optionally, the timing parameter is a delay time tRCD from row addressing to column addressing, a shortest period tRAS from memory row valid to precharging, a row-to-row delay tRRD or a write recovery delay tWR.

Based on the above scheme, by distinguishing which target phase the command is sent from, and for each phase, setting the corresponding actual initial count value of the timing parameter, the timing parameter satisfaction signal, and the second preset value used to indicate that the timing parameter satisfaction signal is valid, it is possible to deal with various default initial count values and various phases in a targeted manner, thereby avoiding the problem of clock cycle loss caused by different default initial count values and different phases when the frequencies of MC_CLK and CK do not match.

While preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment and all changes and modifications which fall within the scope of the present disclosure.

It is obvious that those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies thereof, the present disclosure also intends to include these modifications and variations.

Claims (10)

1. A memory controller includes a command arbiter and a timing parameter control module;

the command arbiter is configured to: according to the target phase used by the currently issued command, a command valid signal corresponding to the target phase is set to be valid;

the timing parameter control module is configured to: for each preset time sequence parameter corresponding to the command, initializing an actual initial count value of a counter corresponding to the time sequence parameter according to the target phase indicated by the valid command valid signal and a default initial count value of the time sequence parameter, and starting the counter to count down according to a first preset value in a clock cycle of each memory controller; when the counter counts to a second preset value, a time sequence parameter meeting signal of a phase corresponding to the second preset value is set to be valid, and the command arbiter is characterized in that a subsequent command indicated by the time sequence parameter corresponding to the time sequence parameter meeting signal can be sent at the phase;

the first preset value is a ratio of the memory frequency to the memory controller frequency, and each phase formed under the ratio has a corresponding second preset value;

the actual initial count value of the counter corresponding to the timing parameter is initialized to: the default initial count value of the time sequence parameter is added with a second preset value; the second preset value is a phase number of the target phase.

2. The memory controller of claim 1, wherein a zeroth phase and a first phase are present and a phase number corresponding to the zeroth phase is 0 and a phase number corresponding to the first phase is 1 in a case where a ratio of the memory controller frequency to the memory frequency is 1:2; when the ratio of the memory controller frequency to the memory frequency is 1:4, there are a zeroth phase, a first phase, a second phase, and a third phase, and the phase number corresponding to the zeroth phase is 0, the phase number corresponding to the first phase is 1, the phase number corresponding to the second phase is 2, and the phase number corresponding to the third phase is 3.

3. The memory controller of claim 1, the number of phases being the same as the value of the ratio.

4. The memory controller of claim 1, the counter count value is a non-negative number, and the count value at the next memory controller clock cycle is configured to be 0 if the current count value is less than the ratio.

5. The memory controller of any one of claims 1-4, the timing parameter being a row-to-column address delay time tRCD, a memory row valid-to-precharge shortest period tRAS, a row-to-row delay tRRD, or a write recovery delay tWR.

6. A timing parameter control method applied to a memory controller including a command arbiter and a timing parameter control module, the method comprising:

the command arbiter sets a command valid signal corresponding to a target phase to be valid according to the target phase used by a currently issued command;

the time sequence parameter control module initializes the actual initial count value of a counter corresponding to the time sequence parameter according to the target phase indicated by the effective command effective signal and the default initial count value of the time sequence parameter aiming at each preset time sequence parameter corresponding to the command, and starts the counter to count down according to a first preset value in the clock period of each memory controller; when the counter counts to a second preset value, a time sequence parameter meeting signal of a phase corresponding to the second preset value is set to be valid, and the command arbiter is characterized in that a subsequent command indicated by the time sequence parameter corresponding to the time sequence parameter meeting signal can be sent at the phase;

the first preset value is a ratio of the memory frequency to the memory controller frequency, and each phase formed under the ratio has a corresponding second preset value;

the actual initial count value of the counter corresponding to the timing parameter is initialized to: the default initial count value of the time sequence parameter is added with a second preset value; the second preset value is a phase number of the target phase.

7. A memory control system comprising the memory controller of any one of claims 1-5, a memory device, a port physical layer chip PHY connected between the memory controller and the memory device.

8. A system on a chip comprising the memory control system of claim 7.

9. An electronic assembly comprising the system-on-chip of claim 8.

10. An electronic device comprising the electronic assembly of claim 9.