CN116010109B - Cache resource allocation method, device, electronic device and storage medium - Google Patents

Abstract

The disclosure relates to the technical field of electric digital data processing, and in particular relates to a cache resource allocation method, a cache resource allocation device, electronic equipment and a storage medium. A processor system comprising at least two levels of cache, the highest level of the at least two levels of cache being a shared cache, the shared cache comprising a plurality of shared cache sets, the method comprising: responding to a first data request from any application, and acquiring first identification information carried by the first data request; and responding to the first data request as the data request corresponding to the first identification information received for the first time, and distributing a preset number of shared cache groups to the first identification information. Because the number of the groups is more than the number of the ways, the shared cache resources are allocated based on the groups, so that the reasonable allocation of the shared cache resources can be realized more easily, and the utilization rate of the shared cache resources can be improved.

Description

Cache resource allocation method, device, electronic device and storage medium

technical field

The present disclosure relates to the technical field of electronic digital data processing, and in particular, to a cache resource allocation method, a cache resource allocation device, electronic equipment, and a storage medium.

Background technique

Cache is a kind of on-chip memory, which is located between CPU (Central Processing Unit, central processing unit)/GPU (Graphics Processing Unit, graphics processing unit) and memory, and can provide fast and small-capacity data reading and writing. The data in the cache is a part of the main memory, which is stored in the cache through a certain mapping relationship, and the data is obtained by comparing the tag information. The mapping relationship is mainly divided into the following three types: The first is direct mapping. In direct mapping, a block of addresses in memory can only be mapped to a fixed location in the cache. The second type is fully connected mapping. In fully associative mapping, an address in memory can be mapped to any location in the cache. The third type is group associative mapping. Group associative mapping is a compromise between direct mapping and fully associative mapping. In set associative mapping, the cache is divided into several sets (sets), and each set has multiple ways (way). A block of addresses in memory can only be mapped to a fixed group, but it can be mapped to a different way in each group. Due to the complexity of physical implementation, in group connection, the number of ways included in each group usually does not exceed 16 or 32. Table 1 shows an exemplary implementation of group associative mapping. In the implementation shown in Table 1, the cache is divided into M+1 groups, and each group includes N+1 ways.

Table 1

road #0 road #1 … Road #N Group #0 data data data data … data data data data Group #M data data data data

Cache utilizes the principle of program locality, which is divided into temporal locality and spatial locality. Time locality means that an address may be accessed repeatedly within a period of time. Spatial locality means that when an address is accessed, nearby addresses are also likely to be accessed. Since the locality exhibited by different programs will also be different, the utilization rate of the cache is also different.

How to improve the utilization rate of cache resources is an urgent technical problem to be solved.

Contents of the invention

The present disclosure provides a technical solution for cache resource allocation.

According to an aspect of the present disclosure, a cache resource allocation method is provided, the processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes multiple shared cache groups, The methods include:

In response to a first data request from any application, acquire first identification information carried in the first data request;

In response to the first data request being a data request corresponding to the first identification information received for the first time, assigning a preset number of shared cache groups to the first identification information.

In a possible implementation manner, the shared cache includes multiple shared cache channels;

The responding to the first data request being a data request corresponding to the first identification information received for the first time, allocating a preset number of shared cache groups to the first identification information includes:

In response to the first data request being a data request corresponding to the first identification information received for the first time, assigning a preset number of shared cache groups among the plurality of shared cache channels to the first identification information.

In a possible implementation manner, the preset number includes a first preset number and a second preset number, and the first preset number is smaller than the second preset number;

The response to the first data request being a data request corresponding to the first identification information received for the first time, respectively assigning a preset number of shared caches in the plurality of shared cache channels to the first identification information group, including:

In response to the first data request being a data request corresponding to the first identification information received for the first time, determining a first reference shared cache channel corresponding to the first identification information from the plurality of shared cache channels, Wherein, the first reference shared cache channel indicates the reference shared cache channel corresponding to the first identification information;

Allocating the first preset number of shared cache groups in the first common shared cache channel to the first identification information, and allocating the first preset number of shared cache groups in the first reference shared cache channel to the first identification information Two preset numbers of shared cache groups, wherein the first common shared cache channel represents a shared cache channel other than the first reference shared cache channel among the plurality of shared cache channels.

In a possible implementation manner, the response to the first data request is a data request corresponding to the first identification information received for the first time, and the first data request is determined from the multiple shared cache channels. The first reference shared cache channel corresponding to the identification information includes:

In response to the first data request being a data request corresponding to the first identification information received for the first time, and there is a shared cache channel that is not determined as a reference shared cache channel among the multiple shared cache channels, from the Among the shared cache channels that are not determined as reference shared cache channels, determine a first reference shared cache channel corresponding to the first identification information.

In a possible implementation, the method further includes:

Acquiring a first hit rate of the first reference shared cache channel for the first identification information, and a second hit rate of the first common shared cache channel for the first identification information;

According to the first hit ratio and the second hit ratio, the number of shared cache groups allocated to the first identification information is adjusted.

In a possible implementation manner, the adjusting the number of shared cache groups allocated to the first identification information according to the first hit rate and the second hit rate includes:

determining a ratio of the first hit rate to the second hit rate;

In response to the ratio being greater than or equal to a first preset threshold, increasing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels; or, in response to the ratio being less than or equal to a first threshold Two preset thresholds, reducing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels; wherein, the first preset threshold is greater than the second preset threshold, and the Both the first preset threshold and the second preset threshold are greater than 1.

In a possible implementation, the method further includes:

Obtain a first request address corresponding to the first data request;

In response to determining that a cache miss occurs in the local cache according to the first request address, acquire a group mask, a group offset, and a flag bit offset corresponding to the first identification information;

According to the second request address corresponding to the first data request, the group mask, the group offset and the flag bit offset, determine the new group bit and new tag information corresponding to the first data request , wherein the second request address is determined according to the first request address;

Searching for target data according to the channel information and the in-row offset address in the second request address, as well as the new group bits and the new label information.

In a possible implementation, the method further includes:

Remapping the first request address to obtain the second request address.

In a possible implementation manner, the first data request is determined according to the second request address corresponding to the first data request, the group mask, the group offset, and the flag bit offset. New group bits and new label information corresponding to the data request, including:

Obtain original group bits and original label information from the second request address;

performing an AND operation on the original group bit and the group mask to obtain the relative position of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information;

determining a new group bit corresponding to the first data request according to the group offset and the relative position;

Determine new tag information corresponding to the first data request according to the original tag information, the flag bit offset, and a specified bit in the original group bits.

In a possible implementation manner, the searching for target data according to the channel information and in-row offset address in the second request address, as well as the new group bit and the new label information includes:

Responding to the fact that the target data cannot be found according to the channel information, the new group bit, the new label information, and the in-line offset address, the target data is acquired from internal memory or external storage, and the target data is writing into the shared cache group corresponding to the new group bit, and returning the target data to the first data request.

In a possible implementation manner, the first identification information includes any of the following:

The identification information determined according to the module called by the application, the identification information determined according to the context identification information, and the identification information determined according to the address range of the target data requested by the first data request in the memory.

According to an aspect of the present disclosure, a cache resource allocation device is provided, the processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes multiple shared cache groups, The device includes: a first acquiring module, configured to acquire first identification information carried in the first data request in response to a first data request from any application; an assigning module, configured to respond to the first data request The data request is a data request corresponding to the first identification information received for the first time, and a preset number of shared cache groups are allocated to the first identification information.

In a possible implementation manner, the shared cache includes multiple shared cache channels; the allocating module is configured to: respond to the first data request corresponding to the first received first identification information , respectively assigning a preset number of shared cache groups in the plurality of shared cache channels to the first identification information.

In a possible implementation manner, the preset quantity includes a first preset quantity and a second preset quantity, and the first preset quantity is smaller than the second preset quantity; the allocation module is used to : In response to the first data request being a data request corresponding to the first identification information received for the first time, from the plurality of shared cache channels, determine the first reference shared cache channel corresponding to the first identification information , wherein, the first reference shared cache channel represents the reference shared cache channel corresponding to the first identification information; the first preset number of shares in the first common shared cache channel are assigned to the first identification information Cache groups, and allocate the second preset number of shared cache groups in the first reference shared cache channel to the first identification information, wherein the first common shared cache channel represents the plurality of shared cache groups Shared cache channels in cache channels other than the first reference shared cache channel.

In a possible implementation manner, the allocating module is configured to: respond to the first data request being a data request corresponding to the first identification information received for the first time, and there are For the shared cache channels not determined as the reference shared cache channels, the first reference shared cache channel corresponding to the first identification information is determined from the shared cache channels not determined as the reference shared cache channels.

In a possible implementation manner, the device further includes: a second obtaining module, configured to obtain a first hit rate of the first reference shared cache channel for the first identification information, and the first common The second hit rate of the shared cache channel for the first identification information; an adjustment module, configured to adjust the shared cache group assigned to the first identification information according to the first hit rate and the second hit rate quantity.

In a possible implementation manner, the adjustment module is configured to: determine a ratio of the first hit rate to the second hit rate; increase the ratio in response to the ratio being greater than or equal to a first preset threshold The number of shared cache groups allocated to the first identification information among the multiple shared cache channels; or, in response to the ratio being less than or equal to a second preset threshold, reducing the number of shared cache groups allocated to the first identification information among the multiple shared cache channels The number of shared cache groups of the first identification information; wherein, the first preset threshold is greater than the second preset threshold, and both the first preset threshold and the second preset threshold are greater than 1.

In a possible implementation manner, the device further includes: a third obtaining module, configured to obtain the first request address corresponding to the first data request; a fourth obtaining module, configured to respond to the The request address determines that a cache miss occurs in the local cache, and obtains the group mask, group offset, and flag bit offset corresponding to the first identification information; the determination module is configured to request the corresponding second The request address, the group mask, the group offset and the flag bit offset determine the new group bit and new tag information corresponding to the first data request, wherein the second request address is based on the The first request address is determined; a search module is configured to search for target data according to the channel information and the in-row offset address in the second request address, as well as the new group bit and the new tag information.

In a possible implementation manner, the device further includes: a remapping module, configured to remap the first request address to obtain the second request address.

In a possible implementation manner, the determining module is configured to: acquire original group bits and original label information from the second request address; perform an AND operation on the original group bits and the group mask, Obtain the relative position of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information; determine the first data request according to the group offset and the relative position The corresponding new group bit: determine the new tag information corresponding to the first data request according to the original tag information, the flag bit offset, and a specified bit in the original group bit.

In a possible implementation manner, the search module is configured to: in response to finding no target data according to the channel information, the new group bit, the new label information, and the in-line offset address, from The target data is acquired from the internal memory or the external storage, the target data is written into the shared cache group corresponding to the new group bit, and the target data is returned to the first data request.

In a possible implementation manner, the first identification information includes any one of the following: identification information determined according to the module called by the application, identification information determined according to the identification information of the context, and information determined according to the first data request The identification information determined by the address range of the requested target data in the memory.

According to an aspect of the present disclosure, there is provided an electronic device, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the memory storage executable instructions to perform the above method.

According to one aspect of the present disclosure, there is provided a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented.

According to an aspect of the present disclosure, there is provided a computer program product, including computer readable codes, or a non-volatile computer readable storage medium bearing computer readable codes, when the computer readable codes are stored in an electronic device During operation, the processor in the electronic device executes the above method.

In an embodiment of the present disclosure, the processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes a plurality of shared cache groups. For the first data request, obtain the first identification information carried in the first data request, and respond to the first data request corresponding to the first identification information received for the first time, send the first identification information to the first data request The information allocates a preset number of shared cache groups, so that the shared cache resources are allocated based on the group. Since the number of groups is larger than the number of ways (for example, a shared cache includes multiple shared cache channels, each shared cache channel includes 256 groups, and the number of ways contained in a group usually does not exceed 16 or 32), therefore, based on The group allocates the shared cache resources, which can more easily realize the reasonable allocation of the shared cache resources, and can improve the utilization rate of the shared cache resources.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings here are incorporated into the description and constitute a part of the present description. These drawings show embodiments consistent with the present disclosure, and are used together with the description to explain the technical solution of the present disclosure.

FIG. 1 shows a schematic diagram of a cache structure of a GPU.

FIG. 2 shows a flow chart of a cache resource allocation method provided by an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of group-by-group allocation of identification information for data requests in the method for allocating cache resources provided by an embodiment of the present disclosure.

FIG. 4 shows a schematic diagram of a cache structure of a GPU provided by an embodiment of the present disclosure.

FIG. 5 shows a schematic diagram of a cache lookup method provided by an embodiment of the present disclosure.

Fig. 6 shows a block diagram of an apparatus for allocating cache resources provided by an embodiment of the present disclosure.

FIG. 7 shows a block diagram of an electronic device 1900 provided by an embodiment of the present disclosure.

Detailed ways

Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements. While various aspects of the embodiments are shown in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations. In addition, the term "at least one" herein means any one of a variety or any combination of at least two of the more, for example, including at least one of A, B, and C, which may mean including from A, Any one or more elements selected from the set formed by B and C.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present disclosure may be practiced without some of the specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art have not been described in detail so as to obscure the gist of the present disclosure.

FIG. 1 shows a schematic diagram of a cache structure of a GPU (Graphics Processing Unit, graphics processor). There are usually at least two levels of cache structures in a GPU system. In the example shown in Figure 1, the GPU system includes two levels of cache.

There are multiple computing unit clusters (GPU clusters) on the GPU, and each computing unit cluster has multiple computing units inside. The local cache (Local Cache) can be considered as the first-level cache, which is only accessed by the corresponding computing unit cluster. In Figure 1, it includes K+1 computing unit clusters (computing unit cluster 0 to computing unit cluster K), and K+1 local caches corresponding to the K+1 computing unit clusters (local cache 0 to local Cache K). Wherein, the local cache may also be called a local cache, a level 1 cache, an L1 cache, etc., which is not limited here.

The interconnect module (interconnect) can be used to pass the request to the corresponding external storage block.

Shared cache (Shared Cache) can be considered as a second-level cache. The shared cache can be accessed by all computing unit clusters. Wherein, the shared cache may also be called level 2 cache, L2 cache, global cache, etc., which is not limited here. In FIG. 1 , there are L+1 shared cache channels, which are shared cache channel 0 to shared cache channel L respectively.

In addition, in FIG. 1 , it includes L+1 DRAM banks (Dynamic Random Access Memory banks, dynamic random access memory banks), which are DRAM banks 0 to DRAM banks L respectively.

Wherein, there may be a one-to-one or many-to-one relationship between the shared cache channel and the DRAM memory bank.

Since the GPU can process many operations or applications in parallel, the data locality of these operations and applications is not necessarily the same, so the requirements for the cache are also different. Even if there is no data sharing between applications, putting them in the shared cache will affect the operation. efficiency.

Since the shared cache may be used by multiple threads, multiple cores, or multiple different applications, and the cache size or data characteristics required by each application are different, it is best to treat them differently to avoid conflicts and allocate cache resources reasonably. The related technology adopts a method of way partitioning (way partitioning) to allocate different ways to different applications. Table 2 shows another exemplary implementation of group associative mapping. In the implementation manner shown in Table 2, the cache is divided into M+1 groups, and each group includes 4 ways.

Table 2

road #0 road #1 road #2 road #3 Group #0 data data data data … data data data data Group #M data data data data

In an example divided by the number of ways, way 0 and way 1 only store data of application A, way 2 only stores data of application B, way 3 only stores data of application C. This way different applications will not interfere with each other.

In the actual physical implementation of this method divided by the number of ways, the number of ways in each group is limited (the number of ways in each group usually does not exceed 16 or 32), when the number of requesters exceeds When the number of ways is large (common in GPU applications), allocation by way has limitations, resulting in unreasonable allocation of resources.

An embodiment of the present disclosure provides a cache resource allocation method. The processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes multiple shared cache groups. By responding to A first data request from any application, acquiring first identification information carried in the first data request, and responding to the fact that the first data request is a data request corresponding to the first identification information received for the first time, A preset number of shared cache groups are allocated to the first identification information, so that shared cache resources are allocated based on groups. Since the number of groups is larger than the number of ways (for example, a shared cache includes multiple shared cache channels, each shared cache channel includes 256 groups, and the number of ways contained in a group usually does not exceed 16 or 32), therefore, based on The group allocates the shared cache resource, which can more easily realize the reasonable allocation of the shared cache resource, and can improve the utilization rate of the shared cache resource.

The method for allocating cache resources provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 2 shows a flow chart of a cache resource allocation method provided by an embodiment of the present disclosure. The cache resource allocation method is used to allocate cache (Cache) resources. In a possible implementation manner, the cache resource allocation method may be executed by a cache resource allocation apparatus, for example, the cache resource allocation method may be executed by a terminal device or a server or other electronic equipment. Wherein, the terminal device may be user equipment (User Equipment, UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (Personal Digital Assistant, PDA), handheld device, computing device, vehicle-mounted device, or Wearable equipment etc. In some possible implementation manners, the method for allocating cache resources may be implemented in a manner in which a processor invokes computer-readable instructions stored in a memory. As shown in FIG. 2 , the cache resource allocation method includes steps S21 to S22.

In step S21, in response to a first data request from any application, first identification information carried in the first data request is acquired.

In step S22, in response to the first data request being a data request corresponding to the first identification information received for the first time, assigning a preset number of shared cache groups to the first identification information.

In an embodiment of the present disclosure, the processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes multiple shared cache groups.

Wherein, the processor system may be a GPU (Graphics Processing Unit, graphics processing unit) system or a CPU (Central Processing Unit, central processing unit) system, which is not limited herein. In the following, description will be made by taking the processor system as an example of a GPU system.

In a possible implementation manner, the processor system may include a two-level cache. Wherein, the first-level cache may be a local cache, and the second-level cache may be a shared cache.

In another possible implementation manner, the processor system may include a L3 cache. Wherein, the first-level cache and the second-level cache may be local caches, and the third-level cache may be a shared cache.

In the embodiment of the present disclosure, the shared cache may include at least one channel, that is, the shared cache may include at least one shared cache channel. Wherein, the shared cache channel indicates a shared cache channel. Any shared cache channel can be accessed by different computing unit clusters.

In a possible implementation manner, the shared cache may include multiple shared cache channels. For example, the number of shared cache channels may be 16, 24, 32, 48, etc., which is not limited here. In this implementation, each shared cache channel may include multiple sets (sets), that is, each shared cache channel may include multiple shared cache sets. For example, each shared cache channel may respectively include 256 shared cache groups.

In the embodiment of the present disclosure, each shared cache group may include multiple ways (way). For example, the number of ways in each shared cache group can be 4, 8, 16, 32, and so on.

In this embodiment of the present disclosure, the first data request may be any data request sent by any application. The first identification information may identify the identification information carried in the first data request.

Any application can make a large number of data requests. The identification information carried in different data requests sent by the same application may be different or the same. The identification information carried in different data requests sent by different applications may be different or the same.

In a possible implementation manner, the first identification information includes any one of the following: identification information determined according to the module called by the application, identification information determined according to the identification information of the context, and information determined according to the first data request The identification information determined by the address range of the requested target data in the memory.

As an example of this implementation manner, the identification information of the data request may be determined according to the module called by the application. Taking the GPU as an example, the GPU module invoked by the application may include a dedicated unit in the GPU for processing coordinate transformation, a dedicated unit in the GPU for texture compression, etc., which are not limited here. In this example, when the same application calls the same module to send two data requests, the identification information of the two data requests is the same; when the same application calls two different modules to send two data requests, the identification information of the two data requests The identification information is different; when two applications call the same module to issue data requests respectively, the identification information of the two data requests is the same; when two applications call two different modules to issue data requests respectively, the identification information of the two data requests The information is different. For example, the identification information of the first data request sent by the application A1 calling the module M1 is the same as the identification information of the second data request sent by the application A1 calling the module M1, and the first data request sent by the application A1 calling the module M1 is the same as the first data request sent by the application A1 calling the module M2. The identification information of the three data requests is different. The identification information of the first data request issued by application A1 calling module M1 is the same as the identification information of the fourth data request issued by application A2 calling module M1. The first data request issued by application A1 calling module M1 is the same as that of application A2. The identification information of the fifth data request sent by the calling module M2 is different.

As another example of this implementation manner, the identification information of the data request may be determined according to the identification information of the context. In this example, the identification information of the context may refer to the identification information of the application. In this example, different data requests sent by the same application have the same identification information, and data requests sent by different applications have different identification information.

As another example of this implementation manner, the identification information of the data request may be determined according to the address range of the target data requested by the data request in the memory. Different applications can access the same address in the memory, therefore, the identification information of data requests sent by different applications may be the same. The same application can access different addresses in the memory, therefore, the identification information of different data requests issued by the same application may be different.

In this implementation, the first identification information is determined according to the module called by the application, or the first identification information is determined according to the identification information of the context, or the address in the memory of the target data requested by the first data request The interval determines the first identification information, so that the identification information of the data request can be reasonably determined, thereby helping to achieve a more reasonable allocation of shared cache resources.

Although the above implementation manners describe the determination manner of the identification information of the data request as above, those skilled in the art can understand that the present disclosure should not be limited thereto. Those skilled in the art may flexibly determine the manner of determining the identification information of the data request according to actual application scenario requirements and/or personal preferences.

In a possible implementation manner, the shared cache includes multiple shared cache channels; the first data request corresponding to the first identification information received in response to the first data request sends the Allocating a preset number of shared cache groups with one piece of identification information includes: in response to the first data request being a data request corresponding to the first identification information received for the first time, allocating the multiple cache groups to the first identification information respectively A preset number of shared cache groups in each shared cache channel.

For example, the shared cache includes 16 shared cache channels, namely shared cache channel 0 to shared cache channel 15, then, in response to the first data request, the data corresponding to the first identification information received for the first time may be The request is to allocate a preset number of shared cache groups among the 16 shared cache channels to the first identification information.

In this implementation manner, by responding to the first data request being a data request corresponding to the first identification information received for the first time, the first identification information is respectively allocated to the first identification information in the plurality of shared cache channels. Set the number of shared cache groups, which is beneficial to balance the requests obtained by each shared cache channel.

As an example of this implementation, the preset number includes a first preset number and a second preset number, and the first preset number is smaller than the second preset number; the response to the first A data request is a data request corresponding to the first identification information received for the first time, assigning a preset number of shared cache groups in the plurality of shared cache channels to the first identification information, including: responding to the The first data request is a data request corresponding to the first identification information received for the first time, and the first reference shared cache channel corresponding to the first identification information is determined from the plurality of shared cache channels, wherein the The first reference shared cache channel indicates a reference shared cache channel (reference cache) corresponding to the first identification information; assigning the first preset number of shares in the first common shared cache channel to the first identification information Cache groups, and allocate the second preset number of shared cache groups in the first reference shared cache channel to the first identification information, wherein the first common shared cache channel represents the plurality of shared cache groups Shared cache channels in cache channels other than the first reference shared cache channel.

In this example, the second preset amount may be 2 times, 1.5 times, 3 times, etc. of the first preset amount, which is not limited here. The first preset number may indicate a preset number corresponding to a common shared cache channel, and the second preset number may indicate a preset number corresponding to a reference shared cache channel. The first reference shared cache channel may indicate a reference shared cache channel corresponding to the first identification information. The reference shared cache channels corresponding to different identification information may be different. The number of reference shared cache channels corresponding to any identification information may be one or more than two. For example, the number of reference shared cache channels corresponding to any piece of identification information may be one. For any identification information, a common shared cache channel may represent a shared cache channel other than the reference shared cache channel corresponding to the identification information. For example, if the number of shared cache channels is 16, and the number of reference shared cache channels is 1, then the number of common shared cache channels is 15.

In one example, the first preset number is 16, and the second preset number is 32. In this example, each first common shared cache channel may allocate 16 shared cache groups for the first identification information, and the first reference shared cache channel may allocate 32 shared cache groups for the first identification information.

In this example, by responding to the first data request being a data request corresponding to the first identification information received for the first time, from the multiple shared cache channels, determine the first data request corresponding to the first identification information A reference shared cache channel, assigning the first preset number of shared cache groups in the first common shared cache channel to the first identification information, and assigning the first reference shared cache to the first identification information The second preset number of shared cache groups in the channel can thereby determine the size of the shared cache resource required by the data request corresponding to the first identification information based on the reference to the shared cache channel, thereby helping to improve the utilization of the shared cache Rate.

In an example, the response to the first data request is a data request corresponding to the first identification information received for the first time, and from the plurality of shared cache channels, determine the The first reference shared cache channel, including: responding to the first data request being a data request corresponding to the first identification information received for the first time, and there is one of the multiple shared cache channels that is not determined to be a reference shared cache The shared cache channel of the channel determines the first reference shared cache channel corresponding to the first identification information from the shared cache channels not determined as the reference shared cache channel.

In this example, for different identification information, selection of reference shared cache channels should be as balanced as possible. For example, identification information of 4 shared cache channels and 3 data requests. Among them, the four shared cache channels are shared cache channel 0, shared cache channel 1, shared cache channel 2, and shared cache channel 3, and the identification information of the three data requests is the first identification information (ID0) and the second identification information (ID1) and third identification information (ID2). For example, after the shared cache channel 2 is selected as the reference shared cache channel for the first identification information, when the reference shared cache channel is selected for the second identification information, the shared cache channel 2 can be avoided, for example, the shared cache channel 3 can be selected as the reference shared cache channel. cache channel. When selecting the reference shared cache channel for the third identification information, shared cache channel 2 and shared cache channel 3 may be avoided, for example, shared cache channel 0 or shared cache channel 1 is selected as the reference shared cache channel.

In this example, by responding to the first data request is the data request corresponding to the first identification information received for the first time, and among the multiple shared cache channels there is a shared The cache channel determines the first reference shared cache channel corresponding to the first identification information from the shared cache channels not determined as the reference shared cache channel, thereby improving the utilization rate of shared cache resources.

In another example, the response to the first data request is a data request corresponding to the first identification information received for the first time, and determining from the multiple shared cache channels that the first identification information corresponds to The first reference shared cache channel includes: in response to the first data request being the data request corresponding to the first identification information received for the first time, assigning the shared cache channel with the largest remaining capacity among the multiple shared cache channels , determine as the first reference shared cache channel corresponding to the first identification information.

In another example, the response to the first data request is a data request corresponding to the first identification information received for the first time, and determining from the multiple shared cache channels that the first identification information corresponds to The first reference shared cache channel includes: in response to the first data request being a data request corresponding to the first identification information received for the first time, randomly selecting the first shared cache channel from the plurality of shared cache channels The first reference shared cache channel corresponding to the identification information.

In another example, for different identification information, reference shared cache channels may be selected sequentially. For example, for the first time, shared buffer channel 0 is selected as the reference shared buffer channel, for the second time, shared buffer channel 1 is selected as the reference shared buffer channel, for the third time, shared buffer channel 2 is selected as the reference shared buffer channel, and so on.

In an example, the method further includes: obtaining a first hit rate of the first reference shared cache channel for the first identification information, and a hit ratio of the first common shared cache channel for the first identification information A second hit rate: adjusting the number of shared cache groups allocated to the first identification information according to the first hit rate and the second hit rate.

In this example, the first hit rate and the second hit rate may be counted at a preset frequency, so that shared cache resources allocated to each piece of identification information may be adjusted at a preset frequency.

In this example, when there are multiple common shared cache channels, the average or median of the hit rates of each common shared cache channel with respect to the first identification information may be determined as the second hit rate.

In this example, by obtaining the first hit rate of the first reference shared cache channel for the first identification information and the second hit rate of the first common shared cache channel for the first identification information, And according to the first hit rate and the second hit rate, adjust the number of shared cache groups allocated to the first identification information, thereby based on the performance of the first reference shared cache channel and the first common shared cache channel difference, and dynamically adjust the shared cache resource allocated to the first identification information, thereby further improving the utilization rate of the shared cache resource and improving the operating efficiency of different applications.

In an example, the adjusting the number of shared cache groups allocated to the first identification information according to the first hit rate and the second hit rate includes: determining the first hit rate and the second hit rate The ratio of the second hit rate; in response to the ratio being greater than or equal to a first preset threshold, increasing the number of shared cache groups allocated to the first identification information in the plurality of shared cache channels; or, in response to The ratio is less than or equal to a second preset threshold, and the number of shared cache groups allocated to the first identification information in the plurality of shared cache channels is reduced; wherein, the first preset threshold is greater than the second A preset threshold, and both the first preset threshold and the second preset threshold are greater than 1.

Wherein, the first preset threshold and the second preset threshold can be configured through registers. The second preset threshold may be slightly greater than 1.

Since the number of shared cache groups allocated by the first identification information in the first reference shared cache channel is greater than the number of shared cache groups allocated by the first identification information in the first common shared cache channel, if more shared If the cache resource brings a significantly higher hit rate (for example, the ratio is greater than or equal to the first preset threshold), it can be considered that the increase in the cache resource has obvious benefits for improving the hit rate, and then it can be considered to increase the first identification information. cache space. If more shared cache resources do not bring about a significant increase in the hit rate (for example, the ratio is less than or equal to the second preset threshold), it can be considered that the increase in cache resources is not beneficial to the increase in the hit rate, and then the allocation to A shared cache resource of the first identification information.

In the above example, when the ratio is smaller than the first preset threshold and larger than the second preset threshold, the number of shared cache groups corresponding to the first identification information may not be changed.

In addition, when the allocation of cache resources is changed, in order to maintain data consistency, additional cache maintenance operations, such as clearing the cache (flush operation) and clearing (invalidate), can be used.

In the above example, by determining the ratio of the first hit rate to the second hit rate, in response to the ratio being greater than or equal to a first preset threshold, increasing the The number of shared cache groups of the first identification information, or, in response to the ratio being less than or equal to a second preset threshold, reducing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels quantity, wherein, the first preset threshold is greater than the second preset threshold, and both the first preset threshold and the second preset threshold are greater than 1, thereby further improving the utilization of shared cache resources Rate.

In a possible implementation, the method further includes: obtaining a first request address corresponding to the first data request; in response to determining that a cache miss occurs in the local cache according to the first request address, obtaining the The group mask, group offset and flag bit offset corresponding to the first identification information; according to the second request address corresponding to the first data request, the group mask, the group offset and the flag bit The offset is to determine the new set of bits and new tag information corresponding to the first data request, wherein the second request address is determined according to the first request address; according to the channel information and The offset address within the row, as well as the new group bits and the new tag information, are used to find the target data.

In this implementation manner, the first request address may indicate the request address carried in the first data request. The first request address may be a virtual address or a physical address.

As an example of this implementation, the set mask (set mask), set offset (set offset) and tag shift (tag shift) corresponding to the first identification information may be obtained from the ID-cache group mapping table . Wherein, the group mask may be used to determine the number of shared cache groups allocated to the first identification information. For example, the group mask set mask=0x0f may indicate that the number of shared cache groups allocated to the first identification information is 16. The group offset may indicate the starting position of the shared cache group allocated to the first identification information. For example, the group offset set offset=0x10 may indicate that the starting position of the shared cache group of the first identification information is the 17th group in the shared cache channel. The flag bit offset can be used to determine the shift amount of the label.

In this implementation, the new group bit indicates the group bit used to store the target data requested by the first data request. The new tag information may represent new tag information corresponding to the target data. The new tag information can be stored in the shared cache group corresponding to the target data for subsequent cache lookup and hit-or-miss judgment.

In this implementation manner, the sizes of group masks corresponding to different identification information may be the same or different. For example, the group mask corresponding to each identification information is 0x0f. For another example, the data request may carry the request size of the shared cache group, and the number of shared cache groups assigned to the identification information of the data request may be determined according to the request size.

In this implementation, by acquiring the first request address corresponding to the first data request, in response to determining that a cache miss occurs in the local cache according to the first request address, the group mask corresponding to the first identification information is acquired code, group offset, and flag bit offset, and determine the first data request according to the second request address corresponding to the first data request, the group mask, the group offset, and the flag bit offset A new set of bits and new label information corresponding to a data request, wherein the second request address is determined according to the first request address, according to the channel information and the in-row offset address in the second request address, and the The new group bit and the new tag information are used to search for the target data, thereby realizing the allocation of the shared cache group based on the identification information of the data request.

As an example of this implementation manner, the method further includes: remapping the first request address to obtain the second request address.

In an example, the addresses sent by the GPU (that is, the request addresses carried in the data requests) can be scrambled through address interleaving and hash operations, so as to be evenly allocated to different shared cache channels.

In this example, the second request address is obtained by remapping the first request address, so that the requests obtained by each shared cache channel can be balanced, and the utilization rate of shared cache resources can be improved.

As another example of this implementation, the first request address is a virtual address; the method further includes: converting the first request address from a virtual address to a physical address by a memory management unit to obtain the second request address. In this example, the second request address is a physical address.

As another example of this implementation manner, the first request address is a physical address, and the first request address may be directly used as the second request address.

As an example of this implementation, the first data is determined according to the second request address corresponding to the first data request, the group mask, the group offset and the flag bit offset Requesting corresponding new group bits and new label information includes: obtaining original group bits and original label information from the second request address; and performing an AND operation on the original group bits and the group mask to obtain the The relative position of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information; according to the group offset and the relative position, determine the new corresponding to the first data request Group bit: determine new tag information corresponding to the first data request according to the original tag information, the flag bit offset, and a specified bit in the original group bit.

For example, the second request address includes 32 bits, expressed as 0x12345678 in hexadecimal. Among them, the upper 4 bits (0x1) are channel information; the 16th to 27th bits (0x234) are the original label information; the 8th to 15th bits (0x56) are the original group bits; the lower 8 bits (0x78) are the offset addresses in the row, It is used to determine its access to the 0x78th byte of data in the cache line.

For example, group mask set mask=0x0f, group offset set offset=0x10, and tag shift=0x4.

By ANDing the original group bit 0x56 and the group mask 0x0f, the relative position 0x06 of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information can be obtained. Wherein, the original group bit and the group mask are respectively converted into binary to obtain 0000010100000110 and 0000000011111111. 0000010100000110&0000000011111111=0000000000000110, thereby determining that the target data requested by the first data request is in the multiple shared cache groups corresponding to the first identification information Relative to The location is 0x06.

The new group bit 0x16 corresponding to the first data request can be obtained by adding the group offset and the relative position. That is, according to the group mask, the 8th to 11th bits in the second request address are selected as part of the new group bits, and an offset of 0x10 is added.

According to the original tag information 0x234, the flag bit offset 0x4 and the original group bit 0x5, the new tag information 0x2345 can be obtained.

Thus, the new request address 0x123451678 can be obtained. In this example, the 8th to 11th bits in the new request address are determined according to the second request address, and a total of 16 shared cache groups are allocated to the first identification information.

In this example, the original group bits and original label information are obtained from the second request address, and the original group bits are ANDed with the group mask to obtain the requested data in the first data request. The relative position of the target data in the multiple shared cache groups corresponding to the first identification information, according to the group offset and the relative position, determine the new group bit corresponding to the first data request, and according to the The original tag information, the offset of the flag bit, and the specified bit in the original group bit determine the new tag information corresponding to the first data request, so that the shared cache group can be realized based on the identification information of the data request Assignment, and when determining the new label information, the designated bit in the original group bit is retained, so that the integrity of the original address can be maintained.

FIG. 3 shows a schematic diagram of group-by-group allocation of identification information for data requests in the method for allocating cache resources provided by an embodiment of the present disclosure. In FIG. 3 , the request ID represents the identification information carried in the data request, for example, the first identification information carried in the first data request. The group mask, group offset and flag bit offset corresponding to the first identification information may be obtained from the ID-cache group mapping table. The ID-cache group mapping table shown in FIG. 3 includes the mapping relationship between ID0~IDN and group mask, group offset, and flag bit offset. The original label information, original group bit and in-line offset address can be obtained from the request address (eg, the second request address). A bitwise AND operation may be performed on the original group bits and the group mask to obtain the relative position of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information. The group offset can be added to the relative position to obtain a new group bit. The original label information, the flag bit offset, and the specified bit in the original group bits can be processed by a shifter to obtain new label information. Cache lookup can be performed based on channel information, in-line offset address, new group bit, and new tag information.

It should be noted that the above definition of group mask and group offset is just an example, not the only way of definition. For example, the same group-by-group allocation function can also be realized by means of new group bit=original group bit+group offset&group mask.

As an example of this implementation, the searching for the target data according to the channel information and the in-line offset address in the second request address, as well as the new group bit and the new tag information includes: responding to The channel information, the new group bit, the new label information and the offset address in the row, if the target data cannot be found, the target data is obtained from the internal memory or external storage, and the target data is written into the The new group is placed in the corresponding shared cache group, and the target data is returned to the first data request.

In this example, if the first data request is a data request corresponding to the first identification information received for the first time, no target data can be found in the shared cache channel. At this time, the target data may be obtained from the internal memory or external storage, written into the shared cache group corresponding to the new group bit, and returned to the first data request.

In this example, the target data is obtained from internal memory or external storage in response to the fact that the target data cannot be found according to the channel information, the new group bit, the new label information and the in-row offset address , write the target data into the shared cache group corresponding to the new group bit, and return the target data to the first data request, so that the target data can be written into the shared cache group corresponding to the first identification information in the cache group.

FIG. 4 shows a schematic diagram of a cache structure of a GPU provided by an embodiment of the present disclosure. Wherein, the part that overlaps with FIG. 1 will not be repeated here. In Figure 4, through address interleaving and hashing operations, the addresses issued by the GPU (that is, the request addresses carried by the data request) can be scrambled to be evenly allocated to different shared cache channels. In addition, for the identification information carried in the data request, a reference shared cache channel corresponding to the identification information may be selected from each shared cache channel.

FIG. 5 shows a schematic diagram of a cache lookup method provided by an embodiment of the present disclosure. As shown in Figure 5, a local cache lookup may be performed in response to a data request. If it hits in the local cache (that is, the target data requested by the data request is found in the local cache), the target data is fetched from the local cache and returned to the data request. If there is a miss in the local cache (that is, a cache miss occurs in the local cache), the first request address carried in the data request can be converted into the second request address through address interleaving and hash operation. The shared cache channel corresponding to the target data may be determined according to the channel information in the second request address, and the data request may be sent to the corresponding shared cache channel. The corresponding group mask, group offset and flag bit offset may be obtained from the ID-cache group mapping table according to the identification information carried in the data request. The original label information, the original group bit and the offset address in the row can be obtained from the second request address. A bitwise AND operation may be performed on the original group bits and the group mask to obtain the relative position of the target data requested by the data request in the plurality of shared cache groups corresponding to the identification information. The group offset can be added to the relative position to obtain a new group bit. The new tag information can be obtained by processing the original tag information, the offset of the flag bit, and the designated bit in the original group bit. A shared cache lookup can be performed on the shared cache channel corresponding to the target data according to the channel information, the in-line offset address, the new group bit and the new tag information. If it hits in the shared cache, the target data is fetched from the shared cache and returned to the data request. If there is a miss (that is, missing) in the shared cache, the data request can be sent to the corresponding DRAM storage bank, the target data is taken out from the DRAM storage bank and the target data is returned to the data request, and can be judged according to the cache request control signal Whether to fill the target data into the cache.

The cache resource allocation method provided by the embodiment of the present disclosure is described below through a specific application scenario. In this application scenario, the first identification information carried in the first data request may be acquired in response to the first data request from any application. Wherein, the first identification information includes any of the following items: identification information determined according to the module called by the application, identification information determined according to the identification information of the context, and target data requested according to the first data request in the internal memory. The identification information determined by the address range in . In response to the first data request being a data request corresponding to the first identification information received for the first time, and there is a shared cache channel among the multiple shared cache channels that is not determined to refer to the shared cache channel, from the Among the shared cache channels that are not determined as reference shared cache channels, determine the first reference shared cache channel corresponding to the first identification information, where the first reference shared cache channel indicates the first reference shared cache channel corresponding to the first identification information Referring to the shared cache channel, assigning the first preset number of shared cache groups in the first common shared cache channel to the first identification information, and assigning the first reference shared cache channel to the first identification information The second preset number of shared cache groups, wherein the first common shared cache channel represents a shared cache channel other than the first reference shared cache channel among the plurality of shared cache channels.

In response to determining that a cache miss occurs in the local cache according to the first request address, the group mask, group offset, and flag bit offset corresponding to the first identification information may be acquired. The second request address may be obtained by remapping the first request address through address interleaving and hash operation. The original group bit and original tag information may be obtained from the second request address; and the original group bit and the group mask are performed to obtain the target data requested by the first data request in the The relative position in the multiple shared cache groups corresponding to the first identification information; according to the group offset and the relative position, determine the new group bit corresponding to the first data request; according to the original tag information, the The offset of the flag bit and the specified bit in the original set of bits determine the new tag information corresponding to the first data request. A cache lookup may be performed according to the channel information and the in-line offset address in the second request address, as well as the new group bit and the new tag information.

The shared cache resource allocated to the first identification information may be adjusted at a preset frequency. For example, a first hit rate of the first reference shared cache channel for the first identification information and a second hit rate of the first common shared cache channel for the first identification information may be obtained; determine the The ratio of the first hit rate to the second hit rate; in response to the ratio being greater than or equal to a first preset threshold, increasing the shared cache group allocated to the first identification information among the multiple shared cache channels or, in response to the ratio being less than or equal to a second preset threshold, reducing the number of shared cache groups allocated to the first identification information among the multiple shared cache channels; wherein, the first preset The threshold is set to be greater than the second preset threshold, and both the first preset threshold and the second preset threshold are greater than 1.

It can be understood that the above-mentioned method embodiments mentioned in this disclosure can all be combined with each other to form a combined embodiment without violating the principle and logic. Due to space limitations, this disclosure will not repeat them. Those skilled in the art can understand that, in the above method in the specific implementation manner, the specific execution order of each step should be determined according to its function and possible internal logic.

In addition, the present disclosure also provides cache resource allocation devices, electronic equipment, computer-readable storage media, and computer program products, all of which can be used to implement any cache resource allocation method provided in the present disclosure. The corresponding technical solutions and technical effects can be found in The corresponding records in the method part will not be repeated here.

Fig. 6 shows a block diagram of an apparatus for allocating cache resources provided by an embodiment of the present disclosure. In an embodiment of the present disclosure, the processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes multiple shared cache groups. As shown in Figure 6, the cache resource allocation device includes:

The first acquiring module 61 is configured to acquire first identification information carried in the first data request in response to a first data request from any application;

The allocation module 62 is configured to allocate a preset number of shared cache groups to the first identification information in response to the first data request being a data request corresponding to the first identification information received for the first time.

In a possible implementation manner, the shared cache includes multiple shared cache channels;

The distribution module 62 is used for:

In response to the first data request being a data request corresponding to the first identification information received for the first time, assigning a preset number of shared cache groups among the plurality of shared cache channels to the first identification information.

In a possible implementation manner, the preset number includes a first preset number and a second preset number, and the first preset number is smaller than the second preset number;

The distribution module 62 is used for:

In response to the first data request being a data request corresponding to the first identification information received for the first time, determining a first reference shared cache channel corresponding to the first identification information from the plurality of shared cache channels, Wherein, the first reference shared cache channel indicates the reference shared cache channel corresponding to the first identification information;

Allocating the first preset number of shared cache groups in the first common shared cache channel to the first identification information, and allocating the first preset number of shared cache groups in the first reference shared cache channel to the first identification information Two preset numbers of shared cache groups, wherein the first common shared cache channel represents a shared cache channel other than the first reference shared cache channel among the plurality of shared cache channels.

In a possible implementation manner, the allocation module 62 is used to:

In response to the first data request being a data request corresponding to the first identification information received for the first time, and there is a shared cache channel that is not determined as a reference shared cache channel among the multiple shared cache channels, from the Among the shared cache channels that are not determined as reference shared cache channels, determine a first reference shared cache channel corresponding to the first identification information.

In a possible implementation manner, the device further includes:

A second acquiring module, configured to acquire a first hit rate of the first reference shared cache channel for the first identification information, and a second hit rate of the first common shared cache channel for the first identification information ;

An adjustment module, configured to adjust the number of shared cache groups allocated to the first identification information according to the first hit rate and the second hit rate.

In a possible implementation manner, the adjustment module is used for:

determining a ratio of the first hit rate to the second hit rate;

In response to the ratio being greater than or equal to a first preset threshold, increasing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels; or, in response to the ratio being less than or equal to a first threshold Two preset thresholds, reducing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels; wherein, the first preset threshold is greater than the second preset threshold, and the Both the first preset threshold and the second preset threshold are greater than 1.

In a possible implementation manner, the device further includes:

A third obtaining module, configured to obtain a first request address corresponding to the first data request;

A fourth acquiring module, configured to acquire a group mask, a group offset, and a flag bit offset corresponding to the first identification information in response to determining that a cache miss occurs in the local cache according to the first request address;

A determining module, configured to determine a new group corresponding to the first data request according to the second request address corresponding to the first data request, the group mask, the group offset, and the flag bit offset bit and new tag information, wherein the second request address is determined according to the first request address;

A search module, configured to search for target data according to the channel information and the in-row offset address in the second request address, as well as the new group bits and the new tag information.

In a possible implementation manner, the device further includes:

A remapping module, configured to remap the first request address to obtain the second request address.

In a possible implementation manner, the determination module is used for:

Obtain original group bits and original label information from the second request address;

performing an AND operation on the original group bit and the group mask to obtain the relative position of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information;

determining a new group bit corresponding to the first data request according to the group offset and the relative position;

Determine new tag information corresponding to the first data request according to the original tag information, the flag bit offset, and a specified bit in the original group bits.

In a possible implementation manner, the search module is used to:

Responding to the fact that the target data cannot be found according to the channel information, the new group bit, the new label information, and the in-line offset address, the target data is acquired from internal memory or external storage, and the target data is writing into the shared cache group corresponding to the new group bit, and returning the target data to the first data request.

In a possible implementation manner, the first identification information includes any of the following:

The identification information determined according to the module called by the application, the identification information determined according to the context identification information, and the identification information determined according to the address range of the target data requested by the first data request in the memory.

In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments, and its specific implementation and technical effects can refer to the descriptions of the above method embodiments, for It is concise and will not be repeated here.

An embodiment of the present disclosure also provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the foregoing method is implemented. Wherein, the computer-readable storage medium may be a non-volatile computer-readable storage medium, or may be a volatile computer-readable storage medium.

An embodiment of the present disclosure also proposes a computer program, including computer readable codes. When the computer readable codes are run in an electronic device, a processor in the electronic device executes the above method.

An embodiment of the present disclosure also provides a computer program product, including computer-readable codes, or a non-volatile computer-readable storage medium carrying computer-readable codes, when the computer-readable codes are run in an electronic device , the processor in the electronic device executes the above method.

An embodiment of the present disclosure also provides an electronic device, including: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory instruction to perform the above method.

Electronic devices may be provided as terminals, servers, or other forms of devices.

FIG. 7 shows a block diagram of an electronic device 1900 provided by an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a terminal or a server. Referring to FIG. 7 , electronic device 1900 includes processing component 1922 , which further includes one or more processors, and a memory resource represented by memory 1932 for storing instructions executable by processing component 1922 , such as application programs. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input/output interface 1958 (I/O interface). The electronic device 1900 can operate based on the operating system stored in the memory 1932, such as the Microsoft server operating system (Windows Server ^TM ), the graphical user interface-based operating system (MacOS X ^TM ) introduced by Apple Inc., and the multi-user and multi-process computer operating system ( Unix ^TM ), a free and open-source Unix-like operating system (Linux ^TM ), an open-source Unix-like operating system (FreeBSD ^TM ), or similar.

In an exemplary embodiment, there is also provided a non-transitory computer-readable storage medium, such as the memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to implement the above method.

The present disclosure can be a system, method and/or computer program product. A computer program product may include a computer readable storage medium having computer readable program instructions thereon for causing a processor to implement various aspects of the present disclosure.

A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media include: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or flash memory), static random access memory (SRAM), compact disc read only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded device, such as a printer with instructions stored thereon A hole card or a raised structure in a groove, and any suitable combination of the above. As used herein, computer-readable storage media are not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., pulses of light through fiber optic cables), or transmitted electrical signals.

Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or downloaded to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or a network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .

Computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or Source or object code written in any combination, including object-oriented programming languages—such as Smalltalk, C++, etc., and conventional procedural programming languages—such as the “C” language or similar programming languages. Computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement. In cases involving a remote computer, the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as through the Internet using an Internet service provider). connect). In some embodiments, electronic circuits, such as programmable logic circuits, field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs), can be customized by utilizing state information of computer-readable program instructions, which can Various aspects of the present disclosure are implemented by executing computer readable program instructions.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It should be understood that each block of the flowcharts and/or block diagrams, and combinations of blocks in the flowcharts and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that when executed by the processor of the computer or other programmable data processing apparatus , producing an apparatus for realizing the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause computers, programmable data processing devices and/or other devices to work in a specific way, so that the computer-readable medium storing instructions includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks in flowcharts and/or block diagrams.

It is also possible to load computer-readable program instructions into a computer, other programmable data processing device, or other equipment, so that a series of operational steps are performed on the computer, other programmable data processing device, or other equipment to produce a computer-implemented process , so that instructions executed on computers, other programmable data processing devices, or other devices implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

The computer program product can be specifically realized by means of hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), etc. wait.

The above descriptions of the various embodiments tend to emphasize the differences between the various embodiments, the same or similar points can be referred to each other, and for the sake of brevity, details are not repeated herein.

If the technical solutions of the embodiments of the present disclosure involve personal information, the products applying the technical solutions of the embodiments of the present disclosure have clearly notified the personal information processing rules and obtained the individual's independent consent before processing personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, the products applying the technical solutions of the embodiments of the present disclosure have obtained individual consent before processing sensitive personal information, and at the same time meet the requirement of "express consent". For example, at a personal information collection device such as a camera, a clear and prominent sign is set up to inform that it has entered the scope of personal information collection, and personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed to agree to the collection of his personal information; or On the personal information processing device, when the personal information processing rules are informed with obvious signs/information, personal authorization is obtained through pop-up information or by asking individuals to upload their personal information; among them, the personal information processing rules may include Information such as the information processor, the purpose of personal information processing, the method of processing, and the type of personal information processed.

Having described various embodiments of the present disclosure above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims (13)

1. A cache resource allocation method, characterized in that the processor system includes at least two levels of cache, the highest level in the at least two levels of cache is a shared cache, and the shared cache includes a plurality of shared cache channels, each shared The cache channels respectively include a plurality of shared cache groups, and each shared cache group includes a plurality of ways, and the method includes: In response to a first data request from any application, obtain first identification information carried by the first data request, where the first data request is any data request sent by any application, and the first The identification information indicates the identification information carried in the first data request; In response to the first data request being a data request corresponding to the first identification information received for the first time, assigning a preset number of shared cache groups among the plurality of shared cache channels to the first identification information, Wherein, at least two shared cache channels allocate different numbers of shared cache groups to the first identification information. 2. The method according to claim 1, wherein the preset number includes a first preset number and a second preset number, and the first preset number is smaller than the second preset number; The response to the first data request being a data request corresponding to the first identification information received for the first time, respectively assigning a preset number of shared caches in the plurality of shared cache channels to the first identification information group, including: In response to the first data request being a data request corresponding to the first identification information received for the first time, determining a first reference shared cache channel corresponding to the first identification information from the plurality of shared cache channels, Wherein, the first reference shared cache channel indicates the reference shared cache channel corresponding to the first identification information; Allocating the first preset number of shared cache groups in the first common shared cache channel to the first identification information, and allocating the first preset number of shared cache groups in the first reference shared cache channel to the first identification information Two preset numbers of shared cache groups, wherein the first common shared cache channel represents a shared cache channel other than the first reference shared cache channel among the plurality of shared cache channels. 3. The method according to claim 2, wherein the response to the first data request is a data request corresponding to the first identification information received for the first time, from the plurality of shared cache channels , determining the first reference shared cache channel corresponding to the first identification information, including: In response to the first data request being a data request corresponding to the first identification information received for the first time, and there is a shared cache channel that is not determined as a reference shared cache channel among the multiple shared cache channels, from the Among the shared cache channels that are not determined as reference shared cache channels, determine a first reference shared cache channel corresponding to the first identification information. 4. The method according to claim 2, characterized in that the method further comprises: Acquiring a first hit rate of the first reference shared cache channel for the first identification information, and a second hit rate of the first common shared cache channel for the first identification information; According to the first hit ratio and the second hit ratio, the number of shared cache groups allocated to the first identification information is adjusted. 5. The method according to claim 4, wherein the adjusting the number of shared cache groups assigned to the first identification information according to the first hit rate and the second hit rate comprises: determining a ratio of the first hit rate to the second hit rate; In response to the ratio being greater than or equal to a first preset threshold, increasing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels; or, in response to the ratio being less than or equal to a first threshold Two preset thresholds, reducing the number of shared cache groups allocated to the first identification information among the plurality of shared cache channels; wherein, the first preset threshold is greater than the second preset threshold, and the Both the first preset threshold and the second preset threshold are greater than 1. 6. The method according to claim 1, further comprising: Obtain a first request address corresponding to the first data request; In response to determining that a cache miss occurs in the local cache according to the first request address, acquire a group mask, a group offset, and a flag bit offset corresponding to the first identification information; According to the second request address corresponding to the first data request, the group mask, the group offset and the flag bit offset, determine the new group bit and new tag information corresponding to the first data request , wherein the second request address is determined according to the first request address; Searching for target data according to the channel information and the in-row offset address in the second request address, as well as the new group bits and the new label information. 7. The method according to claim 6, further comprising: Remapping the first request address to obtain the second request address. 8. The method according to claim 6, wherein the second request address corresponding to the first data request, the group mask, the group offset and the flag bit offset , determining the new group bit and new tag information corresponding to the first data request, including: Obtain original group bits and original label information from the second request address; performing an AND operation on the original group bit and the group mask to obtain the relative position of the target data requested by the first data request in the plurality of shared cache groups corresponding to the first identification information; determining a new group bit corresponding to the first data request according to the group offset and the relative position; Determine new tag information corresponding to the first data request according to the original tag information, the flag bit offset, and a specified bit in the original group bits. 9. The method according to claim 6, characterized in that, according to the channel information in the second request address and the in-line offset address, as well as the new group bit and the new label information, the target data is searched ,include: Responding to the fact that the target data cannot be found according to the channel information, the new group bit, the new label information, and the in-line offset address, the target data is acquired from internal memory or external storage, and the target data is writing into the shared cache group corresponding to the new group bit, and returning the target data to the first data request. 10. The method according to any one of claims 1 to 9, wherein the first identification information includes any of the following: The identification information determined according to the module called by the application, the identification information determined according to the context identification information, and the identification information determined according to the address range of the target data requested by the first data request in the memory. 11. A cache resource allocation device, characterized in that the processor system includes at least two levels of cache, the highest level of the at least two levels of cache is a shared cache, and the shared cache includes a plurality of shared cache channels, each shared The cache channels respectively include a plurality of shared cache groups, and each shared cache group includes a plurality of ways, and the device includes: The first acquiring module is configured to acquire the first identification information carried by the first data request in response to the first data request from any application, where the first data request is any For a data request, the first identification information represents the identification information carried in the first data request; An allocation module, configured to allocate a preset number of shared cache groups to the first identification information in response to the first data request being a data request corresponding to the first identification information received for the first time, wherein at least two The shared cache channels allocate different numbers of shared cache groups to the first identification information. 12. An electronic device, characterized in that it comprises: one or more processors; memory for storing executable instructions; Wherein, the one or more processors are configured to invoke executable instructions stored in the memory to perform the method according to any one of claims 1-10. 13. A computer-readable storage medium, on which computer program instructions are stored, wherein the method according to any one of claims 1 to 10 is implemented when the computer program instructions are executed by a processor.

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