CN116009968A - Computer system, memory device and control method based on wafer stacking architecture - Google Patents

Abstract

The present application proposes a computer system based on a wafer stacking architecture, which includes memory devices and logic circuit layers combined into a wafer stack. The memory device includes a memory array and a line driver. The memory array includes a shared line and a plurality of memory units, and the shared line connects the memory units. The line driver is connected to the shared line to drive the memory unit. The logic circuit layer includes a plurality of connection pads for transmitting signals, and a delay controller, through which the connection pads are connected to the memory array to adjust the number of memory units connected to the shared line to dynamically change the Latency characteristics of memory arrays. The application also proposes the memory device and memory control method.

Description

Computer system based on wafer stacking architecture, memory device and control method

technical field

The present application relates to a memory device, in particular to a memory architecture capable of changing delay characteristics according to application requirements, and a computer system implemented by applying the memory architecture and wafer stacking technology.

Background technique

In this era, the application of artificial intelligence and blockchain has become a new business opportunity. Blockchain can be widely used in smart contracts, digital identities, sharing economy and other applications.

However, some blockchain platforms often change the algorithm of the blockchain for various security considerations or bug fixes. In addition to increasing the difficulty of computing, special designs are often deliberately made to reduce the computing efficiency of application-specific chips (ASICs), such as increasing the requirements of memory throughput or the capacity of storage devices.

Therefore, for developers of blockchain servers, it is also necessary to change the hardware architecture to adapt to changes in blockchain algorithms. However, the algorithms proposed by these crowdfunding platforms may be constantly updated. Therefore, how to make the hardware of the same block chain server elastically change parameters to adapt to new algorithms remains to be developed.

Contents of the invention

This application proposes a computer system that can flexibly adapt to changing requirements of blockchain algorithms. In an embodiment of a computer system, a wafer on wafer technology is adopted, so that the wafer on which the memory device is located and the wafer on which the core logic circuit is located are stacked into a three-dimensional structure. This method can make no extra area between the two wafers, and directly use thousands of connection pads as signal transmission paths. Since the number of transmission lines is no longer limited by the plane design, a large number of dedicated wiring can be used to solve the performance problem of data transmission.

The memory device of the present application is configured on a layer of wafer dedicated to memory, which may include multiple memory arrays (BANKs). Each memory array is mainly composed of a common circuit and a plurality of memory units. The common lines in this embodiment may be referred to as data lines or address lines, and each common line is correspondingly connected to one row or one column of the memory units. A memory cell refers to a basic unit for storing bit information, which is usually turned on under the control of an address signal, and read or written into data under the control of a data signal.

The memory device also includes a line driver connected to the shared line for driving the memory unit. The line driver may be a synonym for a data driver or an address decoder.

As mentioned above, the computer system includes a logic circuit layer, which is combined with the memory crystal layer to form a wafer stack (Wafer on Wafer). It contains several connection pads for passing signals.

In the present application, a delay controller is configured in the logic circuit layer of the computer system, and the memory array is connected through the connection pad. Its design purpose is to flexibly adjust the number of memory units connected to the shared line, so as to dynamically change the delay characteristics of the memory array.

In a further embodiment, multiple multiplexers are configured in each memory array. Each multiplexer is separated by a specific number of rows or columns. These multiplexers define a memory array as a plurality of memory regions, and each memory region contains a specific number of rows or columns of memory cells. In other words, a multiplexer is configured where two memory areas are adjacent, and is connected to the line driver with a dedicated line.

When the delay controller transmits a control signal through a connection pad to activate a multiplexer, the common line is disconnected into a first line segment and a second line segment, and the second line segment is connected to the dedicated line.

Since the shared line originally connects a plurality of memory units in series, after being disconnected into two line segments, two sub-arrays are logically formed. In other words, the memory area corresponding to the first line segment forms a first sub-array, and the memory area corresponding to the second line segment forms a second sub-array. In order to facilitate implementation and management, the disconnection mode in this embodiment may be bisected. Therefore, a memory array can be equally divided into two sub-arrays of equal size, and the two sub-arrays can be further divided into four by more multiplexers, and so on.

In a specific implementation manner, the way of changing the dimension of the memory array, that is, the way of forming the sub-arrays, may be to break the common data line into two shorter data lines. The line driver includes a data driver. The common line here represents one or more common data lines, and each common data line is connected to the data driver and a corresponding row of memory units in the memory units, and is used for transmitting data signals of the memory units. After the multiplexer is activated, the second sub-array no longer shares the common data line of the first sub-array because the common data line is disconnected. Instead, the multiplexer additionally provides dedicated lines to transmit data signals to the memory units in the second sub-array. This approach can reduce the number of memory cells on the shared line, thereby reducing the capacitive load and speeding up the response speed of the data driver.

As for the second sub-array, because the data line is connected to the data driver by a dedicated line, it can independently receive different data signal sources, and also enjoy the effect of low load and high speed. Furthermore, the address lines of the second sub-array can be changed to share the address lines of the first sub-array. In this way, the dimension of the original memory array is changed, the number of data lines (array width) is doubled, and the number of address lines (array height) is halved. The memory device originally includes a plurality of common address lines, and each common address line is connected to the address decoder and a corresponding row of the memory units for transmitting address signals of the memory units. The line driver includes an address decoder connected to each row of memory units in the memory array through the common address line. In practice, after the multiplexer is activated, the address decoder enables the memory cells in the second sub-array to share the common address line of the first sub-array according to the control signal, or The first sub-array and the second sub-array are synchronously driven using the same address signal. In other words, make the common address lines of the second sub-array and the corresponding number of rows in the first sub-array receive the same address signal.

In another specific implementation manner, the way of changing the dimension of the memory array, that is, the way of forming the sub-array, may also be to break the common address line into two shorter address lines. In this case, the above-mentioned common lines represent one or more common address lines for transmitting address signals of the memory units. After the multiplexer is activated, the memory units in the second sub-array transmit address signals using the dedicated lines. At the same time, the address decoder makes the memory cells in the second sub-array share the common data line of the first sub-array according to the control signal, or uses the same data signal to drive the first sub-array and the second subarray. Since the memory cells in the second sub-array use address lines different from those in the first sub-array, the memory array dimension is equivalent to halving the number of data bits (array width) and doubling the number of address lines (array height).

In a further embodiment, the logic circuit layer further includes a memory controller coupled to the memory array through the connection pad. A kernel connects the memory controller and the delay controller for executing an application program. The kernel can set the multiplexer in the memory array through the delay controller according to an application condition required by the application program, so that the memory array can be divided into two Multiply subarrays, reorganized into new array dimensions that meet the application criteria. When executing the program, the kernel can use the reorganized memory array through the memory controller.

In a further embodiment, the application condition includes a response time required by the application. In the embodiment of disconnecting the data line, the more the number of multiplexers activated by the delay controller, the shorter the response time of the new memory array formed,

The present application further proposes a memory control method, which is applied to the aforementioned computer system and memory device. When an application program is executed by a core, the core sets the multiplexer in the memory array through the delay controller according to an application condition required by the application program, so that the memory array Divide into two or more sub-arrays meeting the conditions of the application program, and use the memory sub-arrays through the memory controller when executing the application program.

To sum up, based on the wafer stacking technology, this application proposes a memory architecture that can flexibly adjust the array dimension, so that blockchain server products have the ability to adapt to the needs of future algorithms.

Description of drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application. In the attached picture:

FIG. 1 is an embodiment of the computer system of the present application.

FIG. 2 is an embodiment of a memory device of the present application.

3 to 5 are embodiments of memory arrays and multiplexers of the present application.

FIG. 6 is a further embodiment of the memory device 112 of the present application.

7 to 8 are embodiments of various memory arrays of the present application.

FIG. 9 is an embodiment of a memory layer 600 in a computer system 700 of the present application.

Figure 10 is a further embodiment of the computer system of the present application.

Figure 11 is a further embodiment of the memory array and multiplexer of the present application.

FIG. 12 is another embodiment of the memory array and multiplexer of the present application.

FIG. 13 is a flow chart of the memory control method of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

FIG. 1 is an embodiment of a 3D wafer product 100 of the present application. The three-dimensional wafer product 100 is composed of at least one memory crystal layer 110 , one logic circuit layer 120 , and one substrate 130 stacked layer by layer. In addition to providing basic support, the base 130 also provides additional wiring space. A plurality of connection pads 102 or 104 are disposed between each layer to provide signal channels. The 3D wafer product 100 of this embodiment is a semi-finished product of the computer system 700 , which can produce multiple independently operating computer systems 700 after cutting. As shown in FIG. 1 , each computer system 700 may include several memory devices 112 and several logic circuits 122 and have the same three-dimensional wafer structure. In other words, the memory device 112 and the logic circuit 122 included in each computer system 700 are respectively laid out in the memory crystal layer 110 and the logic circuit layer 120 in advance, and then formed into a three-dimensional structure in the form of wafer stacking . In the three-dimensional structure, the circuit wires between the chipsets do not need to occupy an extra area, and thousands of connection pads 102 and 104 can be directly used as signal transmission paths, so that the performance problem of data transmission can be effectively solved. This implements the computer system 700 of the present application.

FIG. 2 is an embodiment of a memory device of the present application. The memory device 112 of the present application is arranged on the memory crystal layer 110 dedicated to memory. It can be manufactured in a modular form, and each memory device 112 can include multiple memory arrays 200 , or called memory matrix (BANK). The operation of each memory matrix can be controlled by an array selection signal #SL. Each memory array 200 is mainly composed of a plurality of memory units 202 . The memory units 202 are arranged in multiple rows and columns, each row shares one address line, and receives address signals numbered R0 to Rn. Each column shares one data line, and transmits data signals numbered B0 to Bn. In other words, each common line is correspondingly connected to one row or one column of the memory units 202 . The memory unit 202 refers to a basic unit for storing bit information, and is usually turned on under the control of an address signal, and read or written into data under the control of a data signal. The address line is connected to an address decoder 210 for transmitting an address signal 214 generated by the address decoder to enable one or more rows of memory cells 202 selected to be turned on. The data line is connected to a data driver 220 for transmitting data written or read by the memory unit 202 . The architecture disclosed in FIG. 2 is only an example. In actual production, the number of memory array 200, address decoder 210, and data driver 220 is not limited to one, and the link relationship between them is not limited to one-to-one, or multiple To many. To sum up, the address decoder 210 and the data driver 220 in the memory device are a kind of line driver. The connected data lines and address lines are shared lines, which drive multiple memory units 202 in a mesh-like interleaving manner.

3 to 5 are embodiments of the memory array 200 and the multiplexer 302 of the present application. In order to achieve the effect of dynamically adjusting delay characteristics, multiple multiplexers 302 are configured in each memory array 200 in this embodiment. Each multiplexer 302 is separated by a specific number of rows or columns. These multiplexers 302 can define a memory array 200 as a plurality of memory regions 310 , and each memory region 310 includes a specific number of rows or columns of memory cells 202 . Taking FIG. 3 as an example, a multiplexer 302 is disposed adjacent to each two memory areas 310 .

FIG. 4 shows the operation of the multiplexer 302 when it starts up. The multiplexer 302 is connected to the data driver 220 through a dedicated line 224 . When a control signal #S is transmitted to the multiplexer from the logic circuit layer 120 shown in FIG. disconnected so that the upper and lower memory areas 310 no longer share the same data line 222 . The data line 222 is divided into a first line segment in the upper half memory area 310 and a second line segment in the lower half memory area 310 . In this embodiment, the memory area 310 in the upper half can continue to receive the original data signals B0 to B7, but because the number of shared memory cells on the first line segment is reduced, the capacitive load is significantly reduced, so the memory area 310 The delay time can be effectively shortened, that is, the speed of reaction is accelerated. The multiplexer 302 reconnects the second line segment of the lower memory area 310 to the dedicated line 224 , so that the lower memory area 310 continues to be controlled by the data driver 220 . For example, the multiplexer 302 continues to receive data signals numbered B0 to B7 from the data driver 220 through the dedicated line 224 . Since the shared memory units 202 on the second line segment are less than before, the effect of reducing delay is also achieved.

FIG. 5 shows another specific implementation manner when the multiplexer 302 starts. In this embodiment, in addition to changing the delay characteristic of the memory array 200 , the dimensions of the memory array 200 can also be changed. The formation method of the sub-array is also to divide the common data line 222 into two shorter parts, the upper part and the lower part. In other words, since the data line 222 originally connects a plurality of memory units 202 in series, two sub-arrays are logically formed after being disconnected into two line segments. The memory area 310 corresponding to the first line segment forms a first sub-array, and the memory area 310 corresponding to the second line segment forms a second sub-array. After the multiplexer 302 is activated, the second sub-array no longer shares the common data line 222 of the first sub-array because the common data line 222 is disconnected. Instead, the multiplexer 302 additionally provides a dedicated line 224 to transmit data signals to the memory units 202 in the second sub-array. In this embodiment, through the improvement of the data driver 220, the data signals transmitted through the dedicated line 224 are no longer numbered B0 to B7, but newly added B8 to B15. Furthermore, in this embodiment, through the improvement of the address decoder, the second sub-array can share the address lines of the first sub-array, or receive the same address signals R0 to R3 as the first sub-array.

That is to say, the address decoder 230 can make the memory cells in the second sub-array share the common address line of the first sub-array according to the control signal #S, or use the same address signal to synchronize The first sub-array and the second sub-array are driven. In this way, it is equivalent to changing the original 200 dimensions of the memory array. The number of data lines (array width) is doubled from the original 8 to 16, and the number of address lines (array height) is halved from the original 8 to 4. Although this embodiment uses 8x8 as an example to illustrate the division and reorganization method of the memory array 200, it can be understood that in actual manufacturing, the dimension of each memory array 200 may be a large array with a capacity of 100 megabits.

FIG. 6 is a further embodiment of the memory device 112 of the present application. A memory array 200 can be configured with n multiplexers 402 #1 to 402 #n to divide the memory array 200 into n memory areas 410 #1 to 410 #n. When the multiplexer is not activated, the memory array 200 maintains the conventional operation mode. In addition to transmitting data signals through the traditional shared data lines 222, the data driver 220 also provides a plurality of dedicated lines 224 connected to the multiplexers 402 #1 to 402 #n. The memory device 112 further includes an address decoder 230 for transmitting address signal #A to each memory area 410 #1 to 410 #n through an address line 232 . Although the data line 222 and the address line 232 are shown as a single line, it can be understood that they may include multiple lines in practice, respectively connected to each row or column in the memory array. Similar to the conventional design, each memory cell in the memory array 200 is commonly connected to a reference voltage, or ground #Gnd.

In practice, each multiplexer may receive a control signal #S to determine whether to start. For example, the control signal #S can be a square value, that is, 2, 4, 8, or 16, etc., to instruct the multiplexers 402 #1 to 402 #n to use the memory array 200 Divide into a corresponding number of sub-arrays. When the control signal #S is 2, it means that a multiplexer is needed to divide the memory array 200 into two sub-arrays. At this time, the multiplexer numbered n/2 in the memory array 200 can be activated in response to the control signal to achieve this purpose. Similarly, when the value of the control signal #S is 4, it means that three multiplexers are needed to equally divide the memory array 200 into four sub-arrays. At this time, the multiplexers numbered n/4, 2n/4, 3n/4 located in the memory array 200 can be activated in response to the control signal #S to achieve the effect of dividing into four blocks. In this design method, the value of n can be preset as a power of two, so as to facilitate the realization of the above division method.

In another implementation manner, the control signal #S may also be used to determine that every few memory areas need to be cut. For example, when the value of the control signal #S is 1, it means that each memory area needs to be separated, that is, all the multiplexers 402#1 to 402#n are activated, so that the memory array 200 becomes a n subarrays, each subarray contains a memory region. When the value of the control signal #S is 2, it indicates that the memory array 200 needs to be divided into groups of two memory areas. Therefore, multiplexers numbered 2, 4, 6, 8, etc. that are divisible by 2 will be activated in response to the control signal, so that the memory array becomes n/2 sub-arrays, and each sub-array includes 2 memory areas.

In a further implementation manner, the partitioning manner of the memory array 200 can be more flexible. For example, each multiplexer receives different control signals to determine whether to start. The actually possible division possibilities are therefore not limited to the above-described exemplary embodiments.

In the embodiment of FIG. 6, the data driver 220 and the address decoder 230 can also be further improved, and the data signal provided to each memory area can be changed according to the division of the control signal #S, or the data signal provided to each memory area can be changed. The address signal of the memory area. This approach, as described in the embodiment of FIG. 5 , enables the memory array 200 to dynamically change the length and width dimensions logically.

7 to 8 are embodiments of various memory arrays of the present application. FIG. 7 shows a memory array 500a generated after the memory array 200 in FIG. 6 is divided and reorganized by a multiplexer. Originally, each of the memory areas 410 # 1 to 410 #n has W columns of memory cells (width) and H rows of address lines (height). After dimension reorganization, a memory array 500a including a plurality of sub-arrays 502a is formed. All the sub-arrays 502a share the H row address lines, and the bit width is extended to nW columns. This means that the multiplexer needs to provide dedicated lines for nW columns of memory cells to connect to the data drivers, that is, nW lines. With the support of wafer stacking technology, the technical difficulty of implementation can be easily overcome. In the embodiment of FIG. 7, the original memory array dimension may be nH*W, which is reorganized as H*nW here. Therefore, when the data lines of each row of memory cells are driven, the capacitive load to be overcome becomes n times smaller, so that the response speed of the memory cells becomes faster.

FIG. 8 shows the situation of the memory array 500b generated after the memory array 200 in FIG. 6 is divided and reorganized by a multiplexer. Originally, each of the memory areas 410 # 1 to 410 #n has W columns of memory cells (width) and H rows of address lines (height). Here, the dimensions are reorganized by starting a multiplexer every two memory blocks, forming a memory array 500b including a plurality of sub-arrays 502b. Each sub-array 502b includes two memory areas, 2H rows high and W columns wide. The sub-arrays 502a in the memory array 500b share 2H row address lines. More precisely, through the improvement of the address decoder 230, all the memory sub-arrays 502b can share the same address line, or the address decoder 230 can transmit the same address signal flexibly according to the division of the memory array 500b. to these memory subarrays. The bit width of the memory array 500b is extended to nW/2 columns. This means that the multiplexer needs to provide a corresponding number of dedicated lines for nW/2 columns of memory cells to connect to the data driver. In the embodiment of FIG. 8 compared with that of FIG. 7 , since the height of the sub-array 502b (the number of address rows) is larger, the delay time is not as good as that of the architecture of FIG. 7 , but the required number of dedicated lines is less. This shows that the architecture of this embodiment can be flexibly adjusted according to different demands.

FIG. 9 shows a further embodiment of a memory layer 600 in a computer system 700 . Based on the concepts introduced in the foregoing embodiments, the memory layer 600 may be one of the areas of the computer system cut out from the memory crystal layer 110 in FIG. 1 , including a plurality of memory devices 510a to 510d. Each of the memory devices 510a to 510d can apply a variety of different control signals to configure different delay characteristics. For example, a computer system 700 can pre-set the configuration of each memory device 510a to 510d in firmware, configure the memory devices 510a to 510d respectively through control signals #S1 to #S4 after booting, and then Boot up and load the operating system. In a further situation, the computer system 700 of the present application can also be designed to allow dynamic and seamless change of memory latency characteristics during operation. For example, when an application program is loaded, it is judged that the application program requires memory delay, and a control signal is dynamically issued to change the dimensions of the memory devices to change the delay characteristics.

FIG. 10 is a further embodiment of a computer system 700 of the present application. The three-dimensional wafer product 100 shown in FIG. 1 , after completing the wafer stacking process, further undergoes the wafer cutting process to form a plurality of computer systems 700 . Shown in the memory layer 600 are the memory devices 510 a to 510 c configured according to the embodiment of FIG. 9 . A system layer 620 is stacked with the memory layer 600 . The system layer 620 is cut from the logic circuit layer 120 in FIG. 1 , and includes logic circuits necessary for various computer architectures, such as the core 616 and memory controllers 614a to 614c. Each memory controller 614a-614c is connected to the memory devices 510a-510c in the memory layer 600 through an interface module 612a-612c. The interface module is an interface specially designed to ensure data transmission, commonly known as the physical layer interface (PHY). Similar to FIG. 1 , the stacks of the memory layer 600 and the system layer 620 transmit signals through a plurality of connection pads (not shown). The system layer 620 is also fixed on the substrate 130 through a plurality of connection pads 104 . In addition to providing basic support, the base 130 can also provide additional wiring space. The memory controllers 614a to 614c can provide the address signal #A to the memory devices 510a to 510c through the interface modules 612a to 612c and the connection pads to access the data signal #D. The architecture of this computer system 700 is merely an example. The configuration quantity of memory controllers, interface modules, and memory devices is not limited to three groups. The core 616 may be a multi-core architecture.

In the computer system 700 of FIG. 10, a delay controller 602 is configured, connected to the memory layer 600 through one or more pads, and transmits the control signal #S to the memory devices 510a to 510c. These memory devices 510a and 510c, as described in the foregoing embodiments, can flexibly adjust the number of memory units connected to the common line in each memory array according to the control signal #S, so as to dynamically change the delay characteristics of the memory array. The delay controller 602 may be controlled by a core 616 . When the kernel 616 is executing an application program, it can determine the delay requirement of the application program in real time, and instruct the delay controller 602 to adjust the memory devices 510a to 510c. For example, the memory array re-dimension machine can divide each memory array into sub-arrays that are the power of two, and then reorganize into a new array dimension that meets the conditions of the application program. When executing the program, the kernel 616 can adaptively use the memory devices 510a to 510c that meet the requirements of the application program through the memory controllers 614a to 614c.

Figure 11 is a further embodiment of the memory array and multiplexer of the present application. Here, the memory units 202a and 202b are used to illustrate how the multiplexer 402 reduces the capacitive load on the data lines. The basic logic in a memory cell is to control a capacitor with a switch to charge or discharge the capacitor to represent one bit of data. The address lines transmitting the address signals R0 and R1 are connected in series with the gates of the memory units 202a and 202b. The data line for transmitting the data signal B0 is connected in series with the switch ends of the memory units 202a and 202b. When the multiplexer 402 is not activated, the first line segment 222a and the second line segment of the data line are connected to form the same line segment, so that the memory units 202a and 202b share the same data line to receive the data signal B0 and operate normally. When the multiplexer 402 is turned on by the instruction of the control signal #S, the switch in the multiplexer 402 disconnects the second line segment 222b from the first line segment 222a, and reconnects the second line segment 222b to a dedicated Line 224. The dedicated line is connected to the data driver 220 so that the memory unit 202b can still receive data signals. Under this structure, since the first line segment 222 a and the second line segment 222 b respectively drive half the number of memory cells, the delay effect caused by the load capacitance can be reduced, so the response speed of the memory can be improved. Although this embodiment is only illustrated with one column and two rows of memory cells, it can be understood that the number of multiplexers 402 can actually be multiple, inserted in the middle of multiple rows in a memory array, and simultaneously control the sharing of multiple data lines. with disconnect. The data signal transmitted on the dedicated line 224 is not limited to be the same as the data signal on the first line segment 222a. The data driver 220 can also be modified so that the memory units 202a and 202b receive different data signals after they are disconnected. Correspondingly, the address decoder can also be improved, so that the address lines originally transmitting the address signals R0 and R1 respectively share the same address signal, such as R0, after the multiplexer 402 is activated, so that the memory units 202a and 202b are turned on simultaneously. In this case, memory cells 202a and 202b can logically be considered as different bits on the same row. That is, the width and height dimensions of the memory array have changed from the original 1*2 to 2*1. This architecture has a significant effect on elastic adaptation to different latency requirements. The actual circuit structure of the above memory units 202a and 202b has a mature prior art, so this embodiment is only for illustration and does not limit the detailed implementation manner.

Fig. 12 shows an embodiment in which a multiplexer is set on the address line. The foregoing embodiments mainly describe how to shorten the common data line. However, embodiments of the present application can also start from address lines. The way to change the dimension of the memory array, that is, the way to form the first sub-array 810 and the second sub-array 820, can also be to break the common address line into two shorter address lines. In this case, a plurality of common address lines transmit address signals R0 to R7 of the memory cells 202 . After the multiplexer 802 receives the control signal #S and starts up, the plurality of disconnected address lines in the second sub-array 820 are switched to dedicated lines and connected to the address decoder. Further, the data driver 220 and the address decoder 230 can also be improved, according to the control signal #S, the second sub-array 820 can share the common data line of the first sub-array 810, or use the same Data signals drive the first sub-array 810 and the second sub-array 820 . At the same time, the second sub-array 820 uses a different address signal source from the first sub-array, such as R8 to R15 (not shown). In this way, logically, a new memory array is generated, the dimension is half of the original data number (array width), and the number of address lines (array height) is doubled. The approach in Fig. 11, because the address lines are shortened, the driving load of the address lines can be reduced, which also has the effect of changing the delay characteristics of the memory array.

FIG. 13 is a flow chart of the memory control method of the present application. The present application further proposes a memory control method, which is applied to the aforementioned computer system and memory device. In step 901, when an application is executed by a kernel, the kernel instructs the delay controller to send a control signal according to an application condition required by the application. In step 903, the multiplexer in the memory array causes the memory array to change dimensions according to the control signal. For example, the memory array is divided into two or more sub-arrays meeting the conditions of the application program. In step 905, the kernel uses the memory sub-array through the memory controller when executing the application.

To sum up, based on the wafer stacking technology, this application proposes a memory architecture that can flexibly adjust the array dimension, so that blockchain server products have the ability to adapt to the needs of future algorithms.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional same elements in the process, method, article or apparatus comprising said element.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of this application, without departing from the purpose of this application and the scope of protection of the claims, many forms can also be made, all of which belong to the protection of this application.

Claims (13)

1. A computer system based on a wafer stacking architecture, comprising:

a memory crystal layer comprising a plurality of memory devices, wherein each memory device comprises:

a memory array including a common line and a plurality of memory cells, the common line connecting the memory cells; and

a line driver connected to the common line for driving the memory unit;

a logic circuit layer, coupled to the memory crystal layer as a wafer stack, comprising:

a plurality of connection pads for transmitting signals; and

and the delay controller is connected with the memory array through the connecting pad and is used for adjusting the number of the memory units connected on the common line so as to dynamically change the delay characteristic of the memory array.

2. The wafer stack-based architecture of claim 1 wherein the memory array comprises:

a plurality of memory areas, each memory area comprising memory cells of a specific column number or a specific row number;

a plurality of multiplexers each disposed adjacent to each other in the memory area, each connected to the line driver by a dedicated line; wherein:

when the delay controller transmits a control signal through a connecting pad to start the multiplexer, the common line is disconnected into a first line segment and a second line segment, and the second line segment is connected to the special line;

the memory area corresponding to the first line segment forms a first subarray; and

and the memory area corresponding to the second line segment forms a second subarray.

3. The wafer stack-based computer system of claim 2, wherein:

the line driver includes a data driver;

the common line comprises a plurality of common data lines, and each common data line is connected with the data driver and a corresponding column of memory units in the memory units and is used for transmitting data signals; and

after the multiplexer is activated, the memory cells in the second sub-array transmit data signals using the dedicated lines.

4. The wafer stack-based computer system of claim 3 wherein:

the line driver includes an address decoder;

the memory device further comprises a plurality of common address lines, wherein each common address line is connected with the address decoder and a corresponding row of memory units in the memory units and is used for transmitting address signals; and

after the multiplexer is started, the address decoder enables the second subarray and the shared address line of the corresponding line number in the first subarray to receive the same address signal according to the control signal.

5. The wafer stack-based computer system of claim 2 wherein the logic circuit layer further comprises:

a memory controller coupled to the memory array through the connection pad; and

the kernel is connected with the memory controller and the delay controller and is used for executing an application program; wherein:

the kernel sets the multiplexer in the memory array through the delay controller according to the application program condition required by the application program, so that the memory array is divided into two or more subarrays conforming to the application program condition, and the memory array is used through the memory controller when the application program is executed.

6. The wafer stack-based computer system of claim 5 wherein:

the application conditions include a reaction time required by the application; and

the shorter the reaction time required, the greater the number of multiplexers that the delay controller activates.

7. A memory control method applied to the computer system based on the wafer stacking architecture according to claim 5, comprising:

executing an application program;

the kernel sets the multiplexer in the memory array through the delay controller according to the application condition required by the application program, so that the memory array is divided into two or more subarrays conforming to the application program condition, and the memory array is used through the memory controller when the application program is executed, wherein:

the application conditions include a reaction time required by the application.

8. A memory device configured in a memory crystal layer and combined with a logic circuit layer to form a wafer stack-based computer system, comprising:

a memory array including a common line and a plurality of memory cells, the common line connecting the memory cells; and

a line driver connected to the common line for driving the memory unit; wherein:

the memory crystal layer receives a control signal transmitted by the logic circuit layer, and adjusts the number of memory units connected on the common line so as to dynamically change the delay characteristic of the memory array.

9. The memory device of claim 8, wherein the memory array comprises:

a plurality of memory areas, each memory area comprising memory cells of a specific column number or a specific row number;

a plurality of multiplexers each disposed adjacent to each other in the memory area, each connected to the line driver by a dedicated line; wherein:

when the multiplexer is started by the control signal, the common line is disconnected into a first line segment and a second line segment, and the second line segment is connected to the special line;

the memory area corresponding to the first line segment forms a first subarray; and

and the memory area corresponding to the second line segment forms a second subarray.

10. The memory device of claim 9, wherein:

the line driver includes a data driver;

the common line comprises a plurality of common data lines, and each common data line is connected with the data driver and a corresponding column of memory units in the memory units and is used for transmitting data signals; and

after the multiplexer is activated, the memory cells in the second sub-array transmit data signals using the dedicated lines.

11. The memory device of claim 9, wherein:

the line driver includes an address decoder;

the memory device further comprises a plurality of common address lines, wherein each common address line is connected with the address decoder and a corresponding row of memory units in the memory units and is used for transmitting address signals; and

after the multiplexer is started, the address decoder enables the second subarray and the shared address line of the corresponding line number in the first subarray to receive the same address signal according to the control signal.

12. The memory device of claim 9, wherein: when the computer system executes an application program, the control signal is generated according to an application program condition, so that the multiplexer divides the memory array into two or more subarrays which accord with the application program condition for the application program to access.

13. The memory device of claim 12, wherein: the application conditions include a reaction time required by the application.

Images