CN115987218B

CN115987218B - Oscillator circuit

Info

Publication number: CN115987218B
Application number: CN202211650940.6A
Authority: CN
Inventors: 柴军营; 杨书山
Original assignee: Suzhou Zesheng Microelectronics Co ltd
Current assignee: Suzhou Zesheng Microelectronics Co ltd
Priority date: 2022-12-21
Filing date: 2022-12-21
Publication date: 2024-06-07
Anticipated expiration: 2042-12-21
Also published as: CN115987218A

Abstract

The present application provides an oscillator circuit comprising: the device comprises a first current module, a second current module, a temperature drift counteracting module, a first comparison module and a second comparison module. The first sub-current module and the second sub-current module alternately provide a first preset current to generate a first voltage of the first sub-current module and a second voltage of the second sub-current module. The third sub-current module and the fourth sub-current module alternately provide a second preset current to generate a third voltage and a fourth voltage. The first preset current is 2 times the second preset current. And after receiving the starting signal, the temperature drift counteracting module supplies current to the first resistor and the first capacitor through the first current source to obtain a fifth voltage. The circuit is pressurized in a period of time by alternately using 2 times of current through comparison of the first voltage, the second voltage, the third voltage and the fourth voltage with the fifth voltage respectively, so that the effect that the delay exceeding time of the comparator is not delayed in the follow-up process is compensated, and a stable clock signal is output.

Description

Oscillator circuit

Technical Field

The present disclosure relates to integrated circuits, and particularly to an oscillator circuit.

Background

An oscillator circuit is one of the core circuits commonly used in analog and digital chips, and its main function is to provide a clock signal. In oscillator circuits, RC relaxation oscillators are a common structure in low power applications.

A conventional RC relaxation oscillator typically comprises a first current source connected to a resistor, a second current source connected to a capacitor, a comparator and an RS flip-flop. The voltage comparison result can be obtained by comparing the voltages at the two ends of the resistor and the capacitor through a comparator. Based on the voltage comparison result, the RS trigger controls the capacitor to perform charge and discharge operation, and changes the voltages at two ends of the capacitor, so that the comparator determines a new voltage comparison result again based on the resistor and the voltages at two ends of the capacitor, and further generates a clock signal.

However, the comparator in the conventional RC relaxation oscillator is affected by the production process, and there is a certain delay, resulting in poor stability of the output frequency of the clock signal generated by the conventional RC relaxation oscillator.

Disclosure of Invention

In order to overcome the technical problems in the prior art, an oscillator circuit capable of stabilizing the output frequency is provided.

The present application provides an oscillator circuit comprising: the temperature drift counteracting module comprises a first current module, a second current module, a temperature drift counteracting module, a first comparison module and a second comparison module; the first current module comprises a first sub-current module and a second sub-current module; the second current module comprises a third sub-current module and a fourth sub-current module; the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module provide the same current; the first comparison module is the same as the second comparison module; the temperature drift counteracting module comprises a first current source, a first resistor and a first capacitor, one end of the first current source is connected with the power-on starting module, one ends of the first resistor and the first capacitor are connected with the other end of the first current source, the other ends of the first resistor and the first capacitor are grounded, and the first end, the second end and the first end and the second end of the first comparing module are respectively connected with the other end of the first current source; the resistance value of the first resistor is kept in a constant range at different temperatures;

The first sub-current module and the second sub-current module are used for alternately providing a first preset current and generating a first voltage of the first sub-current module and a second voltage of the second sub-current module;

The third sub-current module and the fourth sub-current module are used for alternately providing a second preset current and generating a third voltage and a fourth voltage; the first preset current is 2 times of the second preset current;

The temperature drift counteracting module is used for providing current for the first resistor and the first capacitor through the first current source after receiving the starting signal to obtain a fifth voltage;

When receiving a starting signal and stopping providing current by the first sub-current module:

The second comparison module is used for comparing the third voltage with the fifth voltage, controlling the second sub-current module to provide a second preset current after the third voltage is larger than the fifth voltage and the target delay time is elapsed, and controlling the third sub-current module to stop providing the current;

The first comparison module is used for comparing the second voltage with the fifth voltage and outputting a first clock signal; after the fifth voltage is larger than the second voltage and the target delay time passes, controlling the second sub-current module to stop providing current;

in the case where the second sub-current module stops supplying current:

The second comparison module is further used for comparing the fourth voltage with the fifth voltage, and controlling the first sub-current module to provide a second preset current and controlling the fourth sub-current module to stop providing the current after the fourth voltage is larger than the fifth voltage and the target delay time passes;

the first comparison module is also used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and after the fifth voltage is larger than the first voltage and the target delay time passes, controlling the first sub-current module to stop providing current; the first clock signal and the second clock signal are opposite.

In one embodiment, the first ends of the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are all connected with the power-on starting module; the second ends of the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are grounded;

The other end of the first current source is connected with the first end of the first comparison module; the third end of the second sub-current module is connected with the second end of the first comparison module; the third end of the third sub-current module is connected with the first end of the second comparison module; the other end of the first current source is connected with the second end of the second comparison module;

The third end of the first sub-current module is connected with the first end of the first comparison module; the other end of the first current source is connected with the second end of the first comparison module; the other end of the first current source is connected with the first end of the second comparison module; the third end of the fourth sub-current module is connected with the second end of the second comparison module.

In one embodiment, upon receipt of the start signal and the first sub-current module ceasing to provide current:

the other end of the first current source is communicated with the first end of the first comparison module;

The third end of the second sub-current module is communicated with the second end of the first comparison module;

the third end of the third sub-current module is communicated with the first end of the second comparison module;

the other end of the first current source is communicated with the second end of the second comparison module;

in the case where the second sub-current module stops supplying current:

The third end of the first sub-current module is communicated with the first end of the first comparison module;

the other end of the first current source is communicated with the second end of the first comparison module;

the other end of the first current source is communicated with the first end of the second comparison module;

The third end of the fourth sub-current module is conducted with the second end of the second comparison module.

In one embodiment, the second sub-current module includes a second current source, a third current source, and a second capacitor; the third sub-current module comprises a fourth current source and a third capacitor; the second current source, the third current source and the fourth current source provide the same current;

the second sub-current module is used for charging the second capacitor through a second current source and a third current source;

The third sub-current module is used for charging the third capacitor through the fourth current source after receiving the starting signal;

The second comparison module is used for comparing the third voltage at two ends of the third capacitor with the fifth voltage at two ends of the first capacitor, controlling the second current source to stop supplying current to the second capacitor after the third voltage is larger than the fifth voltage and the target delay time is elapsed, and controlling the fourth current source to stop charging the third capacitor;

The first comparison module is used for comparing the fifth voltage and the second voltage at two ends of the first capacitor, outputting a clock signal and controlling the third current source to stop charging the second capacitor after the fifth voltage is larger than the second voltage and the target delay time passes.

In one embodiment, the second sub-current module further comprises a first switch, a second switch, and a third switch; one end of the second current source and one end of the third current source are connected with the power-on starting module, the other end of the second current source is connected with one end of the first switch, a first common end of the other end of the third current source and the other end of the first switch is respectively connected with one end of the second switch and one end of the third switch, the other end of the second switch is connected with one end of the second capacitor, and the other end of the second capacitor and the other end of the third switch are grounded; the first common end is connected with the second end of the first comparison module, the first end of the first comparison module and the second end of the second comparison module are both connected with the other end of the first current source, and the first end of the second comparison module is connected with the third end of the third sub-current module;

the second comparison module is used for controlling the first switch to be disconnected after the third voltage is larger than the fifth voltage and the target delay time passes, so that the second current source stops providing current to the second capacitor;

The first comparison module is used for comparing the fifth voltage at two ends of the first capacitor with the second voltage, outputting a clock signal, controlling the second switch to be opened and controlling the third switch to be closed after the fifth voltage is larger than the second voltage and the target delay time passes, so that the third current source stops charging the second capacitor and discharges the second capacitor.

In one embodiment, the third sub-current module further comprises a first switch, a third switch, and a fourth switch; the third capacitor comprises a first sub-capacitor and a second sub-capacitor; one end of a fourth current source is connected with the power-on starting module, the other end of the fourth current source is connected with one end of a first switch, a second common end of a first sub capacitor and a second sub capacitor is connected with the other end of the first switch, the other end of the first sub capacitor is respectively connected with the first end of a second comparison module and one end of a third switch, the other end of the third switch is connected with the other end of the first current source, the other end of the second sub capacitor and one end of the fourth switch are grounded, and the other end of the fourth switch is connected with the second common end;

And the second comparison module is used for controlling the first switch to be opened and controlling the fourth switch and the third switch to be closed after the third voltage is larger than the fifth voltage and the target delay time is elapsed, so that the fourth current source stops charging the second sub-capacitor, and controlling the voltages at two ends of the first sub-capacitor to be equal to the fifth voltage.

In one embodiment, the first sub-current module includes a fifth current source, a sixth current source, and a fourth capacitor; the fourth sub-current module comprises a seventh current source and a fifth capacitor; the current provided by the fifth current source, the sixth current source and the seventh current source is the same as the current provided by the second current source, the third current source and the fourth current source;

in the case where the second sub-current module stops supplying current:

The first sub-current module is used for charging the fourth capacitor through the fifth current source and the sixth current source;

The fourth sub-current module is used for charging the fifth capacitor through a seventh current source;

The second comparison module is used for comparing the fourth voltage and the fifth voltage at two ends of the seventh current source, controlling the sixth current source to stop supplying current to the fourth capacitor after the fourth voltage is larger than the fifth voltage and the target delay time passes, and controlling the fourth sub-current module to stop supplying current to the fifth capacitor;

The first comparison module is used for comparing the first voltage and the fifth voltage at two ends of the fourth capacitor and outputting a second clock signal; and after the fifth voltage is larger than the first voltage and the target delay time passes, controlling the fifth current source to stop supplying current to the fourth capacitor.

In one embodiment, the first sub-current module further includes a fourth switch, a third switch and a second switch, one ends of the fifth current source and the sixth current source are connected to the power-on starting module, the other end of the sixth current source is connected to one end of the fourth switch, the other end of the fourth switch is connected to a third common end of the other end of the fifth current source and one end of the third switch, the other end of the third switch is connected to one end of the fourth capacitor and one end of the second switch respectively, and the other end of the fourth capacitor and the other end of the second switch are grounded; the third common end is connected with the first end of the first comparison module; the second end of the first comparison module and the first end of the second comparison module are connected with the other end of the first current source; the second end of the second comparison module is connected with the third end of the fourth sub-current module;

The second comparison module is used for comparing the fourth voltage at two ends of the fifth capacitor with the fifth voltage at two ends of the first capacitor, and controlling the fourth switch to be turned off after the fourth voltage is larger than the fifth voltage and the target delay time passes so as to stop the sixth current source from charging the fourth capacitor;

The first comparison module is used for comparing the first voltage and the fifth voltage at two ends of the fourth capacitor and outputting a second clock signal; and after the fifth voltage is larger than the first voltage and the target delay time is elapsed, the third switch is controlled to be opened so as to stop the fifth current source from charging the fourth capacitor, and the second switch is controlled to be closed so as to discharge the fourth capacitor.

In one embodiment, the fourth sub-current module further comprises: the fourth switch, the second switch and the first switch, and the fifth capacitor comprises a third sub-capacitor and a fourth sub-capacitor; one end of a seventh current source is connected with the power-on starting module, the other end of the seventh current source is connected with one end of a fourth switch, one end of a third sub-capacitor, one end of a fourth sub-capacitor and one end of a first switch are all connected with the other end of the fourth switch, the other end of the first switch and the other end of the third sub-capacitor are grounded, the other end of the fourth sub-capacitor is connected with one end of a second switch, the other end of the second switch is connected with the other end of the first current source, the other end of the fourth sub-capacitor is connected with the second end of a second comparison module, and the first end of the second comparison module is connected with the other end of the first current source;

in the case where the second sub-current module stops supplying current:

The second comparison module is used for comparing the fourth voltage and the fifth voltage at two ends of the fourth sub-capacitor, and after the fourth voltage is larger than the fifth voltage and the target delay time passes, the fourth switch is controlled to be opened so that the seventh current source stops charging the third sub-capacitor, and the second switch and the first switch are closed so that the voltage at two ends of the fourth sub-capacitor is equal to the fifth voltage.

In one embodiment, the first comparison module includes: two third switches, two second switches, a first comparator, a first inverter and a first RS trigger;

a second comparison module comprising: two third switches, two second switches, a second comparator, a second inverter and a second RS trigger;

the oscillator circuit further includes a switch control unit; the switch controller comprises a first switch control unit and a second switch control unit;

One end of a third switch and one end of a second switch in the first comparison module are respectively connected with the first end of a first comparator; the other end of the third switch is connected with the other end of the first current source; the other end of the second switch is connected with the first common end;

One end of the other third switch and one end of the other second switch are respectively connected with the second end of the first comparator; the other end of the other third switch is connected with the third common end, and the other end of the other second switch is connected with the other end of the first current source;

the third end of the first comparator is respectively connected with the input end of the first inverter; the third end of the first comparator and the output end of the first inverter are respectively connected with the first RS trigger, the first output end of the first RS trigger is respectively connected with each second switch and the first input end of the first switch control unit, and the second output end of the first RS trigger is respectively connected with each third switch and the first input end of the second switch control unit;

One end of a third switch and one end of a second switch in the second comparison module are respectively connected with the first end of a second comparator; the other end of the third switch is connected with the other end of the fourth sub-capacitor, and the other end of the second switch is connected with the other end of the first current source;

one end of the other third switch and one end of the other second switch are respectively connected with the second end of the second comparator; the other end of the other third switch is connected with the other end of the first current source, and the other end of the other second switch is connected with the other end of the first sub-capacitor;

The third end of the second comparator is respectively connected with the input end of the second inverter; the third end of the second comparator and the output end of the second inverter are respectively connected with a second RS trigger, the first output end of the second RS trigger is connected with the second input end of the first switch control unit, and the second output end of the second RS trigger is connected with the second input end of the second switch control unit;

The output end of the first comparator is connected with the input end of the first inverter and is used for outputting a clock signal;

the first switch control unit is used for controlling the disconnection or connection of each first switch according to the output signal of the first output end of the first RS trigger and the output signal of the second output end of the second RS trigger;

The second switch control unit is used for controlling the disconnection or connection of each second switch according to the output signal of the second output end of the first RS trigger and the output signal of the first output end of the second RS trigger;

the first RS trigger is used for transmitting an output signal of a first output end of the first RS trigger to each second switch so as to enable the second switch to be disconnected or connected; and transmitting an output signal of the second output terminal of the first RS flip-flop to each third switch to turn off or on the third switch.

In one embodiment, the first RS flip-flop and the second RS flip-flop are and gate flip-flops.

In one embodiment, the first resistor includes a first sub resistor and a second sub resistor, one end of the first sub resistor is connected to the other end of the first signal source, the other end of the first sub resistor is connected to one end of the second sub resistor, the other end of the second sub resistor is grounded, the first sub resistor is a positive temperature coefficient resistor, and the second sub resistor is a negative temperature coefficient resistor.

As can be seen from the above technical solution, the present application provides an oscillator circuit, comprising: the device comprises a first current module, a second current module, a temperature drift counteracting module, a first comparison module and a second comparison module. The first sub-current module and the second sub-current module are used for alternately providing a first preset current to generate a first voltage of the first sub-current module and a second voltage of the second sub-current module. The third sub-current module and the fourth sub-current module are used for alternately providing a second preset current and generating a third voltage and a fourth voltage. And the first preset current is 2 times of the second preset current. The temperature drift counteracting module is used for providing current for the first resistor and the first capacitor through the first current source after receiving the starting signal to obtain a fifth voltage. At this time, when the start signal is received and the first sub-current module stops providing current, the second comparison module may compare the third voltage with the fifth voltage, and after the third voltage is greater than the fifth voltage and the target delay time elapses, control the second sub-current module to provide the second preset current, and control the third sub-current module to stop providing current. In the case where the second sub-current module stops supplying current: the second comparison module is further used for comparing the fourth voltage with the fifth voltage, and controlling the first sub-current module to provide a second preset current and controlling the fourth sub-current module to stop providing the current after the fourth voltage is larger than the fifth voltage and the target delay time passes; the first comparison module is also used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and after the fifth voltage is larger than the first voltage and the target delay time passes, controlling the first sub-current module to stop providing current; the first clock signal and the second clock signal are opposite. Obviously, under different modes, the circuit can be pressurized by adopting 2 times of current, so that the time exceeding the time delay of a subsequent comparator is compensated, the effect of no time delay is further achieved, and the output clock signal is also relatively stable.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a conventional oscillator circuit;

fig. 2 is a schematic diagram of an oscillator circuit according to a first embodiment of the present application;

FIG. 3 is a schematic diagram of an oscillator circuit according to a second embodiment of the present application;

Fig. 4 is a schematic diagram of an oscillator circuit according to a third embodiment of the present application;

Fig. 5 is a schematic diagram of an oscillator circuit according to a fourth embodiment of the present application;

fig. 6 is a schematic diagram of an oscillator circuit according to a fifth embodiment of the present application;

Fig. 7 is a schematic diagram of an oscillator circuit according to a sixth embodiment of the present application;

fig. 8 is a schematic diagram of an oscillator circuit according to a seventh embodiment of the present application;

Fig. 9 is a simulation diagram of an oscillator circuit of the present application.

Reference numerals:

A 10-oscillator circuit; 100-a first current module; 110-a first sub-current module; 120-a second sub-current module;

111-a fifth current source; 112-a sixth current source; 113-fourth capacitance; 114-fourth switch; 115-a third switch; 116-a second switch;

121-a second current source; 122-a third current source; 123-a second capacitance; 124-a first switch; 200-a second current module; 210-a third sub-current module; 220-a fourth sub-current module;

211-a fourth current source; 212-a third capacitance; 2121-a first sub-capacitance; 2122-second sub-capacitance;

221-seventh current source; 222-a fifth capacitance; 2221-third sub-capacitance; 2222-fourth sub-capacitance;

300-a temperature drift counteracting module; 310-a first current source; 320-a first resistor; 330-a first capacitance;

321-a first sub-resistor; 322-second sub-resistor;

400-a first comparison module; 410-a first comparator; 420-a first inverter; 430 a first RS flip-flop;

500-a second comparison module; 510-a second comparator; 520-a second inverter; 530-a second RS flip-flop;

600-powering up the starting module; 700-a switch control unit; 710-a first switch control unit; 720-a second switch control unit.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

The numbering of the components itself, e.g. "first", "second", etc., in the present application is used only to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the present application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

OSC (oscillator) circuits are one of the core circuits commonly used in analog and digital chips to provide a basic clock source. Conventional RC relaxation oscillators are a common structure in low power applications. A conventional RC relaxation oscillator circuit, as shown in fig. 1, generally comprises a first current source I1 connected to a resistor R, a second current source I2 connected to a capacitor C, a Comparator (Comparator) and an RS flip-flop. The voltage V2 at two ends of the resistor and the voltage V1 at two ends of the capacitor can be compared by a comparator, and a voltage comparison result is obtained. Based on the voltage comparison result, the RS trigger controls the capacitor to perform charge and discharge operation, and changes the voltages at two ends of the capacitor, so that the comparator determines a new voltage comparison result again based on the resistor and the voltages at two ends of the capacitor, and further generates a clock signal.

Based on this, an embodiment of the present application provides an oscillator circuit. The first sub-current module and the second sub-current module are used for alternately providing a first preset current to generate a first voltage of the first sub-current module and a second voltage of the second sub-current module. The third sub-current module and the fourth sub-current module are used for alternately providing a second preset current and generating a third voltage and a fourth voltage. And the first preset current is 2 times of the second preset current. The temperature drift counteracting module is used for providing current for the first resistor and the first capacitor through the first current source after receiving the starting signal to obtain a fifth voltage. At this time, when the start signal is received and the first sub-current module stops providing current, the second comparison module may compare the third voltage with the fifth voltage, and after the third voltage is greater than the fifth voltage and the target delay time elapses, control the second sub-current module to provide the second preset current, and control the third sub-current module to stop providing current. In the case where the second sub-current module stops supplying current: the second comparison module is further used for comparing the fourth voltage with the fifth voltage, and controlling the first sub-current module to provide a second preset current and controlling the fourth sub-current module to stop providing the current after the fourth voltage is larger than the fifth voltage and the target delay time passes; the first comparison module is also used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and after the fifth voltage is larger than the first voltage and the target delay time passes, controlling the first sub-current module to stop providing current; the first clock signal and the second clock signal are opposite. Obviously, under different modes, the circuit can be pressurized by adopting 2 times of current, so that the time exceeding the time delay of a subsequent comparator is compensated, the effect of no time delay is further achieved, and the output clock signal is also relatively stable.

In order to achieve the above object, the technical solution provided by the embodiments of the present application is described in detail below, with reference to the accompanying drawings.

As shown in fig. 2, fig. 2 is an oscillator circuit 10 according to an embodiment of the present application, including: the temperature drift compensation device comprises a first current module 100, a second current module 200, a temperature drift compensation module 300, a first comparison module 400 and a second comparison module 500; the first current module 100 includes a first sub-current module 110 and a second sub-current module 120; the second current module 200 includes a third sub-current module 210 and a fourth sub-current module 220; the currents provided by the first sub-current module 110, the second sub-current module 120, the third sub-current module 210 and the fourth sub-current module 220 are the same; the first comparison module 400 and the second comparison module 500 are identical; the temperature drift cancellation module 300 includes a first current source 310, a first resistor 320 and a first capacitor 330, one end of the first current source 310 is connected with the power-on starting module 600, one ends of the first resistor 320 and the first capacitor 330 are connected with the other end of the first current source 310, the other ends of the first resistor 320 and the first capacitor 330 are grounded, and the first end, the second end and the first end and the second end of the first comparison module 400 and the second comparison module 500 are respectively connected with the other end of the first current source 310.

The resistance of the first resistor 320 is maintained within a constant range at different temperatures. That is, the resistance of the first resistor 320 does not change with a change in temperature.

It should be noted that, the current provided by the first current source 310 may be the same as or different from the current provided by the first sub-current module 110, the second sub-current module 120, the third sub-current module 210, and the fourth sub-current module 220. If the current provided by the first current source 310 is slightly greater than the current provided by the first sub-current module 110, the second sub-current module 120, the third sub-current module 210 and the fourth sub-current module 220, the resistance of the first resistor 320 needs to be set to be larger when the first resistor 320 is set, when the current is the same as the current.

As shown in fig. 2, the connection relationship of the oscillator circuit 10 may be that the first ends of the first sub-current module 110, the second sub-current module 120, the third sub-current module 210, and the fourth sub-current module 220 are all connected to the power-on starting module 600; the second ends of the first sub-current module 110, the second sub-current module 120, the third sub-current module 210 and the fourth sub-current module 220 are all grounded;

The other end of the first current source 310 is connected to a first end of the first comparison module 400; the third terminal of the second sub-current module 120 is connected to the second terminal of the first comparison module 400; a third terminal of the third sub-current module 210 is connected to the first terminal of the second comparison module 500; the other end of the first current source 310 is connected to the second end of the second comparison module 500;

the third terminal of the first sub-current module 110 is connected to the first terminal of the first comparison module 400; the other end of the first current source 310 is connected to the second end of the first comparison module 400; the other end of the first current source 310 is connected with the first end of the second comparison module 500; the third terminal of the fourth sub-current module 220 is connected to the second terminal of the second comparison module 500.

Specifically, the first sub-current module 110 and the second sub-current module 120 are configured to alternately provide a first preset current, and generate a first voltage of the first sub-current module 110 and a second voltage of the second sub-current module 120.

The third sub-current module 210 and the fourth sub-current module 220 are configured to alternately provide a second preset current to generate a third voltage and a fourth voltage; the first preset current is 2 times the second preset current.

The temperature drift cancellation module 300 is configured to provide a current to the first resistor 320 and the first capacitor 330 through the first current source 310 after receiving the start signal, so as to obtain a fifth voltage.

It should be noted that the first sub-current module 110 and the third sub-current module 210 cooperate, and the second sub-current module 120 and the fourth sub-current module 220 cooperate.

Upon receiving the start signal and the first sub-current module 110 stopping providing current:

the second comparing module 500 is configured to compare the third voltage with the fifth voltage, and after the third voltage is greater than the fifth voltage and the target delay time elapses, control the second sub-current module 120 to provide the second preset current, and control the third sub-current module 210 to stop providing the current.

The target delay time may be determined by a change of the third voltage or the fourth voltage provided by the third sub-current module 210 and the fourth sub-current module 220. The delay time obtained by multiple experiments after the related personnel determine the type of the comparator is also not limited herein.

A first comparison module 400 for comparing the second voltage and the fifth voltage and outputting a first clock signal; and after the fifth voltage is greater than the second voltage and the target delay time elapses, the second sub-current module 120 is controlled to stop providing current.

And when the second voltage is larger than or equal to the fifth voltage, outputting a high level, and when the second voltage is smaller than the fifth voltage, outputting a low level. When the second voltage changes, a transformed first clock signal may be generated.

In the case where the second sub-current module 120 stops supplying current:

the second comparing module 500 is further configured to compare the fourth voltage with the fifth voltage, and after the fourth voltage is greater than the fifth voltage and the target delay time elapses, control the first sub-current module 110 to provide the second preset current, and control the fourth sub-current module 220 to stop providing the current.

The first comparing module 400 is further configured to compare the first voltage and the fifth voltage and output a second clock signal; and, after the fifth voltage is greater than the first voltage and the target delay time passes, controlling the first sub-current module 110 to stop providing current; the first clock signal and the second clock signal are opposite.

When the first voltage is greater than or equal to the fifth voltage, a low level is output, and when the first voltage is less than the fifth voltage, a high level is output. When the first voltage changes, a transformed second clock signal may be generated.

In the embodiment of the present application, since the first sub-current module 110 and the second sub-current module 120 are used for alternately providing the first preset current, the first voltage of the first sub-current module 110 and the second voltage of the second sub-current module 120 are generated. The third sub-current module 210 and the fourth sub-current module 220 are configured to alternately supply a second preset current to generate a third voltage and a fourth voltage. And the first preset current is 2 times of the second preset current. The temperature drift cancellation module 300 is configured to provide a current to the first resistor 320 and the first capacitor 330 through the first current source 310 after receiving the start signal, so as to obtain a fifth voltage. At this time, when the start signal is received and the first sub-current module 110 stops providing current, the second comparing module 500 may control the second sub-current module 120 to provide the second preset current and control the third sub-current module 210 to stop providing current after the third voltage is greater than the fifth voltage and the target delay time passes by comparing the third voltage with the fifth voltage. In the case where the second sub-current module 120 stops supplying current: the second comparing module 500 is further configured to compare the fourth voltage with the fifth voltage, and after the fourth voltage is greater than the fifth voltage and the target delay time elapses, control the first sub-current module 110 to provide the second preset current, and control the fourth sub-current module 220 to stop providing the current; the first comparing module 400 is further configured to compare the first voltage and the fifth voltage and output a second clock signal; and, after the fifth voltage is greater than the first voltage and the target delay time passes, controlling the first sub-current module 110 to stop providing current; the first clock signal and the second clock signal are opposite. Obviously, under different modes, the circuit can be pressurized by adopting 2 times of current, so that the time exceeding the time delay of a subsequent comparator is compensated, the effect of no time delay is further achieved, and the output clock signal is also relatively stable.

The above embodiment has been described with respect to the oscillator circuit 10, and the operation principle when the start signal is received and the first sub-current module 110 stops supplying current will be further described with an embodiment. In one embodiment, referring to fig. 2, upon receipt of the start signal and the first sub-current module 110 ceasing to provide current:

The other end of the first current source 310 is connected to the first end of the first comparison module 400, the third end of the second sub-current module 120 is connected to the second end of the first comparison module 400, the third end of the third sub-current module 210 is connected to the first end of the second comparison module 500, and the other end of the first current source 310 is connected to the second end of the second comparison module 500.

In the case where the second sub-current module 120 stops supplying current: the third terminal of the first sub-current module 110 is connected to the first terminal of the first comparison module 400, the other terminal of the first current source 310 is connected to the second terminal of the first comparison module 400, the other terminal of the first current source 310 is connected to the first terminal of the second comparison module 500, and the third terminal of the fourth sub-current module 220 is connected to the second terminal of the second comparison module 500.

In the embodiment of the application, by controlling the connection and disconnection of different modules, the realization that in two modes, after boosting is alternately carried out by adopting 2 times of current in each clock signal, the circuit operation is realized by continuously adopting 1 time of current, the time delay time is saved by the time shortened by 2 times of speed boosting and 1 time boosting, and the clock signal can be stably output.

While the above embodiment has described the oscillator circuit 10, the second sub-current module 120 and the third sub-current module 210 in the oscillator circuit 10 will now be described with one embodiment. In one embodiment, as shown in fig. 3, the second sub-current module 120 includes a second current source 121, a third current source 122, and a second capacitor 123. The third sub-current module 210 includes a fourth current source 211 and a third capacitor 212. The second current source 121, the third current source 122 and the fourth current source 211 provide the same current.

the second sub-current module 120 is configured to charge the second capacitor 123 through the second current source 121 and the third current source 122.

Specifically, the second current source 121 and the third current source 122 simultaneously supply charges to the second capacitor 123 for charging, that is, supply the first preset current, and the voltage across the second capacitor 123 increases.

The third sub-current module 210 is configured to charge the third capacitor 212 through the fourth current source 211 after receiving the start signal.

Specifically, when the start signal is received, the fourth current source 211 charges the third capacitor 212, that is, provides the second preset current.

The second comparing module 500 is configured to compare the third voltage across the third capacitor 212 with the fifth voltage across the first capacitor 330, and after the third voltage is greater than the fifth voltage and the target delay time elapses, control the second current source 121 to stop providing the current to the second capacitor 123, and control the fourth current source 211 to stop charging the third capacitor 212.

The first comparing module 400 is configured to compare the fifth voltage and the second voltage across the first capacitor 330, output a clock signal, and control the third current source 122 to stop charging the second capacitor 123 after the fifth voltage is greater than the second voltage and the target delay time elapses.

Specifically, when the start signal is received, the second current source 121 and the third current source 122 charge the second capacitor 123 at the same time, and the fourth current source 211 charges the third capacitor 212. The second comparing module 500 compares the third voltage across the third capacitor 212 with the fifth voltage across the first capacitor 330, and after the third voltage is greater than the fifth voltage and the target delay time elapses, controls the second current source 121 to stop supplying current to the second capacitor 123, and controls the fourth current source 211 to stop charging the third capacitor 212. The first comparing module 400 compares the fifth voltage and the second voltage at both ends of the first capacitor 330, outputs a clock signal, and controls the third current source 122 to stop charging the second capacitor 123 after the fifth voltage is greater than the second voltage and the target delay time elapses.

Further, in one embodiment, as shown in fig. 4, the second sub-current module 120 further includes a first switch 124 (S1), a second switch 116 (Q1), and a third switch 115 (Q1B); one end of the second current source 121 and one end of the third current source 122 are connected with the power-on starting module 600, the other end of the second current source 121 is connected with one end of the first switch 124 (S1), the other end of the third current source 122 and a first common end of the other end of the first switch 124 (S1) are respectively connected with one end of the second switch 116 (Q1) and one end of the third switch 115 (Q1B), the other end of the second switch 116 (Q1) is connected with one end of the second capacitor 123, and the other end of the second capacitor 123 and the other end of the third switch 115 (Q1B) are grounded; the first common terminal is connected to the second terminal of the first comparing module 400, the first terminal of the first comparing module 400 and the second terminal of the second comparing module 500 are both connected to the other terminal of the first current source 310, and the first terminal of the second comparing module 500 is connected to the third terminal of the third sub-current module 210.

The second comparing module 500 is configured to control the first switch 124 to be turned off after the third voltage is greater than the fifth voltage and the target delay time elapses, so that the second current source 121 stops providing the current to the second capacitor 123.

The first comparing module 400 is configured to compare the fifth voltage across the first capacitor 330 with the second voltage, output a clock signal, and after the fifth voltage is greater than the second voltage and the target delay time elapses, control the second switch 116 to be opened and control the third switch 115 to be closed, so that the third current source 122 stops charging the second capacitor 123 and discharges the second capacitor 123.

Further, in one embodiment, referring to fig. 4, the third sub-current module 210 further includes a first switch 124 (S1), a third switch 115 (Q1B), and a fourth switch 114 (S2). Wherein the third capacitor 212 includes a first sub-capacitor 2121 and a second sub-capacitor 2122; one end of the fourth current source 211 is connected to the power-on starting module 600, the other end of the fourth current source 211 is connected to one end of the first switch 124, the second common ends of the first sub-capacitor 2121 and the second sub-capacitor 2122 are connected to the other end of the first switch 124, the other end of the first sub-capacitor 2121 is connected to the first end of the second comparing module 500 and to one end of the third switch 115, the other end of the third switch 115 is connected to the other end of the first current source 310, the other end of the second sub-capacitor 2122 and one end of the fourth switch 114 are grounded, and the other end of the fourth switch 114 is connected to the second common end.

The second comparing module 500 is configured to control the first switch 124 to be opened and control the fourth switch 114 and the third switch 115 to be closed after the third voltage is greater than the fifth voltage and the target delay time elapses, so that the fourth current source 211 stops charging the second sub-capacitor 2122 and controls the voltages at the two ends of the first sub-capacitor 2121 to be equal to the fifth voltage.

In the embodiment of the present application, the second sub-current module 120 and the third sub-current module 210 cooperate to provide a clock signal, and the delay is saved by adopting a 2-time current pressurizing mode, so that the output frequency of the whole circuit is prevented from being unstable due to the delay of the comparator in the operation process.

While the above embodiments illustrate the oscillator circuit 10, the first sub-current block 110 of the oscillator circuit 10 will now be described in one embodiment. In one embodiment, as shown in fig. 5, the first sub-current module 110 includes a fifth current source 111, a sixth current source 112, and a fourth capacitor 113, and the fourth sub-current module 220 includes a seventh current source 221 and a fifth capacitor 222.

The currents provided by the fifth current source 111, the sixth current source 112, and the seventh current source 221 are the same as the currents provided by the second current source 121, the third current source 122, and the fourth current source 211.

In the case where the second sub-current module 120 stops supplying current:

the first sub-current module 110 is configured to charge the fourth capacitor 113 through the fifth current source 111 and the sixth current source 112.

The fourth sub-current module 220 is configured to charge the fifth capacitor 222 through the seventh current source 221.

The second comparing module 500 is configured to compare the fourth voltage and the fifth voltage across the seventh current source 221, and after the fourth voltage is greater than the fifth voltage and the target delay time elapses, control the sixth current source 112 to stop providing current to the fourth capacitor 113, and control the fourth sub-current module 220 to stop providing current to the fifth capacitor 222;

The first comparing module 400 is configured to compare the first voltage and the fifth voltage at two ends of the fourth capacitor 113, and output a second clock signal; and, after the fifth voltage is greater than the first voltage and the target delay time elapses, the fifth current source 111 is controlled to stop supplying current to the fourth capacitor 113.

Further, in one embodiment, as shown in fig. 6, the first sub-current module 110 further includes a fourth switch 114 (S2), a third switch 115 (Q1B), and a second switch 116 (Q1). One end of the fifth current source 111 and one end of the sixth current source 112 are connected to the power-on starting module 600, the other end of the sixth current source 112 is connected to one end of the fourth switch 114, a third common end of the other end of the fourth switch 114 and the other end of the fifth current source 111 is connected to one end of the third switch 115, the other end of the third switch 115 is respectively connected to one end of the fourth capacitor 113 and one end of the second switch 116, and the other end of the fourth capacitor 113 and the other end of the second switch 116 are grounded; the third common terminal is connected with the first terminal of the first comparison module 400; the second end of the first comparison module 400 and the first end of the second comparison module 500 are connected to the other end of the first current source 310; the second terminal of the second comparison module 500 is connected to the third terminal of the fourth sub-current module 220.

The second comparing module 500 is configured to compare the fourth voltage across the fifth capacitor 222 with the fifth voltage across the first capacitor 330, and after the fourth voltage is greater than the fifth voltage and the target delay time elapses, control the fourth switch 114 to be turned off, so that the sixth current source 112 stops charging the fourth capacitor 113;

The first comparing module 400 is configured to compare the first voltage and the fifth voltage at two ends of the fourth capacitor 113, and output a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time passes, the third switch 115 is controlled to be opened so as to stop the fifth current source 111 from charging the fourth capacitor 113, and the second switch 116 is controlled to be closed so as to discharge the fourth capacitor 113.

Further, in one embodiment, referring to fig. 6, the fourth sub-current module 220 further includes: fourth switch 114 (S2), second switch 116 (Q1), and first switch 124 (S1). The fifth capacitor 222 includes a third sub-capacitor 2221 and a fourth sub-capacitor 2222; one end of the seventh current source 221 is connected to the power-on starting module 600, the other end of the seventh current source 221 is connected to one end of the fourth switch 114, one end of the third sub-capacitor 2221, one end of the fourth sub-capacitor 2222 and one end of the first switch 124 are all connected to the other end of the fourth switch 114, the other end of the first switch 124 and the other end of the third sub-capacitor 2221 are grounded, the other end of the fourth sub-capacitor 2222 is connected to one end of the second switch 116, the other end of the second switch 116 is connected to the other end of the first current source 310, the other end of the fourth sub-capacitor 2222 is connected to the second end of the second comparison module 500, and the first end of the second comparison module 500 is connected to the other end of the first current source 310.

In the embodiment of the present application, the resistors of the same type and size are used except for the first resistor 320, and the capacitors of the same type and size are used except for the first capacitor 330.

In the case where the second sub-current module 120 stops supplying current:

The second comparing module 500 is configured to compare the fourth voltage and the fifth voltage across the fourth sub-capacitor 2222, and after the fourth voltage is greater than the fifth voltage and the target delay time elapses, control the fourth switch 114 to be opened so that the seventh current source 221 stops charging the third sub-capacitor 2221, and close the second switch 116 and the first switch 124 so that the voltage across the fourth sub-capacitor 2222 is equal to the fifth voltage.

In the embodiment of the present application, the first sub-current module 110 and the fourth sub-current module cooperate to provide another clock signal, and the delay is saved by adopting a 2-time current pressurizing mode, so that the output frequency of the whole circuit is prevented from being unstable due to the delay of the comparator in the operation process.

The above embodiments have been described for the respective power supply modules in the oscillator circuit 10, and the first comparison module 400 and the second comparison module 500 will now be described for one embodiment. In one embodiment, as shown in fig. 7, the first comparison module 400 includes: two third switches 115 (Q1B), two second switches 116 (Q1), a first comparator 410, a first inverter 420, a first RS flip-flop 430. A second comparison module 500, comprising: two third switches 115 (Q1B), two second switches 116 (Q1), a second comparator 510, a second inverter 520, a second RS flip-flop 530.

The oscillator circuit 10 further includes a switch control unit 700, among other things. The switch controller includes a first switch (S1) control unit 710 and a second switch (S2) control unit 720.

One end of a third switch 115 and one end of a second switch 116 in the first comparison module 400 are respectively connected to a first end of a first comparator 410; the other end of the third switch 115 is connected to the other end of the first current source 310; the other end of a second switch 116 is connected to the first common terminal.

One end of the other third switch 115 and one end of the other second switch 116 are connected to the second end of the first comparator 410, respectively; the other end of the other third switch 115 is connected to a third common terminal, and the other end of the other second switch 116 is connected to the other end of the first current source 310.

The third terminal of the first comparator 410 is connected to the input terminal of the first inverter 420, respectively; the third terminal of the first comparator 410 and the output terminal of the first inverter 420 are respectively connected to the first RS flip-flop 430, the first output terminal of the first RS flip-flop 430 is respectively connected to the respective second switches 116 and the first input terminal of the first switch control unit 710, and the second output terminal of the first RS flip-flop 430 is respectively connected to the respective third switches 115 and the first input terminal of the second switch control unit 720.

One end of a third switch 115 and one end of a second switch 116 in the second comparison module 500 are respectively connected to a first end of a second comparator 510; the other end of the third switch 115 is connected to the other end of the fourth sub-capacitor 2222, and the other end of the second switch 116 is connected to the other end of the first current source 310.

One end of the other third switch 115 and one end of the other second switch 116 are connected to the second end of the second comparator 510, respectively; the other end of the third switch 115 is connected to the other end of the first current source 310, and the other end of the second switch 116 is connected to the other end of the first sub-capacitor 2121.

The third terminal of the second comparator 510 is connected to the input terminal of the second inverter 520, respectively; the third terminal of the second comparator 510 and the output terminal of the second inverter 520 are respectively connected to the second RS flip-flop 530, the first output terminal of the second RS flip-flop 530 is connected to the second input terminal of the first switch control unit 710, and the second output terminal of the second RS flip-flop 530 is connected to the second input terminal of the second switch control unit 720.

Specifically, an output terminal (third terminal) of the first comparator 410 is connected to a book input terminal of the first inverter 420 for outputting a clock signal.

The first switch control unit 710 is configured to control the opening or closing of each first switch 124 according to the output signal of the first output terminal of the first RS flip-flop 430 and the output signal of the second output terminal of the second RS flip-flop 530.

Specifically, when the two RS flip-flop output signals are at the high level at the same time, the first switch 124 is controlled to be turned on, and otherwise, the first switch 124 is controlled to be turned off.

The second switch control unit 720 is configured to control the opening or closing of each fourth switch 114 according to the output signal of the second output terminal of the first RS flip-flop 430 and the output signal of the first output terminal of the second RS flip-flop 530.

Specifically, when the two RS flip-flop output signals are at the high level at the same time, the second switch 116 is controlled to be turned on, and otherwise, the second switch 116 is controlled to be turned off.

The first RS flip-flop 430 is configured to transmit an output signal of the first output terminal of the first RS flip-flop 430 to each of the second switches 116, so that the second switches 116 are turned off or turned on; and transmits an output signal of the second output terminal of the first RS flip-flop 430 to each of the third switches 115 to turn off or on the third switches 115.

Optionally, the first RS flip-flop 430 and the second RS flip-flop 530 are and gate flip-flops.

In the embodiment of the present application, the first comparing module 400 and the second comparing module 500 are described, and the on and off of each switch in the oscillator circuit 10 are controlled by the mutual cooperation of each device, so that each portion performs its own function.

In one embodiment, as shown in fig. 8, the first resistor 320 includes a first sub-resistor 321 and a second sub-resistor 322, one end of the first sub-resistor 321 is connected to the other end of the first signal source, the other end of the first sub-resistor 321 is connected to one end of the second sub-resistor 322, the other end of the second sub-resistor 322 is grounded, the first sub-resistor 321 is a positive temperature coefficient resistor, and the second sub-resistor 322 is a negative temperature coefficient resistor.

The positive and negative temperature coefficients of the first sub-resistor 321 and the second word resistor can be offset, so as to obtain a first resistor 320 which does not change with temperature. And a fifth voltage insensitive to temperature can be obtained. The oscillator circuit 10 can be kept free from temperature influence, which causes temperature drift and thus affects the output frequency of the oscillator circuit 10.

1-9, Where FIG. 9 is a simulation diagram of an oscillator circuit 10 during operation. Wherein V1 is a first voltage across the fourth capacitor, V2 is a second voltage across the second capacitor, V31 is a third voltage across the first sub-capacitor, V4 is a fifth voltage across the first capacitor, V41 is a fourth voltage across the fifth capacitor, S1 is the first switch 124, S2 is the fourth switch 114, Q1 is the second switch 116, Q1B is the third switch 115, phase1 is the output clock signal, phase2 is the Phase1 inversion signal, phase_1 is the first signal output by the second comparator, and phase_2 is the second signal after inverting the first signal.

Referring to the waveforms in the region a in fig. 9, when the start signal is received, S1 is closed (high level), and the first sub-current module 110 is not operated due to S2 being opened. The second current source 121 and the third current source 122 in the second sub-current module 120 charge the second capacitor 123 (V2 shown in fig. 9 rises with a slope twice V31), and the third sub-current module 210 charges the third capacitor 212 through the fourth current source 211 after receiving the start signal.

At this time, V31 starts rising from 0, and after rising to be stable, the second comparing module 500 is configured to compare the third voltage across the third capacitor 212 with the fifth voltage across the first capacitor 330, that is, V31 is compared with V4, and after the third voltage is greater than the fifth voltage and the target delay time elapses (after V31 is greater than V4 and the target delay time elapses), control the second current source 121 to stop providing current to the second capacitor 123, and control the fourth current source 211 to stop charging the third capacitor 212. At this time, the second current source 121 stops supplying power. At this time, V2 applies only the second preset current to pressurize V2, and the slope of V2 becomes gentle. At this time, phase_1 is high and phase_2 is low, and further, the output Q2 of the second RS flip-flop 530 is high and Q2B is low. Further, the first switch control unit 710 controls S1 to be turned off.

At this time, the first comparing module 400 is configured to compare the fifth voltage across the first capacitor 330 with the second voltage, and control the third current source 122 to stop charging the second capacitor 123 after the fifth voltage is greater than the second voltage and the target delay time elapses. In the above process, the clock signal (Phase 1 is high), phase2 is low after passing through the first inverter 420, and Q1 is high and Q1B is low after Phase1 and Phase2 are input to the first RS flip-flop 430.

At this time, when both the second sub-current module 120 and the third sub-current module 210 are turned off by the control of the switches S1 and Q1, the output clock signal (Phase 1 is low) is Q1 is low, and Q1B is high, and at this time, the second switch control unit 720 may control S2 to be turned on, and the first sub-current module 110 is used to charge the fourth capacitor 113 by the fifth current source 111 and the sixth current source 112, that is, the slope of V1 is 2 times the slope of V41. The fourth sub-current module 220 is configured to charge the fifth capacitor 222 through the seventh current source 221.

The second comparing module 500 is configured to compare the fourth voltage V41 across the fifth capacitor 222 with the fifth voltage V4 across the first capacitor 330, and after V41 is greater than V4 and a target delay time elapses, control the fourth switch 114S2 to be turned off, so that the sixth current source 112 stops charging the fourth capacitor 113; at this time, phase_1 is low and phase_2 is high, and further, the output Q2 of the second RS flip-flop 530 is low and Q2B is high.

A first comparing module 400 for comparing the first voltage V1 and the fifth voltage V4 at both ends of the fourth capacitor 113 and outputting a second clock signal, wherein Phase1 is at a low level, and Phase2 is at a high level after passing through the first inverter 420; and after the fifth voltage is greater than the first voltage and the target delay time passes, the third switch 115 is controlled to be opened so as to stop the fifth current source 111 from charging the fourth capacitor 113, and the second switch 116 is controlled to be closed so as to discharge the fourth capacitor 113.

Through the above example, it can be seen that the second sub-current module and the third sub-current module are used in cooperation, and the first sub-current module and the fourth sub-current module are used in cooperation to alternately generate clock signals, and meanwhile, delay can be compensated for, so that the output frequency of the oscillator circuit is stable.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. An oscillator circuit, comprising: the temperature drift counteracting module comprises a first current module, a second current module, a temperature drift counteracting module, a first comparison module and a second comparison module; the first current module comprises a first sub-current module and a second sub-current module; the second current module comprises a third sub-current module and a fourth sub-current module; the currents provided by the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are the same; the first comparison module is the same as the second comparison module; the temperature drift counteracting module comprises a first current source, a first resistor and a first capacitor, one end of the first current source is connected with the power-on starting module, one ends of the first resistor and the first capacitor are connected with the other end of the first current source, the other ends of the first resistor and the first capacitor are grounded, and the first end, the second end and the first end and the second end of the first comparing module are respectively connected with the other end of the first current source; the resistance value of the first resistor is kept in a constant range at different temperatures;

the third sub-current module and the fourth sub-current module are used for alternately providing a second preset current to generate a third voltage and a fourth voltage; the first preset current is 2 times of the second preset current;

when receiving a starting signal and the first sub-current module stops providing current:

the second comparing module is configured to compare the third voltage with the fifth voltage, and after the third voltage is greater than the fifth voltage and a target delay time passes, control the second sub-current module to provide the second preset current, and control the third sub-current module to stop providing the current;

in the case where the second sub-current module stops supplying current:

The second comparing module is further configured to compare the fourth voltage with the fifth voltage, and after the fourth voltage is greater than the fifth voltage and a target delay time elapses, control the first sub-current module to provide the second preset current, and control the fourth sub-current module to stop providing current;

the first comparison module is further used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time passes, controlling the first sub-current module to stop providing current; the first clock signal and the second clock signal are opposite.

2. The oscillator circuit of claim 1, wherein the first ends of the first sub-current module, the second sub-current module, the third sub-current module, and the fourth sub-current module are each connected to a power-on start-up module; the second ends of the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are grounded;

The third end of the first sub-current module is connected with the first end of the first comparison module; the other end of the first current source is connected with the second end of the first comparison module; the other end of the first current source is connected with the first end of the second comparison module; and the third end of the fourth sub-current module is connected with the second end of the second comparison module.

3. The oscillator circuit of claim 2, wherein upon receipt of a start-up signal and the first sub-current module ceasing to provide current:

in the case where the second sub-current module stops supplying current:

The third end of the fourth sub-current module is communicated with the second end of the second comparison module.

4. The oscillator circuit of claim 3, wherein the second sub-current module comprises a second current source, a third current source, and a second capacitor; the third sub-current module comprises a fourth current source and a third capacitor; the second current source, the third current source and the fourth current source provide the same current;

The second sub-current module is used for charging the second capacitor through the second current source and the third current source;

The third sub-current module is used for charging the third capacitor through the fourth current source after receiving a starting signal;

The second comparing module is configured to compare a third voltage across the third capacitor with a fifth voltage across the first capacitor, and after the third voltage is greater than the fifth voltage and a target delay time elapses, control the second current source to stop providing current to the second capacitor, and control the fourth current source to stop charging the third capacitor;

The first comparison module is used for comparing the fifth voltage at two ends of the first capacitor with the second voltage, outputting a clock signal, and controlling the third current source to stop charging the second capacitor after the fifth voltage is larger than the second voltage and the target delay time passes.

5. The oscillator circuit of claim 4, wherein the second sub-current module further comprises a first switch, a second switch, and a third switch; one end of the second current source and one end of the third current source are connected with the power-on starting module, the other end of the second current source is connected with one end of the first switch, the other end of the third current source and the other end of the first switch are used as a first common end to be connected with one end of the second switch, the other end of the second switch is connected with one end of the third switch and one end of the second capacitor, and the other end of the second capacitor and the other end of the third switch are grounded; the first common end is connected with the second end of the first comparison module, the first end of the first comparison module and the second end of the second comparison module are both connected with the other end of the first current source, and the first end of the second comparison module is connected with the third end of the third sub-current module;

The second comparing module is configured to control the first switch to be turned off after the third voltage is greater than the fifth voltage and a target delay time elapses, so that the second current source stops providing current to the second capacitor;

The first comparison module is used for comparing a fifth voltage at two ends of the first capacitor with the second voltage, outputting a clock signal, controlling the second switch to be opened and controlling the third switch to be closed after the fifth voltage is larger than the second voltage and the target delay time passes, so that the third current source stops charging the second capacitor and discharges the second capacitor.

6. The oscillator circuit of claim 5, wherein the third sub-current module further comprises the first switch, the third switch, and a fourth switch; the third capacitor comprises a first sub-capacitor and a second sub-capacitor; one end of the fourth current source is connected with the power-on starting module, the other end of the fourth current source is connected with one end of the first switch, a second common end of the first sub-capacitor and the second sub-capacitor is connected with the other end of the first switch, the other end of the first sub-capacitor is respectively connected with the first end of the second comparison module and one end of the third switch, the other end of the third switch is connected with the other end of the first current source, the other end of the second sub-capacitor is grounded with one end of the fourth switch, and the other end of the fourth switch is connected with the second common end;

the second comparing module is configured to control, after the third voltage is greater than the fifth voltage and a target delay time has elapsed, the first switch to be opened, and control the fourth switch and the third switch to be closed, so that the fourth current source stops charging the second sub-capacitor, and control the voltages at both ends of the first sub-capacitor to be equal to the fifth voltage.

7. The oscillator circuit of claim 6, wherein the first sub-current module comprises a fifth current source, a sixth current source, and a fourth capacitance; the fourth sub-current module comprises a seventh current source and a fifth capacitor; the currents provided by the fifth current source, the sixth current source and the seventh current source are the same as the currents provided by the second current source, the third current source and the fourth current source;

in the case where the second sub-current module stops supplying current:

the fourth sub-current module is configured to charge the fifth capacitor through the seventh current source;

the second comparing module is configured to compare a fourth voltage at two ends of the seventh current source with the fifth voltage, and after the fourth voltage is greater than the fifth voltage and a target delay time elapses, control the sixth current source to stop providing current to the fourth capacitor, and control the fourth sub-current module to stop providing current to the fifth capacitor;

The first comparison module is used for comparing the first voltage at two ends of the fourth capacitor with the fifth voltage and outputting a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time passes, controlling the fifth current source to stop providing current to the fourth capacitor.

8. The oscillator circuit of claim 7, wherein the first sub-current module further comprises the fourth switch, the third switch, and a second switch, one ends of the fifth current source and the sixth current source are connected to the power-on start module, the other end of the sixth current source is connected to one end of the fourth switch, a third common end of the other end of the fourth switch and the other end of the fifth current source is connected to one end of the third switch, the other end of the third switch is connected to one end of the fourth capacitor and one end of the second switch, respectively, and the other ends of the fourth capacitor and the other end of the second switch are grounded; the third common end is connected with the first end of the first comparison module; the second end of the first comparison module and the first end of the second comparison module are connected with the other end of the first current source; the second end of the second comparison module is connected with the third end of the fourth sub-current module;

The second comparing module is configured to compare a fourth voltage across the fifth capacitor with a fifth voltage across the first capacitor, and after the fourth voltage is greater than the fifth voltage and a target delay time passes, control the fourth switch to be turned off, so that the sixth current source stops charging the fourth capacitor;

The first comparison module is used for comparing the first voltage at two ends of the fourth capacitor with the fifth voltage and outputting a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time passes, controlling the third switch to be opened so as to stop the fifth current source from charging the fourth capacitor, and controlling the second switch to be closed so as to discharge the fourth capacitor.

9. The oscillator circuit of claim 8, wherein the fourth sub-current module further comprises: the fourth switch, the second switch and the first switch, the fifth capacitor comprises a third sub-capacitor and a fourth sub-capacitor; one end of the seventh current source is connected with the power-on starting module, the other end of the seventh current source is connected with one end of the fourth switch, one end of the third sub-capacitor, one end of the fourth sub-capacitor and one end of the first switch are all connected with the other end of the fourth switch, the other end of the first switch and the other end of the third sub-capacitor are grounded, the other end of the fourth sub-capacitor is connected with one end of the second switch, the other end of the second switch is connected with the other end of the first current source, the other end of the fourth sub-capacitor is connected with the second end of the second comparison module, and the first end of the second comparison module is connected with the other end of the first current source;

in the case where the second sub-current module stops supplying current:

The second comparing module is configured to compare a fourth voltage at two ends of the fourth sub-capacitor with the fifth voltage, and after the fourth voltage is greater than the fifth voltage and a target delay time passes, control the fourth switch to be turned off, so that the seventh current source stops charging the third sub-capacitor, and close the second switch and the first switch, so that the voltages at two ends of the fourth sub-capacitor are equal to the fifth voltage.

10. The oscillator circuit of claim 9, wherein the first comparison module comprises: two third switches, two second switches, a first comparator, a first inverter and a first RS trigger;

the second comparison module comprises: two third switches, two second switches, a second comparator, a second inverter and a second RS trigger;

one end of the third switch and one end of the second switch in the first comparison module are respectively connected with the first end of the first comparator; the other end of the third switch is connected with the other end of the first current source; the other end of the second switch is connected with the first common terminal;

The output end of the first comparator is connected with the input end of the first inverter and is used for outputting a clock signal; the output end of the first comparator and the output end of the first inverter are respectively connected with the first RS trigger, the first output end of the first RS trigger is respectively connected with each second switch and the first input end of the first switch control unit, and the second output end of the first RS trigger is respectively connected with each third switch and the first input end of the second switch control unit;

One end of the third switch and one end of the second switch in the second comparison module are respectively connected with the first end of the second comparator; the other end of the third switch is connected with the other end of the fourth sub-capacitor, and the other end of the second switch is connected with the other end of the first current source;

One end of the other third switch and one end of the other second switch are respectively connected with the second end of the second comparator; the other end of the third switch is connected with the other end of the first current source, and the other end of the second switch is connected with the other end of the first sub-capacitor;

The third end of the second comparator is respectively connected with the input end of the second inverter; the third end of the second comparator and the output end of the second inverter are respectively connected with the second RS trigger, the first output end of the second RS trigger is connected with the second input end of the first switch control unit, and the second output end of the second RS trigger is connected with the second input end of the second switch control unit;

The second switch control unit is used for controlling the disconnection or connection of each fourth switch according to the output signal of the second output end of the first RS trigger and the output signal of the first output end of the second RS trigger;

The first RS trigger is used for transmitting an output signal of a first output end of the first RS trigger to each second switch so as to enable the second switch to be disconnected or connected; and transmitting an output signal of the second output terminal of the first RS flip-flop to each of the third switches to turn the third switch off or on.

11. The oscillator circuit of claim 10, wherein the first RS flip-flop and the second RS flip-flop are and gate flip-flops.

12. The oscillator circuit according to any one of claims 1 to 11, wherein the first resistor includes a first sub resistor and a second sub resistor, one end of the first sub resistor is connected to the other end of the first signal source, the other end of the first sub resistor is connected to one end of the second sub resistor, the other end of the second sub resistor is grounded, the first sub resistor is a positive temperature coefficient resistor, and the second sub resistor is a negative temperature coefficient resistor.