CN115985380B - FeFET array data verification method based on digital circuit control - Google Patents

Abstract

The invention discloses a FeFET array data verification method based on digital circuit control. The method constructs a storage array composed of m*n ferroelectric transistor FeFETs and its peripheral circuit ferroelectric transistor FeFET array, and then stores and caches the data according to the weight data. Design the check code coding rules based on the data in the data, and then use the digital circuit to complete the check code generation and read and write control; realize two check methods, pre-calculation check and test phase check, to achieve quick check before calculation and The target of the dead point determination. The invention can effectively reduce the data reading time, power consumption and data in the data verification process stored in the FeFET array, and bring out the characteristics of the internal calculation of the FeFET array.

Description

A FeFET array data verification method based on digital circuit control

technical field

The invention relates to the field of memory-computing integrated chip design, in particular to a method for verifying FeFET array data based on digital circuit control.

Background technique

With the advancement of computer technology, the demand for non-volatile memory is increasing, its reading and writing speed is required to be faster and faster, and its power consumption is more and more in line with user requirements. However, traditional non-volatile memory such as EEPROM, FLASH, etc. have been difficult to meet these requirements. Traditional mainstream semiconductor memory can be divided into two categories: volatile and non-volatile. Volatile memory includes static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM lose saved data when power is lost. While RAM is easy to use and performs well, it has the disadvantage of data loss.

Ferroelectric memory is a new type of memory based on the improvement of semiconductor technology, which has some unique characteristics. Ferroelectric memory is compatible with all the functions of RAM and is a non-volatile memory similar to ROM. In other words, ferroelectric memory bridges the gap between these two storage types, a type of non-volatile RAM. Compared with traditional non-volatile memory, it has attracted much attention due to its low power consumption, fast read and write speed, and strong radiation resistance. Ferroelectric field effect transistor, as a new type of high-speed, low-power device, naturally has the advantage of realizing the integrated storage and computing architecture.

With the wide application of neural network memory-computing integrated structure, more and more new storage devices have been deeply studied in the hardware implementation of neural network. The ferroelectric material used in ferroelectric transistor FeFET memory can quickly switch between two polarization states, has faster write/erase speed, its manufacturing process is simple, lower power consumption and can be used at lower voltage down to work. FeFET, as a storage technology with many advantages, has been continuously deepened in research and application in the hardware implementation of neural networks.

At present, data storage technology based on the ferroelectric effect of FeFET array ferroelectric crystals has been widely used. Through the cooperation of digital circuits, the use of FeFET array matrix multiplication in-memory calculation can effectively realize the hardware acceleration of neural network algorithms. .

In order to ensure the correctness of the calculation results during the in-memory calculation process, the data stored in the FeFET array needs to be verified before starting the calculation. However, in the prior art, the data stored in the FeFET array adopts the The verification method is to read all the data in the array, and then directly compare them with the data stored in the digital circuit one by one. This method requires multiple times of data reading, comparison time and power consumption.

Contents of the invention

In view of the deficiencies in the prior art, the purpose of this application is to provide a method for verifying data of FeFET arrays based on digital circuit control.

According to the first aspect of the embodiment of the present application, there is provided a FeFET array data verification method based on digital circuit control, which is a method designed by digital circuits to perform in-memory calculations using the characteristics of FeFET array in-memory calculations. A FeFET array data verification method based on digital circuit control, the method comprising the following steps:

(1) Construct a storage array consisting of m rows and n columns of FeFETs;

(2) Design a check code encoding rule according to the data in the weight data storage cache, and the check code encoding rule includes a binary check code encoding rule and a multi-value check code encoding rule;

(3) After receiving the verification command, first read the data in the weight data storage cache, and then generate the corresponding verification code through the binary or multi-value verification code coding rules according to the data in the weight data storage cache, and then The address and check code corresponding to the data are written to the corresponding point of the array, and the total current value of the column is read after the writing is completed; if the total current value is m*i, where m is the number of rows of the storage array, and the current i is 70nA, it means the verification is correct, the output verification correct signal is pulled high and the next column of verification code is sent, when all the verification is completed and the verification is correct, exit the verification; if the total current value is not m*i, the output verification If the error signal is pulled high, it means that the corresponding column is incorrectly verified. Rewrite the column data and repeat the current step for verification. If all the verification is completed and the verification is correct, the verification will be exited.

Further, the binary check code encoding rule is for binary value storage of a single FeFET device, and performs binary weight check code encoding according to the stored values of 0 and 1 in a single FeFET device.

Further, the multi-value check code encoding rule is aimed at multi-value storage for a single FeFET device. The stored value of a single FeFET device is 0 to N. Two encoding rules are used for the check code encoding. If the stored value is 0 Then the inversion is 1, and if the stored value is non-zero, the check code is returned to 0, so as to obtain a check code with multi-valued weights.

Further, the storage of the FeFET array has a non-lost characteristic, and the stored data needs to be verified before calculation; the FeFET array has the characteristics of in-memory calculation, and when the data is read out, it is designed through an algorithm and stored in the memory. Check the stored data.

Further, the current value read in the FeFET array is converted into a data value through a mapping relationship, and at the same time, the result and the control signal are encoded into the data value for transmission.

Further, in the verification process, the verification code is applied according to the memory calculation characteristics of the FeFET array, and the read voltage is applied and the current sum is detected. According to the mapping relationship, the current sum represents the result of the multiplication and addition calculation, so as to judge the corresponding column. Whether the multiplication and accumulation value of the verification code and the weight meets the verification result.

Further, the dead point collation specifically includes: selecting and reading out the column data corresponding to the verification error, comparing the column data corresponding to the verification error with the corresponding column data in the corresponding cache one by one, finding the corresponding error point and performing multiple times of checking. Write and read out the column; if errors occur repeatedly at the wrong position point, it is considered that there is a bad point at the position point where errors occur repeatedly.

According to the second aspect of the embodiment of the present application, a FeFET array data verification device based on digital circuit control is provided, including:

The row encoding and decoding module is used to select the row address in the FeFET array, and select the bit line according to the row address and operation and verification, and apply a read voltage to the selected bit line;

The column encoding and decoding module is used to select the column address in the FeFET array, and select the bit line according to the column address and operation and verification, and apply a read voltage to the selected bit line;

A data check module, used to check and compare the read data rows;

The read-write control module is used to apply the read-write voltage to the bit line to obtain the read current; when controlling the read operation, the read voltage applied to the selected bit line by the row codec module and the column codec module is used to read the selected unit The electric current; According to the write voltage applied to the selected bit line by the row codec module and the column codec module to read the current of the selected cell during the control write operation;

Weight data storage cache module: used to cache and back up the data of FeFET array.

According to a third aspect of the embodiments of the present application, a terminal is provided, including:

one or more processors;

memory for storing one or more programs;

When the one or more programs are executed by the one or more processors, the one or more processors are made to implement the above-mentioned FeFET array data verification method based on digital circuit control.

According to a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which computer instructions are stored, and when the instructions are executed by a processor, the above-mentioned FeFET array data verification method based on digital circuit control is implemented.

Compared with the prior art, the beneficial effect of the present application is: the present application is suitable for completing the storage of the weight of the neural network and the data verification in the process of multiplying and accumulating calculation by using the FeFET array, effectively reducing the data verification value stored in the FeFET array. The data reading time and power consumption of the process can reduce the time and power consumption of data comparison one by one, effectively bring out the characteristics of FeFET array memory computing, and can make full use of the memory computing characteristics of FeFET array during the test process. Quickly screen out possible bad points through digital circuit control, reduce the number of physical tests, and improve the efficiency of array testing.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

Fig. 1 is a schematic diagram of a verification process of a FeFET array data verification method based on digital circuit control shown according to an exemplary embodiment;

Fig. 2 is a schematic diagram of binary data verification of a FeFET array data verification method based on digital circuit control shown according to an exemplary embodiment;

Fig. 3 is a schematic diagram of multi-valued data verification of a FeFET array data verification method based on digital circuit control shown according to an exemplary embodiment;

Fig. 4 is a schematic structural diagram of a FeFET array data verification device based on digital circuit control shown according to an exemplary embodiment;

Fig. 5 is a schematic diagram of a terminal according to an exemplary embodiment.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word "if" as used herein may be interpreted as "at" or "when" or "in response to a determination."

The present invention will be described in detail below according to the accompanying drawings and preferred embodiments, and the purpose and effect of the present invention will become clearer. It should be understood that the specific embodiments described here are only used to explain the present invention, and are not intended to limit the present invention.

First give an explanation of the technical terms:

FeFET: Metal-Ferroelectric-Semiconductor FET ferroelectric transistor;

DRAM: Digitally Recorded Announcement Machine dynamic random access memory;

ROM: read only memory read-only memory.

This embodiment provides a FeFET array data verification method based on digital circuit control. The specific execution process of the method is as follows:

Step 1: First construct a storage array composed of m*n ferroelectric transistors FeFETs, the main principle of which is: use a hafnium oxide-based High-K (high-K) gate dielectric + Metal Gate (metal gate) on the existing logic transistors Gate) electrode stacking technology, the gate insulator is modified into a ferroelectric transistor FeFET with ferroelectric properties. Although the obtained ferroelectric transistor FeFET has the same structure, it also has scalability, low power and non-volatility. Characteristics; use the ferroelectric effect of the ferroelectric crystal to realize data storage; the ferroelectric effect refers to a stable state in which the central atoms of the crystal move under the action of the electric field when a certain electric field is applied on the ferroelectric crystal; When the electric field is removed from the ferroelectric crystal, the central atom will remain in its original position; this is because the middle layer of the ferroelectric crystal is a high-energy level, and the central atom cannot cross the high-energy level to another stable position without gaining external energy , so the ferroelectric transistor FeFET array does not require voltage to maintain data, nor does it need periodic refresh like DRAM; since the ferroelectric effect is a polarization characteristic inherent in ferroelectric crystals, and has nothing to do with electromagnetic effects, so iron The content stored in the transistor FeFET array will not be affected by external conditions (such as magnetic field factors), and can be used like ordinary ROM memory. The ferroelectric transistor FeFET array storage has non-volatile storage characteristics and unlimited durability, which is very suitable for Applications of various embedded chips. A row codec module and a column codec module are constructed on the periphery of the FeFET array, and the row codec module and column codec module are used to select the data, address and control signal transmitted from the read-write control module according to the row address and column address. Ferroelectric transistor FeFET unit, and then respectively write the weight data and check code into the storage array to realize the storage of weight and write of check code; in the data verification of FeFET array storage, according to the weight The data in the data storage cache is designed with check code coding rules.

Refer to the schematic diagram of binary data verification in Figure 2. The storage value of a single FeFET device is binary storage, and its storage values are 0 and 1. The verification code code adopts the method of data inversion to obtain the verification code of the binary weight. The corresponding calculation results of code verification and weight in the entire column are all 0. Refer to the schematic diagram of multi-value data verification in Figure 3. The storage value of a single FeFET device is multi-value storage, and its storage value is 0~N. 0 encoding rule to obtain the check code of the multi-valued weight. The design of this check code makes the calculation result of the check code and the corresponding weight value both 0, and the corresponding current value is i (in this embodiment, the leakage current of a single device is 70nA), then the m values in the corresponding column are The final measured total current value is m*i; after the verification is completed, if the total current value is m*i, it means that the calibration of this column is correct; if the total current value is not m*i, it means that the calibration of this column is incorrect. After the data storage is completed, start data verification according to the data storage type (binary data or multi-value weight). test efficiency.

Step 2: Before the calculation starts or during the test, after receiving the verification command, first read the weight data in the weight data storage cache, and then write the corresponding address and verification code into the array through the read-write control module At the corresponding point, read the total current value of the column after the writing is completed, exit the verification mode after all verification is completed and the verification is correct; if the verification current is wrong, the output verification error signal is pulled high, and the column data is rewritten . Referring to the schematic diagram of the verification process in Figure 1, before the calculation starts or during the test, after receiving the verification command, first read the weight data in the weight data storage cache, and then pass the binary value according to the data in the weight data storage cache. , The multi-value check code coding rule generates the corresponding check code, and then writes the corresponding address and check code to the corresponding point of the array through the read-write control module, and reads the total current value of the column after the writing is completed. If the total current value is the set current value m*i (in this embodiment, m is the number of rows of the memory array, and the leakage current i of a single device is 70nA), it means that the multiplication and accumulation sum of the calculation results is 0. If the verification is correct Then the output verification correct signal is pulled high, indicating that the corresponding column verification is correct, and then the read-write control module sends the next column verification code after receiving the verification correct signal, and exits the verification mode when all verification is completed and the verification is correct; If the verification current is wrong, the output verification error signal is pulled high, indicating that the corresponding column verification error, and then the read-write control module rewrites the column data after receiving the verification error signal.

Step 3: Refer to the schematic diagram of the verification process in Figure 1. During the test phase, a selection control signal is applied to the test board through the digital circuit; after receiving the verification error signal, if the bad point verification is to be performed, the read-write control module selects the readout The data in this column is transmitted to the data verification module to compare the data in this column with the data in the corresponding cache one by one, find out the corresponding error point and write and read the column multiple times at the same time. If there are repeated errors at the wrong position point, it is considered that there is a bad point at this point. The dead point can be physically tested. Before the test, use a multimeter with an oscilloscope to check whether the control signal of the development board is correct, whether the stimulus is applied correctly, and the connectivity between the stimulus application ports and pins, etc., so as to ensure that the test environment can Normal operation, you can use the high-precision test capability of the test equipment (4200-SCS or B1500 and other equipment can be used in this embodiment) to perform DC scanning on the device to obtain accurate current and voltage characteristics. If the expected IV characteristics are not met, then Indicates that the point is indeed a bad point. The advantage of this design is that it can make full use of the in-memory computing characteristics of the FeFET array, and quickly screen out possible bad points through digital circuit control, which can reduce the number of physical tests and improve the efficiency of array testing.

Corresponding to the aforementioned embodiments of the digital circuit control-based FeFET array data verification method, the present application also provides an embodiment of a digital circuit-based FeFET array data verification device.

Fig. 4 is a schematic structural diagram of a FeFET array data verification device based on digital circuit control according to an exemplary embodiment. Referring to Figure 4, the device may include:

FeFET array, ferroelectric transistor FeFET is composed of a gate, a source terminal, a drain terminal and a substrate; the gate of the ferroelectric transistor is composed of a metal layer, a ferroelectric layer and an insulating layer; a positive voltage is applied to the gate Or a negative voltage, which will cause the polarization of the ferroelectric layer to flip positively or negatively. When the voltage is removed, the polarization state remains unchanged; the ferroelectric transistor realizes 0/1 storage through the polarization reversal of the ferroelectric material.

The row encoding and decoding module selects a row address in the FeFET array, selects a bit line according to the row address and operation and verification and test mode, and applies a read voltage to the selected bit line.

The column encoding and decoding module selects a column address in the FeFET array, selects a bit line according to the column address and operation and verification and test mode, and applies a read voltage to the selected bit line.

The data check module, in the test mode, checks and compares the read data rows; the comparison method is to read the error column data and write it into the comparison register, and back up the data read of the corresponding column in the digital circuit weight data storage cache module. Out, compare bit by bit, count at the same time for different values, compare inconsistent values and output their corresponding count values.

The read-write control module applies a read-write voltage to a corresponding bit line and obtains a read current. When controlling the read operation, apply a read voltage to the selected bit line according to the row and column codec module to read the current of the selected cell; when controlling the write operation, apply a write voltage to the selected bit line according to the row and column codec module to read The current of the selected unit.

Weight data storage cache module: cache and back up the data to be written into the FeFET array.

Among them, the read-write control module is connected to the row encoding module through the row data address line and the data line; the read-write control module is connected to the column encoding module through the row data address line and the data line; the row encoding module is connected to the FeFET array through the row read-write line The column encoding module is connected to the FeFET array through the row and column writing lines; the read-write control module is connected to the weight data storage cache module and the data verification module through the data transmission line. The row codec module and the column codec module write the data, address and control signal transmitted by the read-write control module to the corresponding position according to the row address and column address mapping, and at the same time convert the current value read in the FeFET array through the mapping relationship as a data value, and encode the result and control signal as a data value and transmit it to the read-write control module.

Regarding the apparatus in the foregoing embodiments, the specific manner in which each module executes operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

As for the device embodiment, since it basically corresponds to the method embodiment, for related parts, please refer to the part description of the method embodiment. The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this application. It can be understood and implemented by those skilled in the art without creative effort.

Correspondingly, the present application also provides a terminal, including: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, The one or more processors are made to implement the above-mentioned FeFET array data verification method based on digital circuit control. As shown in Figure 5, it is a hardware structure diagram of any device with data processing capability where the FeFET array data verification method based on digital circuit control provided by the embodiment of the present application, except for the processor shown in Figure 5, In addition to memory, DMA controller, disk, and non-volatile memory, any device with data processing capability in which the device in the embodiment is usually based on the actual function of any device with data processing capability may also include other hardware. This will not be repeated here.

Correspondingly, the present application also provides a computer-readable storage medium, on which computer instructions are stored, and when the instructions are executed by a processor, the above-mentioned FeFET array data verification method based on digital circuit control is implemented. The computer-readable storage medium may be an internal storage unit of any device capable of data processing described in any of the foregoing embodiments, such as a hard disk or a memory. The computer-readable storage medium may also be an external storage device of the wind turbine, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), an SD card, a flash memory card (FlashCard), etc. . Further, the computer-readable storage medium may include both an internal storage unit of any device capable of data processing and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by any device capable of data processing, and may also be used to temporarily store data that has been output or will be output.

Other embodiments of the present application will readily occur to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any modification, use or adaptation of the application, these modifications, uses or adaptations follow the general principles of the application and include common knowledge or conventional technical means in the technical field not disclosed in the application .

It should be understood that the present application is not limited to the precise constructions which have been described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof.

Claims (10)

1. The FeFET array data verification method based on digital circuit control is characterized by comprising the following steps:

(1) Constructing a memory array consisting of m rows and n columns of FeFETs;

(2) Designing a check code coding rule according to data in a weight data storage cache of the neural network, wherein the check code coding rule comprises a binary check code coding rule and a multi-value check code coding rule;

(3) After receiving the check command, firstly reading the data in the weight data storage cache, then generating a corresponding check code according to the data in the weight data storage cache through a binary or multi-value check code coding rule, writing an address corresponding to the data and the check code into a corresponding point of the array, and reading the total current value of the column after the writing is completed; if the total current value is m x i, wherein m is the number of rows of the memory array, and the current i is 70nA, the verification is correct, a verification correct signal is output to be pulled up, the next row of verification codes is sent, and after all verification is completed and the verification is correct, the verification is stopped; if the total current value is not m.i, outputting a verification error signal to be pulled high to indicate that the corresponding row is in a verification error, rewriting the row data, repeating the current step for verification, if all the verification is completed and the verification is correct, exiting the verification, and if the verification is still in an error, performing bad point verification.

2. The digital circuit control-based FeFET array data verification method of claim 1, wherein the binary verification code encoding rule is binary-stored for FeFET individual device storage values, and binary-weighted verification code encoding is performed according to FeFET individual device storage values of 0 and 1.

3. The method for verifying the FeFET array data based on digital circuit control according to claim 1, wherein the multi-value verification code coding rule is that the storage value of each FeFET is multi-value storage, the storage value of each FeFET is 0-N, the verification code coding adopts two coding rules, the inverse is 1 if the storage value is 0, and the verification code is classified as 0 if the storage value is non-0, so as to obtain the verification code of multi-value weight.

4. The method for verifying data of the FeFET array based on digital circuit control according to claim 1, wherein the storage of the FeFET array has a non-missing characteristic, and the stored data is verified before calculation; the FeFET array has in-memory computing characteristics, and memory data verification is performed in memory through algorithm design under the condition of data reading.

5. The method for verifying data of a FeFET array based on digital circuit control of claim 1, wherein the current values read in the FeFET array are converted into data values by a mapping relationship, and the result and control signals are encoded into the data values for transmission.

6. The method for verifying the FeFET array data based on digital circuit control according to claim 4, wherein in the verification process, the verification code is applied with a read voltage according to the memory calculation characteristic of the FeFET array, the sum of currents is detected, and the sum of currents represents the result of the multiply-add calculation according to the mapping relation, so as to judge whether the multiply-add value of the verification code and the weight of the corresponding column meets the verification result.

7. The digital circuit control-based FeFET array data verification method of claim 1, wherein the dead pixel verification specifically comprises: selecting and reading out corresponding column data of the check errors, comparing the corresponding column data of the check errors with the corresponding column data in the corresponding cache one by one, finding out corresponding error points and writing in and reading out the column for a plurality of times; if the position point with the error repeatedly appears the error, the position point with the error repeatedly appears a bad point.

8. A FeFET array data verification device based on digital circuit control, comprising:

the row coding and decoding module is used for selecting a row address in the FeFET array, selecting a bit line according to the row address and operation and verification, and applying a read voltage to the selected bit line;

the column coding and decoding module is used for selecting a column address in the FeFET array, selecting a bit line according to the column address and operation and verification, and applying a read voltage to the selected bit line;

the data verification module is used for performing verification comparison on the read data line;

the read-write control module is used for applying read-write voltage to the bit line to obtain read current; when controlling the read operation, reading the current of the selected unit according to the read voltage applied to the selected bit line by the row encoding and decoding module and the column encoding and decoding module; when the write operation is controlled, the write voltage applied to the selected bit line by the row encoding and decoding module and the column encoding and decoding module is used for reading the current of the selected unit;

the weight data storage and caching module: and the neural network weight data of the FeFET array is cached and backed up.

9. A terminal, comprising:

one or more processors;

a memory for storing one or more programs;

the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any of claims 1-7.

10. A computer readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the steps of the method of any of claims 1-7.

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